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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.iir_filter.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lpp_fifo IS
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GENERIC(
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tech : INTEGER := 0;
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Mem_use : INTEGER := use_RAM;
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DataSz : INTEGER RANGE 1 TO 32 := 8;
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AddrSz : INTEGER RANGE 2 TO 12 := 8
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);
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PORT(
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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--
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reUse : IN STD_LOGIC;
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--IN
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ren : IN STD_LOGIC;
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rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
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--OUT
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wen : IN STD_LOGIC;
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wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
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empty : OUT STD_LOGIC;
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full : OUT STD_LOGIC;
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almost_full : OUT STD_LOGIC
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);
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END ENTITY;
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ARCHITECTURE ar_lpp_fifo OF lpp_fifo IS
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SIGNAL sFull : STD_LOGIC;
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SIGNAL sFull_s : STD_LOGIC;
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SIGNAL sEmpty_s : STD_LOGIC;
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SIGNAL sEmpty : STD_LOGIC;
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SIGNAL sREN : STD_LOGIC;
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SIGNAL sWEN : STD_LOGIC;
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SIGNAL sRE : STD_LOGIC;
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SIGNAL sWE : STD_LOGIC;
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SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL Waddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL Raddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL almost_full_s : STD_LOGIC;
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SIGNAL almost_full_r : STD_LOGIC;
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BEGIN
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--==================================================================================
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-- /!\ syncram_2p Write et Read actif a l'�tat haut /!\
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-- A l'inverse de RAM_CEL !!!
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--==================================================================================
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memRAM : IF Mem_use = use_RAM GENERATE
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SRAM : syncram_2p
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GENERIC MAP(tech, AddrSz, DataSz)
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PORT MAP(CLK, sRE, Raddr_vect, rdata, CLK, sWE, Waddr_vect, wdata);
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END GENERATE;
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--==================================================================================
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memCEL : IF Mem_use = use_CEL GENERATE
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CRAM : RAM_CEL
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GENERIC MAP(DataSz, AddrSz)
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PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, CLK, rstn);
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END GENERATE;
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--==================================================================================
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--=============================
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-- Read section
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--=============================
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sREN <= REN OR sEmpty;
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sRE <= NOT sREN;
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sEmpty_s <= '0' WHEN ReUse = '1' else
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'1' WHEN sEmpty = '1' AND Wen = '1' ELSE
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'1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
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'0';
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Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1);
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PROCESS (clk, rstn)
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BEGIN
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IF(rstn = '0')then
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Raddr_vect <= (OTHERS => '0');
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sempty <= '1';
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ELSIF(clk'EVENT AND clk = '1')then
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sEmpty <= sempty_s;
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IF(sREN = '0' and sempty = '0')then
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Raddr_vect <= Raddr_vect_s;
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END IF;
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END IF;
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END PROCESS;
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--=============================
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-- Write section
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--=============================
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sWEN <= WEN OR sFull;
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sWE <= NOT sWEN;
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sFull_s <= '1' WHEN ReUse = '1' else
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'1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
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'1' WHEN sFull = '1' AND REN = '1' ELSE
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'0';
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almost_full_s <= '1' WHEN STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +2) = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
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'1' WHEN almost_full_r = '1' AND WEN = REN ELSE
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'0';
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Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1);
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PROCESS (clk, rstn)
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BEGIN
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IF(rstn = '0')then
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Waddr_vect <= (OTHERS => '0');
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sfull <= '0';
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almost_full_r <= '0';
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ELSIF(clk'EVENT AND clk = '1')then
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sfull <= sfull_s;
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almost_full_r <= almost_full_s;
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IF(sWEN = '0' and sfull = '0')THEN
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Waddr_vect <= Waddr_vect_s;
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END IF;
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END IF;
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END PROCESS;
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almost_full <= almost_full_s;
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full <= sFull_s;
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empty <= sEmpty_s;
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END ARCHITECTURE;
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