# HG changeset patch # User pellion # Date 2014-09-17 09:18:45 # Node ID 92057c9e9a3b8f2c2697aaeb0b5926514c05e3fd # Parent b764c62fa31455b2b103452367da657d7740931f temp diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -428,7 +428,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"000118") -- aa.bb.cc version + top_lfr_version => X"00011B") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => reset, diff --git a/designs/Validation_FIFO/Makefile b/designs/Validation_FIFO/Makefile --- a/designs/Validation_FIFO/Makefile +++ b/designs/Validation_FIFO/Makefile @@ -13,7 +13,7 @@ XSTOPT= SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd VHDLSYNFILES= -VHDLSIMFILES= tb.vhd +VHDLSIMFILES= FIFO_Verif.vhd tb.vhd SIMTOP=testbench #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc diff --git a/designs/Validation_FIFO/run.do b/designs/Validation_FIFO/run.do --- a/designs/Validation_FIFO/run.do +++ b/designs/Validation_FIFO/run.do @@ -1,3 +1,5 @@ +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO_control.vhd +vcom -quiet -93 -work work FIFO_Verif.vhd vcom -quiet -93 -work work tb.vhd vsim work.testbench diff --git a/designs/Validation_FIFO/tb.vhd b/designs/Validation_FIFO/tb.vhd --- a/designs/Validation_FIFO/tb.vhd +++ b/designs/Validation_FIFO/tb.vhd @@ -13,236 +13,135 @@ ENTITY testbench IS END; ARCHITECTURE behav OF testbench IS + + COMPONENT fifo_verif + PORT ( + verif_clk : OUT STD_LOGIC; + verif_rstn : OUT STD_LOGIC; + verif_ren : OUT STD_LOGIC; + verif_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + verif_wen : OUT STD_LOGIC; + verif_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + verif_empty : IN STD_LOGIC; + verif_full : IN STD_LOGIC; + verif_almost_full : IN STD_LOGIC; + error_now : OUT STD_LOGIC; + error_new : OUT STD_LOGIC); + END COMPONENT; ----------------------------------------------------------------------------- - -- Common signal - SIGNAL clk : STD_LOGIC := '0'; - SIGNAL rstn : STD_LOGIC := '0'; - SIGNAL run : STD_LOGIC := '0'; - + SIGNAL CEL_clk : STD_LOGIC := '0'; + SIGNAL CEL_rstn : STD_LOGIC := '0'; + ----------------------------------------------------------------------------- + SIGNAL CEL_data_ren : STD_LOGIC; + SIGNAL CEL_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL CEL_data_wen : STD_LOGIC; + SIGNAL CEL_wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL CEL_full_almost : STD_LOGIC; + SIGNAL CEL_full : STD_LOGIC; + SIGNAL CEL_empty : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL CEL_error_now : STD_LOGIC; + SIGNAL CEL_error_new : STD_LOGIC; ----------------------------------------------------------------------------- - SIGNAL full_almost : STD_LOGIC; - SIGNAL full : STD_LOGIC; - SIGNAL data_wen : STD_LOGIC; - SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); - - SIGNAL empty : STD_LOGIC; - SIGNAL data_ren : STD_LOGIC; - SIGNAL data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_out_obs : STD_LOGIC_VECTOR(31 DOWNTO 0); - - SIGNAL empty_reg : STD_LOGIC; - SIGNAL full_reg : STD_LOGIC; - + ----------------------------------------------------------------------------- + SIGNAL RAM_clk : STD_LOGIC := '0'; + SIGNAL RAM_rstn : STD_LOGIC := '0'; ----------------------------------------------------------------------------- - TYPE DATA_CHANNEL IS ARRAY (0 TO 128-1) OF STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_in : DATA_CHANNEL; - + SIGNAL RAM_data_ren : STD_LOGIC; + SIGNAL RAM_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL RAM_data_wen : STD_LOGIC; + SIGNAL RAM_wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL RAM_full_almost : STD_LOGIC; + SIGNAL RAM_full : STD_LOGIC; + SIGNAL RAM_empty : STD_LOGIC; ----------------------------------------------------------------------------- - CONSTANT RANDOM_VECTOR_SIZE : INTEGER := 1+1; --READ + WRITE + CHANNEL_READ + CHANNEL_WRITE - CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : REAL := (2**RANDOM_VECTOR_SIZE)*1.0; - SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); - -- - SIGNAL rand_ren : STD_LOGIC; - SIGNAL rand_wen : STD_LOGIC; - - SIGNAL pointer_read : INTEGER; - SIGNAL pointer_write : INTEGER := 0; - - SIGNAL error_now : STD_LOGIC; - SIGNAL error_new : STD_LOGIC; - - SIGNAL read_stop : STD_LOGIC; + SIGNAL RAM_error_now : STD_LOGIC; + SIGNAL RAM_error_new : STD_LOGIC; + ----------------------------------------------------------------------------- + BEGIN - all_J : FOR J IN 0 TO 127 GENERATE - data_in(J) <= STD_LOGIC_VECTOR(to_unsigned(J*2+1, 32)); - END GENERATE all_J; - - ----------------------------------------------------------------------------- - lpp_fifo_1 : lpp_fifo + lpp_fifo_CEL : lpp_fifo GENERIC MAP ( tech => 0, Mem_use => use_CEL, + EMPTY_THRESHOLD_LIMIT => 1, + FULL_THRESHOLD_LIMIT => 1, DataSz => 32, AddrSz => 8) PORT MAP ( - clk => clk, - rstn => rstn, + clk => CEL_clk, + rstn => CEL_rstn, reUse => '0', - ren => data_ren, - rdata => data_out, - wen => data_wen, - wdata => wdata, - empty => empty, - full => full, - almost_full => full_almost); - + ren => CEL_data_ren, + rdata => CEL_data_out, + wen => CEL_data_wen, + wdata => CEL_wdata, + empty => CEL_empty, + full => CEL_full, + full_almost => CEL_full_almost, + empty_threshold => OPEN, + full_threshold => OPEN); ----------------------------------------------------------------------------- - + fifo_verif_CEL : fifo_verif + PORT MAP ( + verif_clk => CEL_clk, + verif_rstn => CEL_rstn, + verif_ren => CEL_data_ren, + verif_rdata => CEL_data_out, + verif_wen => CEL_data_wen, + verif_wdata => CEL_wdata, + verif_empty => CEL_empty, + verif_full => CEL_full, + verif_almost_full => CEL_full_almost, + error_now => CEL_error_now, + error_new => CEL_error_new + ); + ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- - -- READ + lpp_fifo_RAM : lpp_fifo + GENERIC MAP ( + tech => 0, + Mem_use => use_RAM, + EMPTY_THRESHOLD_LIMIT => 1, + FULL_THRESHOLD_LIMIT => 1, + DataSz => 32, + AddrSz => 8) + PORT MAP ( + clk => RAM_clk, + rstn => RAM_rstn, + reUse => '0', + ren => RAM_data_ren, + rdata => RAM_data_out, + wen => RAM_data_wen, + wdata => RAM_wdata, + empty => RAM_empty, + full => RAM_full, + full_almost => RAM_full_almost, + empty_threshold => OPEN, + full_threshold => OPEN); ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - empty_reg <= '1'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - empty_reg <= empty; - END IF; - END PROCESS; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - data_out_obs <= (OTHERS => '0'); - - pointer_read <= 0; - error_now <= '0'; - error_new <= '0'; - - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - error_now <= '0'; - IF empty_reg = '0' THEN - IF data_ren = '0' THEN - --IF data_ren_and_not_empty = '0' THEN - error_new <= '0'; - data_out_obs <= data_out; - - IF pointer_read < 127 THEN - pointer_read <= pointer_read + 1; - ELSE - pointer_read <= 0; - END IF; - - IF data_out /= data_in(pointer_read) THEN - error_now <= '1'; - error_new <= '1'; - END IF; - END IF; - - END IF; - END IF; - END PROCESS; + fifo_verif_RAM : fifo_verif + PORT MAP ( + verif_clk => RAM_clk, + verif_rstn => RAM_rstn, + verif_ren => RAM_data_ren, + verif_rdata => RAM_data_out, + verif_wen => RAM_data_wen, + verif_wdata => RAM_wdata, + verif_empty => RAM_empty, + verif_full => RAM_full, + verif_almost_full => RAM_full_almost, + error_now => RAM_error_now, + error_new => RAM_error_new + ); ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- WRITE - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - full_reg <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - full_reg <= full; - END IF; - END PROCESS; - - proc_verif : PROCESS (clk, rstn) - BEGIN -- PROCESS proc_verif - IF rstn = '0' THEN -- asynchronous reset (active low) - pointer_write <= 0; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - IF data_wen = '0' THEN - IF full_reg = '0' THEN - IF pointer_write < 127 THEN - pointer_write <= pointer_write+1; - ELSE - pointer_write <= 0; - END IF; - END IF; - END IF; - END IF; - END PROCESS proc_verif; - - wdata <= data_in(pointer_write) WHEN data_wen = '0' ELSE (OTHERS => 'X'); - ----------------------------------------------------------------------------- - - - - ----------------------------------------------------------------------------- - clk <= NOT clk AFTER 5 ns; -- 100 MHz - ----------------------------------------------------------------------------- - WaveGen_Proc : PROCESS - BEGIN - -- insert signal assignments here - WAIT UNTIL clk = '1'; - read_stop <= '0'; - rstn <= '0'; - run <= '0'; - WAIT UNTIL clk = '1'; - WAIT UNTIL clk = '1'; - WAIT UNTIL clk = '1'; - rstn <= '1'; - WAIT UNTIL clk = '1'; - WAIT UNTIL clk = '1'; - WAIT UNTIL clk = '1'; - WAIT UNTIL clk = '1'; - WAIT UNTIL clk = '1'; - run <= '1'; - WAIT UNTIL clk = '1'; - WAIT UNTIL clk = '1'; - WAIT UNTIL clk = '1'; - WAIT UNTIL clk = '1'; - WAIT FOR 10 us; - read_stop <= '1'; - WAIT FOR 10 us; - read_stop <= '0'; - WAIT FOR 80 us; - REPORT "*** END simulation ***" SEVERITY failure; - WAIT; - END PROCESS WaveGen_Proc; - ----------------------------------------------------------------------------- - - - - ----------------------------------------------------------------------------- - -- RANDOM GENERATOR - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - VARIABLE seed1, seed2 : POSITIVE; - VARIABLE rand1 : REAL; - VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - random_vector <= (OTHERS => '0'); - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - UNIFORM(seed1, seed2, rand1); - RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR( - to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)), - RANDOM_VECTOR_VAR'LENGTH) - ); - random_vector <= RANDOM_VECTOR_VAR; - END IF; - END PROCESS; - ----------------------------------------------------------------------------- - rand_wen <= random_vector(1); - rand_ren <= random_vector(0); - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - data_wen <= '1'; - data_ren <= '1'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - data_wen <= rand_wen; - IF read_stop = '0' THEN - data_ren <= rand_ren; - ELSE - data_ren <= '1'; - END IF; - END IF; - END PROCESS; - ----------------------------------------------------------------------------- - - - END; diff --git a/designs/Validation_FIFO/wave.do b/designs/Validation_FIFO/wave.do --- a/designs/Validation_FIFO/wave.do +++ b/designs/Validation_FIFO/wave.do @@ -1,23 +1,42 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate -expand -group COMMON /testbench/clk -add wave -noupdate -expand -group COMMON /testbench/rstn -add wave -noupdate -expand -group COMMON /testbench/run -add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/full_almost -add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/full -add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/data_wen -add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/wdata -add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/empty -add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/data_ren -add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/data_out -add wave -noupdate -radix hexadecimal /testbench/data_out_obs -add wave -noupdate /testbench/pointer_read -add wave -noupdate /testbench/pointer_write -add wave -noupdate /testbench/error_now -add wave -noupdate /testbench/error_new -add wave -noupdate /testbench/read_stop +add wave -noupdate -expand -group FIFO_CEL -expand -group COMMON /testbench/cel_clk +add wave -noupdate -expand -group FIFO_CEL -expand -group COMMON /testbench/cel_rstn +add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_READ /testbench/cel_data_out +add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_READ /testbench/cel_data_ren +add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_READ /testbench/cel_empty +add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_WRITE /testbench/cel_data_wen +add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_WRITE /testbench/cel_full +add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_WRITE /testbench/cel_full_almost +add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_WRITE /testbench/cel_wdata +add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_ERROR /testbench/cel_error_new +add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_ERROR /testbench/cel_error_now +add wave -noupdate -expand -group FIFO_RAM -group COMMON /testbench/ram_clk +add wave -noupdate -expand -group FIFO_RAM -group COMMON /testbench/ram_rstn +add wave -noupdate -expand -group FIFO_RAM -group FIFO_READ /testbench/ram_data_out +add wave -noupdate -expand -group FIFO_RAM -group FIFO_READ /testbench/ram_data_ren +add wave -noupdate -expand -group FIFO_RAM -group FIFO_READ /testbench/ram_empty +add wave -noupdate -expand -group FIFO_RAM -group FIFO_WRITE /testbench/ram_data_wen +add wave -noupdate -expand -group FIFO_RAM -group FIFO_WRITE /testbench/ram_full +add wave -noupdate -expand -group FIFO_RAM -group FIFO_WRITE /testbench/ram_full_almost +add wave -noupdate -expand -group FIFO_RAM -group FIFO_WRITE /testbench/ram_wdata +add wave -noupdate -expand -group FIFO_RAM -expand -group FIFO_ERROR /testbench/ram_error_new +add wave -noupdate -expand -group FIFO_RAM -expand -group FIFO_ERROR /testbench/ram_error_now +add wave -noupdate -format Analog-Step -height 74 -max 256.0 /testbench/lpp_fifo_ram/lpp_fifo_control_1/space_busy +add wave -noupdate -format Analog-Step -height 74 -max 256.0 /testbench/lpp_fifo_ram/lpp_fifo_control_1/space_free +add wave -noupdate /testbench/fifo_verif_ram/read_stop +add wave -noupdate /testbench/fifo_verif_ram/write_stop +add wave -noupdate -expand -group EMPTY_FIFO_RAM /testbench/lpp_fifo_ram/lpp_fifo_control_1/empty +add wave -noupdate -expand -group EMPTY_FIFO_RAM /testbench/lpp_fifo_ram/lpp_fifo_control_1/empty_threshold +add wave -noupdate -expand -group FULL_FIFO_RAM /testbench/lpp_fifo_ram/lpp_fifo_control_1/full +add wave -noupdate -expand -group FULL_FIFO_RAM /testbench/lpp_fifo_ram/lpp_fifo_control_1/full_almost +add wave -noupdate -expand -group FULL_FIFO_RAM /testbench/lpp_fifo_ram/lpp_fifo_control_1/full_threshold +add wave -noupdate -radix unsigned /testbench/lpp_fifo_ram/lpp_fifo_control_1/waddr_vect +add wave -noupdate -radix unsigned /testbench/lpp_fifo_ram/lpp_fifo_control_1/raddr_vect +add wave -noupdate -radix unsigned /testbench/lpp_fifo_ram/lpp_fifo_control_1/waddr_vect_s +add wave -noupdate -radix unsigned /testbench/lpp_fifo_ram/lpp_fifo_control_1/raddr_vect_s TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {56085000 ps} 0} +WaveRestoreCursors {{Cursor 1} {4865000 ps} 0} configure wave -namecolwidth 510 configure wave -valuecolwidth 172 configure wave -justifyvalue left @@ -32,4 +51,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ps} {105131250 ps} +WaveRestoreZoom {0 ps} {127181250 ps} diff --git a/lib/lpp/lpp_memory/lppFIFOxN.vhd b/lib/lpp/lpp_memory/lppFIFOxN.vhd --- a/lib/lpp/lpp_memory/lppFIFOxN.vhd +++ b/lib/lpp/lpp_memory/lppFIFOxN.vhd @@ -42,6 +42,8 @@ ENTITY lppFIFOxN IS ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); + run : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); + wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); @@ -64,19 +66,25 @@ BEGIN GENERIC MAP ( tech => tech, Mem_use => Mem_use, + EMPTY_THRESHOLD_LIMIT => 1, + FULL_THRESHOLD_LIMIT => 1, DataSz => Data_sz, AddrSz => Addr_sz) PORT MAP ( clk => clk, rstn => rstn, reUse => reUse(I), + run => run(I), ren => ren(I), rdata => rdata( ((I+1)*Data_sz)-1 DOWNTO (I*Data_sz) ), wen => wen(I), wdata => wdata(((I+1)*Data_sz)-1 DOWNTO (I*Data_sz)), empty => empty(I), full => full(I), - almost_full => almost_full(I)); + full_almost => almost_full(I), + empty_threshold => OPEN, + full_threshold => OPEN + ); END GENERATE; END ARCHITECTURE; diff --git a/lib/lpp/lpp_memory/lpp_FIFO.vhd b/lib/lpp/lpp_memory/lpp_FIFO.vhd --- a/lib/lpp/lpp_memory/lpp_FIFO.vhd +++ b/lib/lpp/lpp_memory/lpp_FIFO.vhd @@ -30,51 +30,47 @@ USE techmap.gencomp.ALL; ENTITY lpp_fifo IS GENERIC( - tech : INTEGER := 0; - Mem_use : INTEGER := use_RAM; - DataSz : INTEGER RANGE 1 TO 32 := 8; - AddrSz : INTEGER RANGE 2 TO 12 := 8 + tech : INTEGER := 0; + Mem_use : INTEGER := use_RAM; + EMPTY_THRESHOLD_LIMIT : INTEGER := 16; + FULL_THRESHOLD_LIMIT : INTEGER := 5; + DataSz : INTEGER RANGE 1 TO 32 := 8; + AddrSz : INTEGER RANGE 2 TO 12 := 8 ); PORT( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; -- - reUse : IN STD_LOGIC; - + reUse : IN STD_LOGIC; + run : IN STD_LOGIC; + --IN - ren : IN STD_LOGIC; - rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); - + ren : IN STD_LOGIC; + rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); + --OUT - wen : IN STD_LOGIC; - wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); + wen : IN STD_LOGIC; + wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); - empty : OUT STD_LOGIC; - full : OUT STD_LOGIC; - almost_full : OUT STD_LOGIC + empty : OUT STD_LOGIC; + full : OUT STD_LOGIC; + full_almost : OUT STD_LOGIC; + empty_threshold : OUT STD_LOGIC; + full_threshold : OUT STD_LOGIC ); END ENTITY; ARCHITECTURE ar_lpp_fifo OF lpp_fifo IS - SIGNAL sFull : STD_LOGIC; - SIGNAL sFull_s : STD_LOGIC; - SIGNAL sEmpty_s : STD_LOGIC; + SIGNAL sREN : STD_LOGIC; + SIGNAL sWEN : STD_LOGIC; + SIGNAL sRE : STD_LOGIC; + SIGNAL sWE : STD_LOGIC; - SIGNAL sEmpty : STD_LOGIC; - SIGNAL sREN : STD_LOGIC; - SIGNAL sWEN : STD_LOGIC; - SIGNAL sRE : STD_LOGIC; - SIGNAL sWE : STD_LOGIC; + SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0'); - SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0'); - SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0'); - SIGNAL Waddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0'); - SIGNAL Raddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0'); - - SIGNAL almost_full_s : STD_LOGIC; - SIGNAL almost_full_r : STD_LOGIC; BEGIN --================================================================================== @@ -93,75 +89,33 @@ BEGIN PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, CLK, rstn); END GENERATE; --================================================================================== - ---============================= --- Read section ---============================= - sREN <= REN OR sEmpty; - sRE <= NOT sREN; - - sEmpty_s <= '0' WHEN ReUse = '1' else - '1' WHEN sEmpty = '1' AND Wen = '1' ELSE - '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE - '0'; - - Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1); - - PROCESS (clk, rstn) - BEGIN - IF(rstn = '0')then - Raddr_vect <= (OTHERS => '0'); - sempty <= '1'; - ELSIF(clk'EVENT AND clk = '1')then - sEmpty <= sempty_s; - - IF(sREN = '0' and sempty = '0')then - Raddr_vect <= Raddr_vect_s; - END IF; - - END IF; - END PROCESS; - ---============================= --- Write section ---============================= - sWEN <= WEN OR sFull; - sWE <= NOT sWEN; - - sFull_s <= '1' WHEN ReUse = '1' else - '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE - '1' WHEN sFull = '1' AND REN = '1' ELSE - '0'; - - almost_full_s <= '1' WHEN STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +2) = Raddr_vect AND REN = '1' AND WEN = '0' ELSE - '1' WHEN almost_full_r = '1' AND WEN = REN ELSE - '0'; - - Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1); - - PROCESS (clk, rstn) - BEGIN - IF(rstn = '0')then - Waddr_vect <= (OTHERS => '0'); - sfull <= '0'; - almost_full_r <= '0'; - ELSIF(clk'EVENT AND clk = '1')then - sfull <= sfull_s; - almost_full_r <= almost_full_s; - - IF(sWEN = '0' and sfull = '0')THEN - Waddr_vect <= Waddr_vect_s; - END IF; - - END IF; - END PROCESS; - - almost_full <= almost_full_s; - full <= sFull_s; - empty <= sEmpty_s; + sRE <= NOT sREN; + sWE <= NOT sWEN; - + lpp_fifo_control_1 : lpp_fifo_control + GENERIC MAP ( + AddrSz => AddrSz, + EMPTY_THRESHOLD_LIMIT => EMPTY_THRESHOLD_LIMIT, + FULL_THRESHOLD_LIMIT => FULL_THRESHOLD_LIMIT) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + reUse => reUse, + fifo_r_en => ren, + fifo_w_en => wen, + mem_r_en => sREN, + mem_w_en => SWEN, + mem_r_addr => Raddr_vect, + mem_w_addr => Waddr_vect, + empty => empty, + full => full, + full_almost => full_almost, + empty_threshold => empty_threshold, + full_threshold => full_threshold); + + END ARCHITECTURE; diff --git a/lib/lpp/lpp_memory/lpp_FIFO_4_Shared.vhd b/lib/lpp/lpp_memory/lpp_FIFO_4_Shared.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_memory/lpp_FIFO_4_Shared.vhd @@ -0,0 +1,185 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_fifo_4_shared IS + GENERIC( + tech : INTEGER := 0; + Mem_use : INTEGER := use_RAM; + EMPTY_THRESHOLD_LIMIT : INTEGER := 16; + FULL_THRESHOLD_LIMIT : INTEGER := 5; + DataSz : INTEGER RANGE 1 TO 32 := 8; + AddrSz : INTEGER RANGE 3 TO 12 := 8 + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + --------------------------------------------------------------------------- + run : IN STD_LOGIC; + + --------------------------------------------------------------------------- + empty_threshold : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b + empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + r_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + r_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + --------------------------------------------------------------------------- + full_threshold : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b + full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b + full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + w_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + w_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE beh OF lpp_fifo_4_shared IS + + SIGNAL full_s : STD_LOGIC_VECTOR(3 DOWNTO 0); + + TYPE LPP_TYPE_ADDR_FIFO_SHARED IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR(AddrSz-3 DOWNTO 0); + SIGNAL mem_r_addr_v : LPP_TYPE_ADDR_FIFO_SHARED; + SIGNAL mem_w_addr_v : LPP_TYPE_ADDR_FIFO_SHARED; + SIGNAL mem_r_addr : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0); + SIGNAL mem_w_addr : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0); + + SIGNAL fifo_r_en_v : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL fifo_w_en_v : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL mem_r_en_v : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL mem_w_en_v : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL mem_r_e : STD_LOGIC; + SIGNAL mem_w_e : STD_LOGIC; + + SIGNAL NB_DATA_IN_FIFO : INTEGER; + + + CONSTANT length : INTEGER := 2**(AddrSz-2); + TYPE INTEGER_ARRAY_4 IS ARRAY (3 DOWNTO 0) OF INTEGER; + SIGNAL mem_r_addr_v_int : INTEGER_ARRAY_4; + SIGNAL mem_w_addr_v_int : INTEGER_ARRAY_4; + SIGNAL space_busy : INTEGER_ARRAY_4; + SIGNAL space_free : INTEGER_ARRAY_4; + +BEGIN + + ----------------------------------------------------------------------------- + SRAM : syncram_2p + GENERIC MAP(tech, AddrSz, DataSz) + PORT MAP(clk, mem_r_e, mem_r_addr, r_data, + clk, mem_w_e, mem_w_addr, w_data); + ----------------------------------------------------------------------------- + + mem_r_addr <= "00" & mem_r_addr_v(0) WHEN fifo_r_en_v(0) = '0' ELSE + "01" & mem_r_addr_v(1) WHEN fifo_r_en_v(1) = '0' ELSE + "10" & mem_r_addr_v(2) WHEN fifo_r_en_v(2) = '0' ELSE + "11" & mem_r_addr_v(3); -- WHEN fifo_r_en(2) = '0' ELSE + + mem_w_addr <= "00" & mem_w_addr_v(0) WHEN fifo_w_en_v(0) = '0' ELSE + "01" & mem_w_addr_v(1) WHEN fifo_w_en_v(1) = '0' ELSE + "10" & mem_w_addr_v(2) WHEN fifo_w_en_v(2) = '0' ELSE + "11" & mem_w_addr_v(3); -- WHEN fifo_r_en(2) = '0' ELSE + + mem_r_e <= '0' WHEN mem_r_en_v = "1111" ELSE '1'; + mem_w_e <= '0' WHEN mem_w_en_v = "1111" ELSE '1'; + + ---------------------------------------------------------------------------- + all_fifo : FOR I IN 3 DOWNTO 0 GENERATE + fifo_r_en_v(I) <= r_en(I); + fifo_w_en_v(I) <= w_en(I); + + lpp_fifo_control_1 : lpp_fifo_control + GENERIC MAP ( + AddrSz => AddrSz-2, + EMPTY_THRESHOLD_LIMIT => EMPTY_THRESHOLD_LIMIT, + FULL_THRESHOLD_LIMIT => FULL_THRESHOLD_LIMIT) + PORT MAP ( + clk => clk, + rstn => rstn, + reUse => '0', + run => run, + fifo_r_en => fifo_r_en_v(I), + fifo_w_en => fifo_w_en_v(I), + mem_r_en => mem_r_en_v(I), + mem_w_en => mem_w_en_v(I), + mem_r_addr => mem_r_addr_v(I), + mem_w_addr => mem_w_addr_v(I), + empty => empty(I), + full => full_s(I), + full_almost => full_almost(I), + empty_threshold => empty_threshold(I), + full_threshold => full_threshold(I) + ); + + --full(I) <= full_s(I); + + --mem_w_addr_v_int(I) <= to_integer(UNSIGNED(mem_w_addr_v(I))); + --mem_r_addr_v_int(I) <= to_integer(UNSIGNED(mem_r_addr_v(I))); + + --space_busy(I) <= length WHEN full_s(I) = '1' ELSE + -- length + mem_w_addr_v_int(I) - mem_r_addr_v_int(I) WHEN mem_w_addr_v_int(I) < mem_r_addr_v_int(I) ELSE + -- mem_w_addr_v_int(I) - mem_r_addr_v_int(I); + + --space_free(I) <= length - space_busy(I); + + --empty_threshold(I) <= '0' WHEN space_busy(I) > EMPTY_THRESHOLD_LIMIT ELSE '1'; + --full_threshold(I) <= '0' WHEN space_free(I) > FULL_THRESHOLD_LIMIT ELSE '1'; + + END GENERATE all_fifo; + + + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd b/lib/lpp/lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd @@ -0,0 +1,145 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_fifo_4_shared_headreg_latency_0 IS + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + --------------------------------------------------------------------------- + run : IN STD_LOGIC; + --------------------------------------------------------------------------- + o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b + o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + --------------------------------------------------------------------------- + i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- + i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE beh OF lpp_fifo_4_shared_headreg_latency_0 IS + + TYPE REG_HEAD_TYPE IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL reg_head_data : REG_HEAD_TYPE; + + + SIGNAL reg_head_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL i_data_ren_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL o_data_ren_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL i_data_ren_s_temp : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL i_data_ren_s : STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + SIGNAL i_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + + +BEGIN + --i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- + i_data_ren <= i_data_ren_s; + o_empty_almost <= i_empty_almost; --TODO + + o_rdata_0 <= i_rdata WHEN o_data_ren_pre(0) = '0' AND o_data_ren(0) = '0' ELSE reg_head_data(0) ; + o_rdata_1 <= i_rdata WHEN o_data_ren_pre(1) = '0' AND o_data_ren(1) = '0' ELSE reg_head_data(1) ; + o_rdata_2 <= i_rdata WHEN o_data_ren_pre(2) = '0' AND o_data_ren(2) = '0' ELSE reg_head_data(2) ; + o_rdata_3 <= i_rdata WHEN o_data_ren_pre(3) = '0' AND o_data_ren(3) = '0' ELSE reg_head_data(3) ; + + i_data_ren_s(0) <= i_data_ren_s_temp(0); + i_data_ren_s(1) <= i_data_ren_s_temp(1) WHEN i_data_ren_s_temp(0) = '1' ELSE '1'; + i_data_ren_s(2) <= i_data_ren_s_temp(2) WHEN i_data_ren_s_temp(1 DOWNTO 0) = "11" ELSE '1'; + i_data_ren_s(3) <= i_data_ren_s_temp(3) WHEN i_data_ren_s_temp(2 DOWNTO 0) = "111" ELSE '1'; + + each_fifo: FOR I IN 3 DOWNTO 0 GENERATE + o_empty(I) <= NOT reg_head_full(I); + +-- i_data_ren_pre(I) <= i_data_ren_s(I); + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + reg_head_data(I) <= (OTHERS => '0'); + i_data_ren_pre(I) <= '1'; + reg_head_full(I) <= '0'; + o_data_ren_pre(I) <= '1'; + ELSIF clk'event AND clk = '1' THEN + o_data_ren_pre(I) <= o_data_ren(I) ; + IF i_data_ren_pre(I) = '0' THEN + reg_head_data(I) <= i_rdata; + END IF; + i_data_ren_pre(I) <= i_data_ren_s(I); + +-- IF i_data_ren_pre(I) = '0' THEN + IF i_data_ren_s(I) = '0' THEN + reg_head_full(I) <= '1'; +-- ELSIF o_data_ren_pre(I) = '0' THEN + ELSIF o_data_ren(I) = '0' THEN + reg_head_full(I) <= '0'; + END IF; + + END IF; + END PROCESS; + + i_data_ren_s_temp(I) <= '1' WHEN i_empty_reg(I) = '1' ELSE + '0' WHEN o_data_ren(I) = '0' ELSE + '0' WHEN reg_head_full(I) = '0' ELSE + '1'; + + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + i_empty_reg(I) <= '1'; + ELSIF clk'event AND clk = '1' THEN + i_empty_reg(I) <= i_empty(I); + END IF; + END PROCESS; + + + + END GENERATE each_fifo; + + +END ARCHITECTURE; + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd b/lib/lpp/lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd @@ -0,0 +1,171 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_fifo_4_shared_headreg_latency_1 IS + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + --------------------------------------------------------------------------- + run : IN STD_LOGIC; + --------------------------------------------------------------------------- + o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b + o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + --------------------------------------------------------------------------- + i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- + i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE beh OF lpp_fifo_4_shared_headreg_latency_1 IS + + TYPE REG_HEAD_TYPE IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL reg_head_data : REG_HEAD_TYPE; + + + SIGNAL reg_head_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL i_data_ren_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL o_data_ren_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL i_data_ren_s_temp : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL i_data_ren_s : STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + SIGNAL i_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL o_rdata_0_s : STD_LOGIC_VECTOR(31 DOWNTO 0); -- + SIGNAL o_rdata_1_s : STD_LOGIC_VECTOR(31 DOWNTO 0); -- + SIGNAL o_rdata_2_s : STD_LOGIC_VECTOR(31 DOWNTO 0); -- + SIGNAL o_rdata_3_s : STD_LOGIC_VECTOR(31 DOWNTO 0); -- + + +BEGIN + --i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- + i_data_ren <= i_data_ren_s; + + o_rdata_0_s <= i_rdata WHEN o_data_ren_pre(0) = '0' AND o_data_ren(0) = '0' ELSE reg_head_data(0) ; + o_rdata_1_s <= i_rdata WHEN o_data_ren_pre(1) = '0' AND o_data_ren(1) = '0' ELSE reg_head_data(1) ; + o_rdata_2_s <= i_rdata WHEN o_data_ren_pre(2) = '0' AND o_data_ren(2) = '0' ELSE reg_head_data(2) ; + o_rdata_3_s <= i_rdata WHEN o_data_ren_pre(3) = '0' AND o_data_ren(3) = '0' ELSE reg_head_data(3) ; + + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + o_rdata_0 <= (OTHERS => '0'); + o_rdata_1 <= (OTHERS => '0'); + o_rdata_2 <= (OTHERS => '0'); + o_rdata_3 <= (OTHERS => '0'); + --o_empty_almost <= (OTHERS => '0'); + --o_empty <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + o_rdata_0 <= o_rdata_0_s; + o_rdata_1 <= o_rdata_1_s; + o_rdata_2 <= o_rdata_2_s; + o_rdata_3 <= o_rdata_3_s; + + --o_empty_almost <= i_empty_almost; --TODO + --o_empty <= NOT reg_head_full; + END IF; + END PROCESS; + + + o_empty_almost <= i_empty_almost; --TODO + o_empty <= NOT reg_head_full OR (i_empty AND o_data_ren); + + + + i_data_ren_s(0) <= i_data_ren_s_temp(0); + i_data_ren_s(1) <= i_data_ren_s_temp(1) WHEN i_data_ren_s_temp(0) = '1' ELSE '1'; + i_data_ren_s(2) <= i_data_ren_s_temp(2) WHEN i_data_ren_s_temp(1 DOWNTO 0) = "11" ELSE '1'; + i_data_ren_s(3) <= i_data_ren_s_temp(3) WHEN i_data_ren_s_temp(2 DOWNTO 0) = "111" ELSE '1'; + + each_fifo: FOR I IN 3 DOWNTO 0 GENERATE + +-- i_data_ren_pre(I) <= i_data_ren_s(I); + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + reg_head_data(I) <= (OTHERS => '0'); + i_data_ren_pre(I) <= '1'; + reg_head_full(I) <= '0'; + o_data_ren_pre(I) <= '1'; + ELSIF clk'event AND clk = '1' THEN + o_data_ren_pre(I) <= o_data_ren(I) ; + IF i_data_ren_pre(I) = '0' THEN + reg_head_data(I) <= i_rdata; + END IF; + i_data_ren_pre(I) <= i_data_ren_s(I); + IF i_data_ren_s(I) = '0' THEN + reg_head_full(I) <= '1'; + ELSIF o_data_ren(I) = '0' THEN + reg_head_full(I) <= '0'; + END IF; + + END IF; + END PROCESS; + + i_data_ren_s_temp(I) <= '1' WHEN i_empty_reg(I) = '1' ELSE + '0' WHEN o_data_ren(I) = '0' ELSE + '0' WHEN reg_head_full(I) = '0' ELSE + '1'; + + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + i_empty_reg(I) <= '1'; + ELSIF clk'event AND clk = '1' THEN + i_empty_reg(I) <= i_empty(I); + END IF; + END PROCESS; + + + + END GENERATE each_fifo; + + +END ARCHITECTURE; + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_memory/lpp_FIFO_control.vhd b/lib/lpp/lpp_memory/lpp_FIFO_control.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_memory/lpp_FIFO_control.vhd @@ -0,0 +1,208 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY lpp_fifo_control IS + GENERIC( + AddrSz : INTEGER RANGE 2 TO 12 := 8; + EMPTY_THRESHOLD_LIMIT : INTEGER := 16; + FULL_THRESHOLD_LIMIT : INTEGER := 5 + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + -- + reUse : IN STD_LOGIC; + run : IN STD_LOGIC; + + --IN + fifo_r_en : IN STD_LOGIC; + fifo_w_en : IN STD_LOGIC; + + mem_r_en : OUT STD_LOGIC; + mem_w_en : OUT STD_LOGIC; + mem_r_addr : OUT STD_LOGIC_VECTOR(AddrSz -1 DOWNTO 0); + mem_w_addr : OUT STD_LOGIC_VECTOR(AddrSz -1 DOWNTO 0); + + empty : OUT STD_LOGIC; + full : OUT STD_LOGIC; + full_almost : OUT STD_LOGIC; + empty_threshold : OUT STD_LOGIC; + full_threshold : OUT STD_LOGIC + + ); +END ENTITY; + + +ARCHITECTURE beh OF lpp_fifo_control IS + + SIGNAL sFull : STD_LOGIC; + SIGNAL sFull_s : STD_LOGIC; + SIGNAL sEmpty_s : STD_LOGIC; + + SIGNAL sEmpty : STD_LOGIC; + SIGNAL sREN : STD_LOGIC; + SIGNAL sWEN : STD_LOGIC; + + SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL Waddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL Raddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0'); + + SIGNAL almost_full_s : STD_LOGIC; + SIGNAL almost_full_r : STD_LOGIC; + + SIGNAL mem_r_addr_int : INTEGER; + SIGNAL mem_w_addr_int : INTEGER; + SIGNAL space_busy : INTEGER; + SIGNAL space_free : INTEGER; + + CONSTANT length : INTEGER := 2**(AddrSz); + +BEGIN + + mem_r_addr <= Raddr_vect; + mem_w_addr <= Waddr_vect; + + + mem_r_en <= sREN; + mem_w_en <= sWEN; +--============================= +-- Read section +--============================= + sREN <= FIFO_R_EN OR sEmpty; + --sRE <= NOT sREN; + + sEmpty_s <= '0' WHEN ReUse = '1' ELSE + '1' WHEN sEmpty = '1' AND Fifo_W_En = '1' ELSE + '1' WHEN sEmpty = '0' AND (Fifo_W_En = '1' AND Fifo_R_en = '0' AND Raddr_vect_s = Waddr_vect) ELSE + '0'; + + Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1); + + PROCESS (clk, rstn) + BEGIN + IF(rstn = '0')THEN + Raddr_vect <= (OTHERS => '0'); + sempty <= '1'; + ELSIF(clk'EVENT AND clk = '1')THEN + + IF run = '0' THEN + Raddr_vect <= (OTHERS => '0'); + sempty <= '1'; + ELSE + sEmpty <= sempty_s; + + IF(sREN = '0' AND sempty = '0')THEN + Raddr_vect <= Raddr_vect_s; + END IF; + END IF; + + END IF; + END PROCESS; + +--============================= +-- Write section +--============================= + sWEN <= FIFO_W_EN OR sFull; +-- sWE <= NOT sWEN; + + sFull_s <= '1' WHEN ReUse = '1' ELSE + '1' WHEN Waddr_vect_s = Raddr_vect AND FIFO_R_EN = '1' AND FIFO_W_EN = '0' ELSE + '1' WHEN sFull = '1' AND FIFO_R_EN = '1' ELSE + '0'; + + almost_full_s <= '1' WHEN STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +2) = Raddr_vect AND FIFO_R_EN = '1' AND FIFO_W_EN = '0' ELSE + '1' WHEN almost_full_r = '1' AND FIFO_W_EN = FIFO_R_EN ELSE + '0'; + + Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1); + + PROCESS (clk, rstn) + BEGIN + IF(rstn = '0')THEN + Waddr_vect <= (OTHERS => '0'); + sfull <= '0'; + almost_full_r <= '0'; + ELSIF(clk'EVENT AND clk = '1')THEN + IF run = '0' THEN + Waddr_vect <= (OTHERS => '0'); + sfull <= '0'; + almost_full_r <= '0'; + ELSE + sfull <= sfull_s; + almost_full_r <= almost_full_s; + + IF(sWEN = '0' AND sfull = '0')THEN + Waddr_vect <= Waddr_vect_s; + END IF; + END IF; + END IF; + END PROCESS; + + full_almost <= almost_full_s; + full <= sFull_s; + empty <= sEmpty_s; + + ----------------------------------------------------------------------------- + mem_w_addr_int <= to_integer(UNSIGNED(Waddr_vect)); + mem_r_addr_int <= to_integer(UNSIGNED(Raddr_vect)); + + space_busy <= length WHEN sFull = '1' ELSE + length + mem_w_addr_int - mem_r_addr_int WHEN mem_w_addr_int < mem_r_addr_int ELSE + mem_w_addr_int - mem_r_addr_int; + + space_free <= length - space_busy; + + empty_threshold <= '0' WHEN space_busy > EMPTY_THRESHOLD_LIMIT ELSE '1'; + full_threshold <= '0' WHEN space_free > FULL_THRESHOLD_LIMIT ELSE '1'; + ----------------------------------------------------------------------------- + + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -39,21 +39,108 @@ PACKAGE lpp_memory IS COMPONENT lpp_fifo GENERIC ( - tech : INTEGER; - Mem_use : INTEGER; - DataSz : INTEGER RANGE 1 TO 32; - AddrSz : INTEGER RANGE 2 TO 12); + tech : INTEGER; + Mem_use : INTEGER; + EMPTY_THRESHOLD_LIMIT : INTEGER; + FULL_THRESHOLD_LIMIT : INTEGER; + DataSz : INTEGER RANGE 1 TO 32; + AddrSz : INTEGER RANGE 2 TO 12); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + reUse : IN STD_LOGIC; + run : IN STD_LOGIC; + ren : IN STD_LOGIC; + rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); + wen : IN STD_LOGIC; + wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); + empty : OUT STD_LOGIC; + full : OUT STD_LOGIC; + full_almost : OUT STD_LOGIC; + empty_threshold : OUT STD_LOGIC; + full_threshold : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_fifo_4_shared + GENERIC ( + tech : INTEGER; + Mem_use : INTEGER; + EMPTY_THRESHOLD_LIMIT : INTEGER; + FULL_THRESHOLD_LIMIT : INTEGER; + DataSz : INTEGER RANGE 1 TO 32; + AddrSz : INTEGER RANGE 3 TO 12); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + empty_threshold : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + r_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + r_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + full_threshold : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + w_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + w_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_fifo_4_shared_headreg_latency_0 PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - reUse : IN STD_LOGIC; - ren : IN STD_LOGIC; - rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); - wen : IN STD_LOGIC; - wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); - empty : OUT STD_LOGIC; - full : OUT STD_LOGIC; - almost_full : OUT STD_LOGIC); + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_fifo_4_shared_headreg_latency_1 + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_fifo_control + GENERIC ( + AddrSz : INTEGER RANGE 2 TO 12; + EMPTY_THRESHOLD_LIMIT : INTEGER; + FULL_THRESHOLD_LIMIT : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + reUse : IN STD_LOGIC; + run : IN STD_LOGIC; + fifo_r_en : IN STD_LOGIC; + fifo_w_en : IN STD_LOGIC; + mem_r_en : OUT STD_LOGIC; + mem_w_en : OUT STD_LOGIC; + mem_r_addr : OUT STD_LOGIC_VECTOR(AddrSz -1 DOWNTO 0); + mem_w_addr : OUT STD_LOGIC_VECTOR(AddrSz -1 DOWNTO 0); + empty : OUT STD_LOGIC; + full : OUT STD_LOGIC; + full_almost : OUT STD_LOGIC; + empty_threshold : OUT STD_LOGIC; + full_threshold : OUT STD_LOGIC); END COMPONENT; COMPONENT lppFIFOxN @@ -67,6 +154,7 @@ PACKAGE lpp_memory IS clk : IN STD_LOGIC; rstn : IN STD_LOGIC; ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); + run : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); @@ -138,56 +226,6 @@ PACKAGE lpp_memory IS ); END COMPONENT; - --COMPONENT lpp_fifo IS - -- GENERIC( - -- tech : INTEGER := 0; - -- Mem_use : INTEGER := use_RAM; - -- Enable_ReUse : STD_LOGIC := '0'; - -- DataSz : INTEGER RANGE 1 TO 32 := 8; - -- AddrSz : INTEGER RANGE 2 TO 12 := 8 - -- ); - -- PORT( - -- rstn : IN STD_LOGIC; - -- ReUse : IN STD_LOGIC; --27/01/12 - -- rclk : IN STD_LOGIC; - -- ren : IN STD_LOGIC; - -- rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); - -- empty : OUT STD_LOGIC; - -- raddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0); - -- wclk : IN STD_LOGIC; - -- wen : IN STD_LOGIC; - -- wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); - -- full : OUT STD_LOGIC; - -- almost_full : OUT STD_LOGIC; - -- waddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) - -- ); - --END COMPONENT; - - - --COMPONENT lppFIFOxN IS - -- GENERIC( - -- tech : INTEGER := 0; - -- Mem_use : INTEGER := use_RAM; - -- Data_sz : INTEGER RANGE 1 TO 32 := 8; - -- Addr_sz : INTEGER RANGE 1 TO 32 := 8; - -- FifoCnt : INTEGER := 1; - -- Enable_ReUse : STD_LOGIC := '0' - -- ); - -- PORT( - -- rstn : IN STD_LOGIC; - -- wclk : IN STD_LOGIC; - -- rclk : IN STD_LOGIC; - -- ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); - -- wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); - -- ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); - -- wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); - -- rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); - -- full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); - -- almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); - -- empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0) - -- ); - --END COMPONENT; - COMPONENT FillFifo IS GENERIC( Data_sz : INTEGER RANGE 1 TO 32 := 16; diff --git a/lib/lpp/lpp_memory/vhdlsyn.txt b/lib/lpp/lpp_memory/vhdlsyn.txt --- a/lib/lpp/lpp_memory/vhdlsyn.txt +++ b/lib/lpp/lpp_memory/vhdlsyn.txt @@ -1,4 +1,9 @@ lpp_memory.vhd lpp_FIFO.vhd +lpp_FIFO_4_Shared.vhd +lpp_FIFO_control.vhd +lpp_FIFO_4_Shared_headreg_latency_0.vhd +lpp_FIFO_4_Shared_headreg_latency_1.vhd lppFIFOxN.vhd + diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -117,6 +117,7 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL data_shaping_SP1 : STD_LOGIC; SIGNAL data_shaping_R0 : STD_LOGIC; SIGNAL data_shaping_R1 : STD_LOGIC; + SIGNAL data_shaping_R2 : STD_LOGIC; -- SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); @@ -312,6 +313,7 @@ BEGIN data_shaping_SP1 => data_shaping_SP1, data_shaping_R0 => data_shaping_R0, data_shaping_R1 => data_shaping_R1, + data_shaping_R2 => data_shaping_R2, sample_f0_val => sample_f0_val, sample_f1_val => sample_f1_val, sample_f2_val => sample_f2_val, @@ -380,6 +382,7 @@ BEGIN data_shaping_SP1 => data_shaping_SP1, data_shaping_R0 => data_shaping_R0, data_shaping_R1 => data_shaping_R1, + data_shaping_R2 => data_shaping_R2, delta_snapshot => delta_snapshot, delta_f0 => delta_f0, delta_f0_2 => delta_f0_2, @@ -745,4 +748,4 @@ BEGIN debug_ms(11 DOWNTO 0) & -- 23 .. 12 debug_signal(11 DOWNTO 0); -- 11 .. 0 -END beh; \ No newline at end of file +END beh; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -102,6 +102,7 @@ ENTITY lpp_lfr_apbreg IS data_shaping_SP1 : OUT STD_LOGIC; data_shaping_R0 : OUT STD_LOGIC; data_shaping_R1 : OUT STD_LOGIC; + data_shaping_R2 : OUT STD_LOGIC; delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); @@ -182,6 +183,7 @@ ARCHITECTURE beh OF lpp_lfr_apbreg IS data_shaping_SP1 : STD_LOGIC; data_shaping_R0 : STD_LOGIC; data_shaping_R1 : STD_LOGIC; + data_shaping_R2 : STD_LOGIC; delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); @@ -267,6 +269,7 @@ BEGIN -- beh data_shaping_SP1 <= reg_wp.data_shaping_SP1; data_shaping_R0 <= reg_wp.data_shaping_R0; data_shaping_R1 <= reg_wp.data_shaping_R1; + data_shaping_R2 <= reg_wp.data_shaping_R2; delta_snapshot <= reg_wp.delta_snapshot; delta_f0 <= reg_wp.delta_f0; @@ -342,6 +345,7 @@ BEGIN -- beh reg_wp.data_shaping_SP1 <= '0'; reg_wp.data_shaping_R0 <= '0'; reg_wp.data_shaping_R1 <= '0'; + reg_wp.data_shaping_R2 <= '0'; reg_wp.enable_f0 <= '0'; reg_wp.enable_f1 <= '0'; reg_wp.enable_f2 <= '0'; @@ -458,6 +462,7 @@ BEGIN -- beh prdata(2) <= reg_wp.data_shaping_SP1; prdata(3) <= reg_wp.data_shaping_R0; prdata(4) <= reg_wp.data_shaping_R1; + prdata(5) <= reg_wp.data_shaping_R2; --21 WHEN "010101" => prdata(0) <= reg_wp.enable_f0; prdata(1) <= reg_wp.enable_f1; @@ -536,6 +541,7 @@ BEGIN -- beh reg_wp.data_shaping_SP1 <= apbi.pwdata(2); reg_wp.data_shaping_R0 <= apbi.pwdata(3); reg_wp.data_shaping_R1 <= apbi.pwdata(4); + reg_wp.data_shaping_R2 <= apbi.pwdata(5); WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0); reg_wp.enable_f1 <= apbi.pwdata(1); reg_wp.enable_f2 <= apbi.pwdata(2); diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd @@ -33,6 +33,7 @@ ENTITY lpp_lfr_filter IS data_shaping_SP1 : IN STD_LOGIC; data_shaping_R0 : IN STD_LOGIC; data_shaping_R1 : IN STD_LOGIC; + data_shaping_R2 : IN STD_LOGIC; -- sample_f0_val : OUT STD_LOGIC; sample_f1_val : OUT STD_LOGIC; @@ -274,7 +275,7 @@ BEGIN sample_out_val => sample_f1_val_s, sample_out => sample_f1); - sample_f1_val <= sample_f1_val_s; + sample_f1_val <= sample_f1_val_s; all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE sample_f1_wdata_s(I) <= sample_f1(0, I); -- V @@ -326,8 +327,8 @@ BEGIN all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE sample_f2_wdata_s(I) <= sample_f2(0, I); - sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); - sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); + sample_f2_wdata_s(16*1+I) <= sample_f2(1, I) WHEN data_shaping_R2 = '1' ELSE sample_f1(3, I);; + sample_f2_wdata_s(16*2+I) <= sample_f2(2, I) WHEN data_shaping_R2 = '1' ELSE sample_f1(4, I);; sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); @@ -382,4 +383,4 @@ BEGIN sample_f2_wdata <= sample_f2_wdata_s; sample_f3_wdata <= sample_f3_wdata_s; -END tb; \ No newline at end of file +END tb; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd @@ -291,6 +291,8 @@ BEGIN ReUse => (OTHERS => '0'), + run => (OTHERS => '1'), + wen => sample_f0_A_wen, wdata => sample_f0_wdata, @@ -313,6 +315,7 @@ BEGIN rstn => rstn, ReUse => (OTHERS => '0'), + run => (OTHERS => '1'), wen => sample_f0_B_wen, wdata => sample_f0_wdata, @@ -358,6 +361,7 @@ BEGIN rstn => rstn, ReUse => (OTHERS => '0'), + run => (OTHERS => '1'), wen => sample_f1_wen_head, wdata => sample_f1_wdata_head, @@ -400,6 +404,7 @@ BEGIN rstn => rstn, ReUse => (OTHERS => '0'), + run => (OTHERS => '1'), wen => sample_f2_wen, wdata => sample_f2_wdata, @@ -748,6 +753,7 @@ BEGIN rstn => rstn, ReUse => MEM_IN_SM_ReUse, + run => (OTHERS => '1'), wen => MEM_IN_SM_wen, wdata => MEM_IN_SM_wData, @@ -887,6 +893,7 @@ BEGIN rstn => rstn, ReUse => (OTHERS => '0'), + run => (OTHERS => '1'), wen => MEM_OUT_SM_Write, wdata => MEM_OUT_SM_Data_in, diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -204,6 +204,7 @@ PACKAGE lpp_lfr_pkg IS data_shaping_SP1 : IN STD_LOGIC; data_shaping_R0 : IN STD_LOGIC; data_shaping_R1 : IN STD_LOGIC; + data_shaping_R2 : IN STD_LOGIC; sample_f0_val : OUT STD_LOGIC; sample_f1_val : OUT STD_LOGIC; sample_f2_val : OUT STD_LOGIC; @@ -332,6 +333,7 @@ PACKAGE lpp_lfr_pkg IS data_shaping_SP1 : OUT STD_LOGIC; data_shaping_R0 : OUT STD_LOGIC; data_shaping_R1 : OUT STD_LOGIC; + data_shaping_R2 : OUT STD_LOGIC; delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd @@ -32,6 +32,8 @@ USE GRLIB.DMA2AHB_Package.ALL; LIBRARY lpp; USE lpp.lpp_waveform_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.lpp_memory.ALL; LIBRARY techmap; USE techmap.gencomp.ALL; @@ -212,15 +214,18 @@ ARCHITECTURE beh OF lpp_waveform IS SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); +-- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); -- SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0); + BEGIN -- beh + ----------------------------------------------------------------------------- -- DEBUG ----------------------------------------------------------------------------- @@ -454,49 +459,83 @@ BEGIN -- beh --debug_f3_data_fifo_in <= wdata;s ----------------------------------------------------------------------------- - lpp_waveform_fifo_1 : lpp_waveform_fifo - GENERIC MAP (tech => tech) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, + + -- lpp_fifo_4_shared_1: lpp_fifo_4_shared + -- GENERIC MAP ( + -- tech => tech, + -- Mem_use => use_RAM, + -- EMPTY_ALMOST_LIMIT => 16, + -- FULL_ALMOST_LIMIT => 5, + -- DataSz => 32, + -- AddrSz => 7 + -- ) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- run => run, + -- empty_almost => s_empty_almost, + -- empty => s_empty, + -- r_en => s_data_ren, + -- r_data => s_rdata, + -- full_almost => full_almost, + -- full => full, + -- w_en => data_wen, + -- w_data => wdata); - empty => s_empty, - empty_almost => s_empty_almost, - data_ren => s_data_ren, - rdata => s_rdata, + --lpp_waveform_fifo_headreg_1 : lpp_fifo_4_shared_headreg_latency_1 + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- run => run, + -- o_empty_almost => empty_almost, + -- o_empty => empty, - - full_almost => full_almost, - full => full, - data_wen => data_wen, - wdata => wdata); + -- o_data_ren => data_ren, + -- o_rdata_0 => data_f0_data_out, + -- o_rdata_1 => data_f1_data_out, + -- o_rdata_2 => data_f2_data_out, + -- o_rdata_3 => data_f3_data_out, - lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg - GENERIC MAP (tech => tech) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - o_empty_almost => empty_almost, - o_empty => empty, + -- i_empty_almost => s_empty_almost, + -- i_empty => s_empty, + -- i_data_ren => s_data_ren, + -- i_rdata => s_rdata); - o_data_ren => data_ren, - o_rdata_0 => data_f0_data_out, - o_rdata_1 => data_f1_data_out, - o_rdata_2 => data_f2_data_out, - o_rdata_3 => data_f3_data_out, + generate_all_fifo: FOR I IN 0 TO 3 GENERATE + lpp_fifo_1: lpp_fifo + GENERIC MAP ( + tech => tech, + Mem_use => use_RAM, + EMPTY_THRESHOLD_LIMIT => 16, + FULL_THRESHOLD_LIMIT => 5, + DataSz => 32, + AddrSz => 7) + PORT MAP ( + clk => clk, + rstn => rstn, + reUse => '0', + run => run, + ren => data_ren(I), + rdata => s_rdata_v((I+1)*32-1 downto I*32), + wen => data_wen(I), + wdata => wdata, + empty => empty(I), + full => full(I), + full_almost => OPEN, + empty_threshold => empty_almost(I), + full_threshold => full_almost(I) ); + + END GENERATE generate_all_fifo; - i_empty_almost => s_empty_almost, - i_empty => s_empty, - i_data_ren => s_data_ren, - i_rdata => s_rdata); - - - --data_f0_data_out <= rdata; - --data_f1_data_out <= rdata; - --data_f2_data_out <= rdata; - --data_f3_data_out <= rdata; + + --empty <= s_empty; + --empty_almost <= s_empty_almost; + --s_data_ren <= data_ren; + + data_f0_data_out <= s_rdata_v(31 downto 0); + data_f1_data_out <= s_rdata_v(31+32 downto 0+32); + data_f2_data_out <= s_rdata_v(31+32*2 downto 32*2); + data_f3_data_out <= s_rdata_v(31+32*3 downto 32*3); data_ren <= data_f3_data_out_ren & data_f2_data_out_ren &