HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r560:8e5e2afea36a

Update SDC for the MINI-LFR boards

pellion -

r560:8e5e2afea36a JC

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r560:8e5e2afea36a

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boards/MINI-LFR/MINI_LFR_synthesis.sdc +3 -5

             #
-            define_clock  {clk_50} -name {clk_50}  -freq 100    -clockgroup default_clkgroup -route 5
+            define_clock  -name {clk_50}  -freq 100    -clockgroup default_clkgroup_50 -route 5
-            define_clock  {clk_49} -name {clk_49}  -freq 49.152 -clockgroup default_clkgroup -route 5
+            define_clock  -name {clk_49}  -freq 49.152 -clockgroup default_clkgroup_49 -route 5
             #
             # Clock to Clock
             #
             # Inputs/Outputs
             #
-            define_output_delay -disable     -default  5.00 -improve 0.00 -route 0.00 -ref {clk:r}
-            define_input_delay -disable      -default  5.00 -improve 0.00 -route 0.00 -ref {clk:r}
             #
             #
             # False Path
             #
+            set_false_path -from reset
             #
             # Path Delay
             #
             define_global_attribute          syn_useioff {1}
             define_global_attribute -disable syn_netlist_hierarchy {0}
-            define_attribute          {etx_clk} syn_noclockbuf {1}
             #
             # I/O standards

designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +19 -5

               SIGNAL rstn_25_d2 : STD_LOGIC;
               SIGNAL rstn_25_d3 : STD_LOGIC;
+              SIGNAL rstn_24    : STD_LOGIC;
+              SIGNAL rstn_24_d1 : STD_LOGIC;
+              SIGNAL rstn_24_d2 : STD_LOGIC;
+              SIGNAL rstn_24_d3 : STD_LOGIC;
               SIGNAL rstn_50    : STD_LOGIC;
               SIGNAL rstn_50_d1 : STD_LOGIC;
               SIGNAL rstn_50_d2 : STD_LOGIC;
               BEGIN  -- PROCESS
                 IF reset = '0' THEN                 -- asynchronous reset (active low)
                   clk_24     <= '0';
+                  rstn_24_d1 <= '0';
+                  rstn_24_d2 <= '0';
+                  rstn_24_d3 <= '0';
+                  rstn_24    <= '0';
                 ELSIF clk_49'EVENT AND clk_49 = '1' THEN  -- rising clock edge
                   clk_24     <= NOT clk_24;
+                  rstn_24_d1 <= '1';
+                  rstn_24_d2 <= rstn_24_d1;
+                  rstn_24_d3 <= rstn_24_d2;
+                  rstn_24    <= rstn_24_d3;
                 END IF;
               END PROCESS;
                 END IF;
               END PROCESS;
-              PROCESS (clk_24, rstn_25)
+              PROCESS (clk_24, rstn_24)
               BEGIN  -- PROCESS
-                IF rstn_25 = '0' THEN               -- asynchronous reset (active low)
+                IF rstn_24 = '0' THEN               -- asynchronous reset (active low)
                   I00_s <= '0';
                 ELSIF clk_24'EVENT AND clk_24 = '1' THEN  -- rising clock edge
                   I00_s <= NOT I00_s;
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz         => clk_25,
+                  resetn_25MHz     => rstn_25,      --      TODO
                   clk24_576MHz     => clk_24,       -- 49.152MHz/2
-                  resetn        => rstn_25,
+                  resetn_24_576MHz => rstn_24,      --      TODO
                   grspw_tick       => swno.tickout,
                   apbi             => apbi_ext,
                   apbo             => apbo_ext(6),
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"000143")  -- aa.bb.cc version
+                  top_lfr_version        => X"000144")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                 PORT MAP (
                   -- CONV
                   cnv_clk    => clk_24,
-                  cnv_rstn   => rstn_25,
+                  cnv_rstn   => rstn_24,
                   cnv        => ADC_nCS_sig,
                   -- DATA
                   clk        => clk_25,

designs/MINI-LFR_WFP_MS/Makefile +1 -1

             SIMTOP=testbench
             PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
             ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
-            ##SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
+            SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
             SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
             BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
             CLEAN=soft-clean

lib/lpp/dsp/cic/cic_lfr_r2.vhd +1 -5

               SIGNAL addr_gen: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL addr_read: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL addr_write: STD_LOGIC_VECTOR(8 DOWNTO 0);
-              SIGNAL addr_write_mux: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL addr_write_s: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL data_we: STD_LOGIC;
               SIGNAL data_we_s: STD_LOGIC;
               SIGNAL data_wen       : STD_LOGIC;
-            --  SIGNAL data_write     : STD_LOGIC_VECTOR(15 DOWNTO 0);
-            --  SIGNAL data_read      : STD_LOGIC_VECTOR(15 DOWNTO 0);
-            --  SIGNAL data_read_pre      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_out_reg16   : sample_vector(8*2-1 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_out_reg256  : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0);
                 END GENERATE all_bits;
               END GENERATE all_channel_out_v;
-            END beh;
+            END beh;
  No newline at end of file

lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd +10 -10

               TYPE   FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE);
               SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION;
-              SIGNAL   sample_out_zero     : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
+              --SIGNAL   sample_out_zero     : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
             BEGIN
                 BEGIN  -- PROCESS
                   IF rstn = '0' THEN                  -- asynchronous reset (active low)
                     channel_ready(I) <= '0';
-                  ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+                  ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                     IF channel_val(I) = '1' THEN
                       channel_ready(I) <= '1';
                     ELSIF channel_done(I) = '1' THEN
                 END PROCESS;
               END GENERATE all_channel_input_valid;
               -----------------------------------------------------------------------------
-              all_channel_sample_out: FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
-                all_bit: FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
-                  sample_out_zero(I,J) <= '0';
-                END GENERATE all_bit;
-              END GENERATE all_channel_sample_out;
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                   sample_in_val           <= '0';
                   sample_out1_val         <= '0';
                   sample_out2_val         <= '0';
-                  sample_out1 <= sample_out_zero;
+                  all_channel_sample_out : FOR I IN ChanelsCount-1 DOWNTO 0 LOOP
-                  sample_out2 <= sample_out_zero;
+                    all_bit : FOR J IN Sample_SZ-1 DOWNTO 0 LOOP
+                      sample_out1(I, J) <= '0';
+                      sample_out2(I, J) <= '0';
+                    END LOOP all_bit;
+                  END LOOP all_channel_sample_out;
                   channel_done <= "00";
-                ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+                ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   CASE state_channel_selection IS
                     WHEN IDLE =>
                       CHANNEL_SEL     <= '0';

lib/lpp/general_purpose/SYNC_VALID_BIT.vhd +5 -4

                 NB_FF_OF_SYNC : INTEGER := 2);
               PORT (
                 clk_in  : IN  STD_LOGIC;
+                rstn_in : IN  STD_LOGIC;
                 clk_out  : IN  STD_LOGIC;
-                rstn    : IN  STD_LOGIC;
+                rstn_out : IN  STD_LOGIC;
                 sin      : IN  STD_LOGIC;
                 sout     : OUT STD_LOGIC);
             END SYNC_VALID_BIT;
               lpp_front_to_level_1: lpp_front_to_level
                 PORT MAP (
                   clk  => clk_in,
-                  rstn => rstn,
+                  rstn => rstn_in,
                   sin  => sin,
                   sout => s_1);
                   NB_FF_OF_SYNC => NB_FF_OF_SYNC)
                 PORT MAP (
                   clk    => clk_out,
-                  rstn   => rstn,
+                  rstn   => rstn_out,
                   A      => s_1,
                   A_sync => s_2);
               lpp_front_detection_1: lpp_front_detection
                 PORT MAP (
                   clk  => clk_out,
-                  rstn => rstn,
+                  rstn => rstn_out,
                   sin  => s_2,
                   sout => sout);

lib/lpp/general_purpose/general_purpose.vhd +13 -1

                   sout : OUT STD_LOGIC);
               END COMPONENT;
+              --COMPONENT SYNC_VALID_BIT
+              --  GENERIC (
+              --    NB_FF_OF_SYNC : INTEGER);
+              --  PORT (
+              --    clk_in  : IN  STD_LOGIC;
+              --    clk_out : IN  STD_LOGIC;
+              --    rstn : IN  STD_LOGIC;
+              --    sin  : IN  STD_LOGIC;
+              --    sout : OUT STD_LOGIC);
+              --END COMPONENT;
               COMPONENT SYNC_VALID_BIT
                 GENERIC (
                   NB_FF_OF_SYNC : INTEGER);
                 PORT (
                   clk_in   : IN  STD_LOGIC;
+                  rstn_in  : IN  STD_LOGIC;
                   clk_out  : IN  STD_LOGIC;
-                  rstn : IN  STD_LOGIC;
+                  rstn_out : IN  STD_LOGIC;
                   sin      : IN  STD_LOGIC;
                   sout     : OUT STD_LOGIC);
               END COMPONENT;

lib/lpp/lfr_management/apb_lfr_management.vhd +19 -14

               PORT (
                 clk25MHz         : IN STD_LOGIC;    --! Clock
+                resetn_25MHz     : IN STD_LOGIC;    --! Reset
                 clk24_576MHz     : IN STD_LOGIC;    --! secondary clock
-                resetn       : IN STD_LOGIC;        --! Reset
+                resetn_24_576MHz : IN STD_LOGIC;    --! Reset
                 grspw_tick : IN STD_LOGIC;  --! grspw signal asserted when a valid time-code is received
               LFR_soft_rstn <= NOT r.LFR_soft_reset;
-              PROCESS(resetn, clk25MHz)
+              PROCESS(resetn_25MHz, clk25MHz)
                 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
               BEGIN
-                IF resetn = '0' THEN
+                IF resetn_25MHz = '0' THEN
                   Rdata              <= (OTHERS => '0');
                   r.coarse_time_load <= (OTHERS => '0');
                   r.soft_reset       <= '0';
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
+                  rstn_in    => resetn_25MHz,
                   clk_out => clk24_576MHz,
-                  rstn    => resetn,
+                  rstn_out => resetn_24_576MHz,
                   sin     => tick,
                   sout    => new_timecode);
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
+                  rstn_in    => resetn_25MHz,
                   clk_out => clk24_576MHz,
-                  rstn    => resetn,
+                  rstn_out => resetn_24_576MHz,
                   sin     => coarsetime_reg_updated,
                   sout    => new_coarsetime);
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
+                  rstn_in    => resetn_25MHz,
                   clk_out => clk24_576MHz,
-                  rstn    => resetn,
+                  rstn_out => resetn_24_576MHz,
                   sin     => soft_reset,
                   sout    => soft_reset_sync);
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk24_576MHz,
+                  rstn_in    => resetn_24_576MHz,
                   clk_out => clk25MHz,
-                  rstn    => resetn,
+                  rstn_out => resetn_25MHz,
                   sin     => time_new_49,
                   sout    => time_new);
-              PROCESS (clk25MHz, resetn)
+              PROCESS (clk25MHz, resetn_25MHz)
               BEGIN  -- PROCESS
-                IF resetn = '0' THEN                -- asynchronous reset (active low)
+                IF resetn_25MHz = '0' THEN                -- asynchronous reset (active low)
                   fine_time_s   <= (OTHERS => '0');
                   coarse_time_s <= (OTHERS => '0');
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN  -- rising clock edge
               END PROCESS;
-              rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
+              rstn_LFR_TM <= '0' WHEN resetn_24_576MHz = '0' ELSE
                              '0' WHEN soft_reset_sync = '1' ELSE
                              '1';
               -- HK
               -----------------------------------------------------------------------------
-              PROCESS (clk25MHz, resetn)
+              PROCESS (clk25MHz, resetn_25MHz)
                 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14;  -- freq = 2^(16-BIT)
                                       -- for each HK, the update frequency is freq/3
                                       --
                                       -- 4Hz and update for each
                                       -- HK is 1.33Hz
               BEGIN  -- PROCESS
-                IF resetn = '0' THEN                -- asynchronous reset (active low)
+                IF resetn_25MHz = '0' THEN                -- asynchronous reset (active low)
                   r.HK_temp_0 <= (OTHERS => '0');
                   r.HK_temp_1 <= (OTHERS => '0');
                   )
                 PORT MAP(
                   clk  => clk25MHz,
-                  rstn => resetn,
+                  rstn => resetn_25MHz,
                   pre           => pre,
                   N             => N,
                   );
               DAC_CAL_EN <= DAC_CAL_EN_s;
-            END Behavioral;
+            END Behavioral;
  No newline at end of file

lib/lpp/lfr_management/lpp_lfr_management.vhd +2 -1

                   NB_SECOND_DESYNC : INTEGER);
                 PORT (
                   clk25MHz         : IN  STD_LOGIC;
+                  resetn_25MHz     : IN  STD_LOGIC;
                   clk24_576MHz     : IN  STD_LOGIC;
-                  resetn        : IN  STD_LOGIC;
+                  resetn_24_576MHz : IN  STD_LOGIC;
                   grspw_tick       : IN  STD_LOGIC;
                   apbi             : IN  apb_slv_in_type;
                   apbo             : OUT apb_slv_out_type;

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