# HG changeset patch # User pellion # Date 2015-03-16 14:42:31 # Node ID 8e5e2afea36a3ed07b7013d947ad1d122fc1a25e # Parent 1388b2e7c598466a0b7dbf695a351d2c6c2c0a68 Update SDC for the MINI-LFR boards diff --git a/boards/MINI-LFR/MINI_LFR_synthesis.sdc b/boards/MINI-LFR/MINI_LFR_synthesis.sdc --- a/boards/MINI-LFR/MINI_LFR_synthesis.sdc +++ b/boards/MINI-LFR/MINI_LFR_synthesis.sdc @@ -12,8 +12,8 @@ # -define_clock {clk_50} -name {clk_50} -freq 100 -clockgroup default_clkgroup -route 5 -define_clock {clk_49} -name {clk_49} -freq 49.152 -clockgroup default_clkgroup -route 5 +define_clock -name {clk_50} -freq 100 -clockgroup default_clkgroup_50 -route 5 +define_clock -name {clk_49} -freq 49.152 -clockgroup default_clkgroup_49 -route 5 # # Clock to Clock @@ -22,8 +22,6 @@ define_clock {clk_49} -name {clk_49} - # # Inputs/Outputs # -define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} -define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} # @@ -37,6 +35,7 @@ define_input_delay -disable -defaul # # False Path # +set_false_path -from reset # # Path Delay @@ -47,7 +46,6 @@ define_input_delay -disable -defaul # define_global_attribute syn_useioff {1} define_global_attribute -disable syn_netlist_hierarchy {0} -define_attribute {etx_clk} syn_noclockbuf {1} # # I/O standards diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -185,6 +185,11 @@ ARCHITECTURE beh OF MINI_LFR_top IS SIGNAL rstn_25_d2 : STD_LOGIC; SIGNAL rstn_25_d3 : STD_LOGIC; + SIGNAL rstn_24 : STD_LOGIC; + SIGNAL rstn_24_d1 : STD_LOGIC; + SIGNAL rstn_24_d2 : STD_LOGIC; + SIGNAL rstn_24_d3 : STD_LOGIC; + SIGNAL rstn_50 : STD_LOGIC; SIGNAL rstn_50_d1 : STD_LOGIC; SIGNAL rstn_50_d2 : STD_LOGIC; @@ -198,7 +203,7 @@ ARCHITECTURE beh OF MINI_LFR_top IS -- SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0); + SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN -- beh @@ -272,9 +277,17 @@ BEGIN -- beh PROCESS (clk_49, reset) BEGIN -- PROCESS IF reset = '0' THEN -- asynchronous reset (active low) - clk_24 <= '0'; + clk_24 <= '0'; + rstn_24_d1 <= '0'; + rstn_24_d2 <= '0'; + rstn_24_d3 <= '0'; + rstn_24 <= '0'; ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge - clk_24 <= NOT clk_24; + clk_24 <= NOT clk_24; + rstn_24_d1 <= '1'; + rstn_24_d2 <= rstn_24_d1; + rstn_24_d3 <= rstn_24_d2; + rstn_24 <= rstn_24_d3; END IF; END PROCESS; @@ -315,9 +328,9 @@ BEGIN -- beh END IF; END PROCESS; - PROCESS (clk_24, rstn_25) + PROCESS (clk_24, rstn_24) BEGIN -- PROCESS - IF rstn_25 = '0' THEN -- asynchronous reset (active low) + IF rstn_24 = '0' THEN -- asynchronous reset (active low) I00_s <= '0'; ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge I00_s <= NOT I00_s; @@ -331,56 +344,56 @@ BEGIN -- beh nDCD2 <= '1'; -- - + leon3_soc_1 : leon3_soc GENERIC MAP ( - fabtech => apa3e, - memtech => apa3e, - padtech => inferred, - clktech => inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - IS_RADHARD => 0, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 0, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 1, - ENABLE_APB_UART => 1, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE, - ADDRESS_SIZE => 20, + fabtech => apa3e, + memtech => apa3e, + padtech => inferred, + clktech => inferred, + disas => 0, + dbguart => 0, + pclow => 2, + clk_freq => 25000, + IS_RADHARD => 0, + NB_CPU => 1, + ENABLE_FPU => 1, + FPU_NETLIST => 0, + ENABLE_DSU => 1, + ENABLE_AHB_UART => 1, + ENABLE_APB_UART => 1, + ENABLE_IRQMP => 1, + ENABLE_GPT => 1, + NB_AHB_MASTER => NB_AHB_MASTER, + NB_AHB_SLAVE => NB_AHB_SLAVE, + NB_APB_SLAVE => NB_APB_SLAVE, + ADDRESS_SIZE => 20, USES_IAP_MEMCTRLR => 0) PORT MAP ( - clk => clk_25, - reset => rstn_25, - errorn => errorn, - ahbrxd => TXD1, - ahbtxd => RXD1, - urxd1 => TXD2, - utxd1 => RXD2, - address => SRAM_A, - data => SRAM_DQ, - nSRAM_BE0 => SRAM_nBE(0), - nSRAM_BE1 => SRAM_nBE(1), - nSRAM_BE2 => SRAM_nBE(2), - nSRAM_BE3 => SRAM_nBE(3), - nSRAM_WE => SRAM_nWE, - nSRAM_CE => SRAM_CE_s, - nSRAM_OE => SRAM_nOE, + clk => clk_25, + reset => rstn_25, + errorn => errorn, + ahbrxd => TXD1, + ahbtxd => RXD1, + urxd1 => TXD2, + utxd1 => RXD2, + address => SRAM_A, + data => SRAM_DQ, + nSRAM_BE0 => SRAM_nBE(0), + nSRAM_BE1 => SRAM_nBE(1), + nSRAM_BE2 => SRAM_nBE(2), + nSRAM_BE3 => SRAM_nBE(3), + nSRAM_WE => SRAM_nWE, + nSRAM_CE => SRAM_CE_s, + nSRAM_OE => SRAM_nOE, nSRAM_READY => '0', SRAM_MBE => OPEN, - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); + apbi_ext => apbi_ext, + apbo_ext => apbo_ext, + ahbi_s_ext => ahbi_s_ext, + ahbo_s_ext => ahbo_s_ext, + ahbi_m_ext => ahbi_m_ext, + ahbo_m_ext => ahbo_m_ext); SRAM_CE <= SRAM_CE_s(0); ------------------------------------------------------------------------------- @@ -392,25 +405,26 @@ BEGIN -- beh pindex => 6, paddr => 6, pmask => 16#fff#, - FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 + FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set PORT MAP ( - clk25MHz => clk_25, - clk24_576MHz => clk_24, -- 49.152MHz/2 - resetn => rstn_25, - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - HK_sample => sample_hk, - HK_val => sample_val, - HK_sel => HK_SEL, - DAC_SDO => OPEN, - DAC_SCK => OPEN, - DAC_SYNC => OPEN, - DAC_CAL_EN => OPEN, - coarse_time => coarse_time, - fine_time => fine_time, - LFR_soft_rstn => LFR_soft_rstn + clk25MHz => clk_25, + resetn_25MHz => rstn_25, -- TODO + clk24_576MHz => clk_24, -- 49.152MHz/2 + resetn_24_576MHz => rstn_24, -- TODO + grspw_tick => swno.tickout, + apbi => apbi_ext, + apbo => apbo_ext(6), + HK_sample => sample_hk, + HK_val => sample_val, + HK_sel => HK_SEL, + DAC_SDO => OPEN, + DAC_SCK => OPEN, + DAC_SYNC => OPEN, + DAC_CAL_EN => OPEN, + coarse_time => coarse_time, + fine_time => fine_time, + LFR_soft_rstn => LFR_soft_rstn ); ----------------------------------------------------------------------- @@ -522,7 +536,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"000143") -- aa.bb.cc version + top_lfr_version => X"000144") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => LFR_rstn, @@ -566,7 +580,7 @@ BEGIN -- beh PORT MAP ( -- CONV cnv_clk => clk_24, - cnv_rstn => rstn_25, + cnv_rstn => rstn_24, cnv => ADC_nCS_sig, -- DATA clk => clk_25, @@ -589,7 +603,7 @@ BEGIN -- beh "0010001000100010" WHEN HK_SEL = "01" ELSE "0100010001000100" WHEN HK_SEL = "10" ELSE (OTHERS => '0'); - + ---------------------------------------------------------------------- --- GPIO ----------------------------------------------------------- diff --git a/designs/MINI-LFR_WFP_MS/Makefile b/designs/MINI-LFR_WFP_MS/Makefile --- a/designs/MINI-LFR_WFP_MS/Makefile +++ b/designs/MINI-LFR_WFP_MS/Makefile @@ -15,7 +15,7 @@ VHDLSIMFILES= testbench.vhd SIMTOP=testbench PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc -##SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc +SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut CLEAN=soft-clean diff --git a/lib/lpp/dsp/cic/cic_lfr_r2.vhd b/lib/lpp/dsp/cic/cic_lfr_r2.vhd --- a/lib/lpp/dsp/cic/cic_lfr_r2.vhd +++ b/lib/lpp/dsp/cic/cic_lfr_r2.vhd @@ -89,14 +89,10 @@ ARCHITECTURE beh OF cic_lfr_r2 IS SIGNAL addr_gen: STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL addr_read: STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL addr_write: STD_LOGIC_VECTOR(8 DOWNTO 0); - SIGNAL addr_write_mux: STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL addr_write_s: STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL data_we: STD_LOGIC; SIGNAL data_we_s: STD_LOGIC; SIGNAL data_wen : STD_LOGIC; --- SIGNAL data_write : STD_LOGIC_VECTOR(15 DOWNTO 0); --- SIGNAL data_read : STD_LOGIC_VECTOR(15 DOWNTO 0); --- SIGNAL data_read_pre : STD_LOGIC_VECTOR(15 DOWNTO 0); ----------------------------------------------------------------------------- SIGNAL sample_out_reg16 : sample_vector(8*2-1 DOWNTO 0, 15 DOWNTO 0); SIGNAL sample_out_reg256 : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0); @@ -394,4 +390,4 @@ BEGIN END GENERATE all_bits; END GENERATE all_channel_out_v; -END beh; +END beh; \ No newline at end of file diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd --- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd @@ -1,442 +1,442 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe PELLION --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- - -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -LIBRARY lpp; -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; - -ENTITY IIR_CEL_CTRLR_v3 IS - GENERIC ( - tech : INTEGER := 0; - Mem_use : INTEGER := use_RAM; - Sample_SZ : INTEGER := 18; - Coef_SZ : INTEGER := 9; - Coef_Nb : INTEGER := 25; - Coef_sel_SZ : INTEGER := 5; - Cels_count : INTEGER := 5; - ChanelsCount : INTEGER := 8); - PORT ( - rstn : IN STD_LOGIC; - clk : IN STD_LOGIC; - - virg_pos : IN INTEGER; - coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); - - sample_in1_val : IN STD_LOGIC; - sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); - sample_in2_val : IN STD_LOGIC; - sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); - - sample_out1_val : OUT STD_LOGIC; - sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); - sample_out2_val : OUT STD_LOGIC; - sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); -END IIR_CEL_CTRLR_v3; - -ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS - - COMPONENT RAM_CTRLR_v2 - GENERIC ( - tech : INTEGER; - Input_SZ_1 : INTEGER; - Mem_use : INTEGER); - PORT ( - rstn : IN STD_LOGIC; - clk : IN STD_LOGIC; - ram_write : IN STD_LOGIC; - ram_read : IN STD_LOGIC; - raddr_rst : IN STD_LOGIC; - raddr_add1 : IN STD_LOGIC; - waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); - sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)); - END COMPONENT; - - COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW - GENERIC ( - Sample_SZ : INTEGER; - Coef_SZ : INTEGER; - Coef_Nb : INTEGER; - Coef_sel_SZ : INTEGER); - PORT ( - rstn : IN STD_LOGIC; - clk : IN STD_LOGIC; - virg_pos : IN INTEGER; - coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); - in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); - ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); - alu_sel_input : IN STD_LOGIC; - alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); - alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0); - alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); - sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)); - END COMPONENT; - - COMPONENT IIR_CEL_CTRLR_v2_CONTROL - GENERIC ( - Coef_sel_SZ : INTEGER; - Cels_count : INTEGER; - ChanelsCount : INTEGER); - PORT ( - rstn : IN STD_LOGIC; - clk : IN STD_LOGIC; - sample_in_val : IN STD_LOGIC; - sample_in_rot : OUT STD_LOGIC; - sample_out_val : OUT STD_LOGIC; - sample_out_rot : OUT STD_LOGIC; - in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - ram_write : OUT STD_LOGIC; - ram_read : OUT STD_LOGIC; - raddr_rst : OUT STD_LOGIC; - raddr_add1 : OUT STD_LOGIC; - waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - alu_sel_input : OUT STD_LOGIC; - alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); - alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); - END COMPONENT; - - SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL ram_write : STD_LOGIC; - SIGNAL ram_read : STD_LOGIC; - SIGNAL raddr_rst : STD_LOGIC; - SIGNAL raddr_add1 : STD_LOGIC; - SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL alu_sel_input : STD_LOGIC; - SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); - SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0); - - SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); - SIGNAL sample_in_rotate : STD_LOGIC; - SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); - SIGNAL sample_out_val_s : STD_LOGIC; - SIGNAL sample_out_val_s2 : STD_LOGIC; - SIGNAL sample_out_rot_s : STD_LOGIC; - SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); - - SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); - - SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); - SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); - -- - SIGNAL sample_in_val : STD_LOGIC; - SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); - SIGNAL sample_out_val : STD_LOGIC; - SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - SIGNAL CHANNEL_SEL : STD_LOGIC; - - SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); - SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); - - SIGNAL ram_write_1 : STD_LOGIC; - SIGNAL ram_read_1 : STD_LOGIC; - SIGNAL raddr_rst_1 : STD_LOGIC; - SIGNAL raddr_add1_1 : STD_LOGIC; - SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL ram_write_2 : STD_LOGIC; - SIGNAL ram_read_2 : STD_LOGIC; - SIGNAL raddr_rst_2 : STD_LOGIC; - SIGNAL raddr_add1_2 : STD_LOGIC; - SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0); - ----------------------------------------------------------------------------- - TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE); - SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION; - - SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); - -BEGIN - - ----------------------------------------------------------------------------- - channel_val(0) <= sample_in1_val; - channel_val(1) <= sample_in2_val; - all_channel_input_valid: FOR I IN 1 DOWNTO 0 GENERATE - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - channel_ready(I) <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - IF channel_val(I) = '1' THEN - channel_ready(I) <= '1'; - ELSIF channel_done(I) = '1' THEN - channel_ready(I) <= '0'; - END IF; - END IF; - END PROCESS; - END GENERATE all_channel_input_valid; - ----------------------------------------------------------------------------- - all_channel_sample_out: FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE - all_bit: FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE - sample_out_zero(I,J) <= '0'; - END GENERATE all_bit; - END GENERATE all_channel_sample_out; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - state_channel_selection <= IDLE; - CHANNEL_SEL <= '0'; - sample_in_val <= '0'; - sample_out1_val <= '0'; - sample_out2_val <= '0'; - sample_out1 <= sample_out_zero; - sample_out2 <= sample_out_zero; - channel_done <= "00"; - - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - CASE state_channel_selection IS - WHEN IDLE => - CHANNEL_SEL <= '0'; - sample_in_val <= '0'; - sample_out1_val <= '0'; - sample_out2_val <= '0'; - channel_done <= "00"; - IF channel_ready(0) = '1' THEN - state_channel_selection <= ONGOING_1; - CHANNEL_SEL <= '0'; - sample_in_val <= '1'; - ELSIF channel_ready(1) = '1' THEN - state_channel_selection <= ONGOING_2; - CHANNEL_SEL <= '1'; - sample_in_val <= '1'; - END IF; - WHEN ONGOING_1 => - sample_in_val <= '0'; - IF sample_out_val = '1' THEN - state_channel_selection <= WAIT_STATE; - sample_out1 <= sample_out; - sample_out1_val <= '1'; - channel_done(0) <= '1'; - END IF; - WHEN ONGOING_2 => - sample_in_val <= '0'; - IF sample_out_val = '1' THEN - state_channel_selection <= WAIT_STATE; - sample_out2 <= sample_out; - sample_out2_val <= '1'; - channel_done(1) <= '1'; - END IF; - WHEN WAIT_STATE => - state_channel_selection <= IDLE; - CHANNEL_SEL <= '0'; - sample_in_val <= '0'; - sample_out1_val <= '0'; - sample_out2_val <= '0'; - channel_done <= "00"; - - WHEN OTHERS => NULL; - END CASE; - - END IF; - END PROCESS; - - sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2; - ----------------------------------------------------------------------------- - ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE - ram_output_2; - - ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0'; - ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0'; - raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1'; - raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0'; - waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00"; - - ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0'; - ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0'; - raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1'; - raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0'; - waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00"; - - RAM_CTRLR_v2_1: RAM_CTRLR_v2 - GENERIC MAP ( - tech => tech, - Input_SZ_1 => Sample_SZ, - Mem_use => Mem_use) - PORT MAP ( - clk => clk, - rstn => rstn, - ram_write => ram_write_1, - ram_read => ram_read_1, - raddr_rst => raddr_rst_1, - raddr_add1 => raddr_add1_1, - waddr_previous => waddr_previous_1, - sample_in => ram_input, - sample_out => ram_output_1); - - RAM_CTRLR_v2_2: RAM_CTRLR_v2 - GENERIC MAP ( - tech => tech, - Input_SZ_1 => Sample_SZ, - Mem_use => Mem_use) - PORT MAP ( - clk => clk, - rstn => rstn, - ram_write => ram_write_2, - ram_read => ram_read_2, - raddr_rst => raddr_rst_2, - raddr_add1 => raddr_add1_2, - waddr_previous => waddr_previous_2, - sample_in => ram_input, - sample_out => ram_output_2); - ----------------------------------------------------------------------------- - - IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW - GENERIC MAP ( - Sample_SZ => Sample_SZ, - Coef_SZ => Coef_SZ, - Coef_Nb => Coef_Nb, - Coef_sel_SZ => Coef_sel_SZ) - PORT MAP ( - rstn => rstn, - clk => clk, - virg_pos => virg_pos, - coefs => coefs, - --CTRL - in_sel_src => in_sel_src, - ram_sel_Wdata => ram_sel_Wdata, - -- - ram_input => ram_input, - ram_output => ram_output, - -- - alu_sel_input => alu_sel_input, - alu_sel_coeff => alu_sel_coeff, - alu_ctrl => alu_ctrl, - alu_comp => "00", - --DATA - sample_in => sample_in_s, - sample_out => sample_out_s); - ----------------------------------------------------------------------------- - - - IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL - GENERIC MAP ( - Coef_sel_SZ => Coef_sel_SZ, - Cels_count => Cels_count, - ChanelsCount => ChanelsCount) - PORT MAP ( - rstn => rstn, - clk => clk, - sample_in_val => sample_in_val, - sample_in_rot => sample_in_rotate, - sample_out_val => sample_out_val_s, - sample_out_rot => sample_out_rot_s, - - in_sel_src => in_sel_src, - ram_sel_Wdata => ram_sel_Wdata, - ram_write => ram_write, - ram_read => ram_read, - raddr_rst => raddr_rst, - raddr_add1 => raddr_add1, - waddr_previous => waddr_previous, - alu_sel_input => alu_sel_input, - alu_sel_coeff => alu_sel_coeff, - alu_ctrl => alu_ctrl); - - ----------------------------------------------------------------------------- - -- SAMPLE IN - ----------------------------------------------------------------------------- - loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE - - loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_in_buf(I, J) <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - IF sample_in_val = '1' THEN - sample_in_buf(I, J) <= sample_in(I, J); - ELSIF sample_in_rotate = '1' THEN - sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J); - END IF; - END IF; - END PROCESS; - END GENERATE loop_all_chanel; - - sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J); - - END GENERATE loop_all_sample; - - ----------------------------------------------------------------------------- - -- SAMPLE OUT - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_out_val <= '0'; - sample_out_val_s2 <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - sample_out_val <= sample_out_val_s2; - sample_out_val_s2 <= sample_out_val_s; - END IF; - END PROCESS; - - chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_out_s2(ChanelsCount-1, I) <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - IF sample_out_rot_s = '1' THEN - sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I); - END IF; - END IF; - END PROCESS; - END GENERATE chanel_HIGH; - - chanel_more : IF ChanelsCount > 1 GENERATE - all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE - all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_out_s2(J-1, I) <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - IF sample_out_rot_s = '1' THEN - sample_out_s2(J-1, I) <= sample_out_s2(J, I); - END IF; - END IF; - END PROCESS; - END GENERATE all_bit; - END GENERATE all_chanel; - END GENERATE chanel_more; - - sample_out <= sample_out_s2; -END ar_IIR_CEL_CTRLR_v3; +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY lpp; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; + +ENTITY IIR_CEL_CTRLR_v3 IS + GENERIC ( + tech : INTEGER := 0; + Mem_use : INTEGER := use_RAM; + Sample_SZ : INTEGER := 18; + Coef_SZ : INTEGER := 9; + Coef_Nb : INTEGER := 25; + Coef_sel_SZ : INTEGER := 5; + Cels_count : INTEGER := 5; + ChanelsCount : INTEGER := 8); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + virg_pos : IN INTEGER; + coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); + + sample_in1_val : IN STD_LOGIC; + sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + sample_in2_val : IN STD_LOGIC; + sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + + sample_out1_val : OUT STD_LOGIC; + sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + sample_out2_val : OUT STD_LOGIC; + sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); +END IIR_CEL_CTRLR_v3; + +ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS + + COMPONENT RAM_CTRLR_v2 + GENERIC ( + tech : INTEGER; + Input_SZ_1 : INTEGER; + Mem_use : INTEGER); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + ram_write : IN STD_LOGIC; + ram_read : IN STD_LOGIC; + raddr_rst : IN STD_LOGIC; + raddr_add1 : IN STD_LOGIC; + waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW + GENERIC ( + Sample_SZ : INTEGER; + Coef_SZ : INTEGER; + Coef_Nb : INTEGER; + Coef_sel_SZ : INTEGER); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + virg_pos : IN INTEGER; + coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); + in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + alu_sel_input : IN STD_LOGIC; + alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); + alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT IIR_CEL_CTRLR_v2_CONTROL + GENERIC ( + Coef_sel_SZ : INTEGER; + Cels_count : INTEGER; + ChanelsCount : INTEGER); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + sample_in_val : IN STD_LOGIC; + sample_in_rot : OUT STD_LOGIC; + sample_out_val : OUT STD_LOGIC; + sample_out_rot : OUT STD_LOGIC; + in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + ram_write : OUT STD_LOGIC; + ram_read : OUT STD_LOGIC; + raddr_rst : OUT STD_LOGIC; + raddr_add1 : OUT STD_LOGIC; + waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + alu_sel_input : OUT STD_LOGIC; + alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); + alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); + END COMPONENT; + + SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ram_write : STD_LOGIC; + SIGNAL ram_read : STD_LOGIC; + SIGNAL raddr_rst : STD_LOGIC; + SIGNAL raddr_add1 : STD_LOGIC; + SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL alu_sel_input : STD_LOGIC; + SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); + SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0); + + SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + SIGNAL sample_in_rotate : STD_LOGIC; + SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + SIGNAL sample_out_val_s : STD_LOGIC; + SIGNAL sample_out_val_s2 : STD_LOGIC; + SIGNAL sample_out_rot_s : STD_LOGIC; + SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + + SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + + SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + -- + SIGNAL sample_in_val : STD_LOGIC; + SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + SIGNAL sample_out_val : STD_LOGIC; + SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + SIGNAL CHANNEL_SEL : STD_LOGIC; + + SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + + SIGNAL ram_write_1 : STD_LOGIC; + SIGNAL ram_read_1 : STD_LOGIC; + SIGNAL raddr_rst_1 : STD_LOGIC; + SIGNAL raddr_add1_1 : STD_LOGIC; + SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL ram_write_2 : STD_LOGIC; + SIGNAL ram_read_2 : STD_LOGIC; + SIGNAL raddr_rst_2 : STD_LOGIC; + SIGNAL raddr_add1_2 : STD_LOGIC; + SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0); + ----------------------------------------------------------------------------- + TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE); + SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION; + + --SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + +BEGIN + + ----------------------------------------------------------------------------- + channel_val(0) <= sample_in1_val; + channel_val(1) <= sample_in2_val; + all_channel_input_valid : FOR I IN 1 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + channel_ready(I) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF channel_val(I) = '1' THEN + channel_ready(I) <= '1'; + ELSIF channel_done(I) = '1' THEN + channel_ready(I) <= '0'; + END IF; + END IF; + END PROCESS; + END GENERATE all_channel_input_valid; + ----------------------------------------------------------------------------- + + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + state_channel_selection <= IDLE; + CHANNEL_SEL <= '0'; + sample_in_val <= '0'; + sample_out1_val <= '0'; + sample_out2_val <= '0'; + all_channel_sample_out : FOR I IN ChanelsCount-1 DOWNTO 0 LOOP + all_bit : FOR J IN Sample_SZ-1 DOWNTO 0 LOOP + sample_out1(I, J) <= '0'; + sample_out2(I, J) <= '0'; + END LOOP all_bit; + END LOOP all_channel_sample_out; + channel_done <= "00"; + + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + CASE state_channel_selection IS + WHEN IDLE => + CHANNEL_SEL <= '0'; + sample_in_val <= '0'; + sample_out1_val <= '0'; + sample_out2_val <= '0'; + channel_done <= "00"; + IF channel_ready(0) = '1' THEN + state_channel_selection <= ONGOING_1; + CHANNEL_SEL <= '0'; + sample_in_val <= '1'; + ELSIF channel_ready(1) = '1' THEN + state_channel_selection <= ONGOING_2; + CHANNEL_SEL <= '1'; + sample_in_val <= '1'; + END IF; + WHEN ONGOING_1 => + sample_in_val <= '0'; + IF sample_out_val = '1' THEN + state_channel_selection <= WAIT_STATE; + sample_out1 <= sample_out; + sample_out1_val <= '1'; + channel_done(0) <= '1'; + END IF; + WHEN ONGOING_2 => + sample_in_val <= '0'; + IF sample_out_val = '1' THEN + state_channel_selection <= WAIT_STATE; + sample_out2 <= sample_out; + sample_out2_val <= '1'; + channel_done(1) <= '1'; + END IF; + WHEN WAIT_STATE => + state_channel_selection <= IDLE; + CHANNEL_SEL <= '0'; + sample_in_val <= '0'; + sample_out1_val <= '0'; + sample_out2_val <= '0'; + channel_done <= "00"; + + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS; + + sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2; + ----------------------------------------------------------------------------- + ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE + ram_output_2; + + ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0'; + ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0'; + raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1'; + raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0'; + waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00"; + + ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0'; + ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0'; + raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1'; + raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0'; + waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00"; + + RAM_CTRLR_v2_1 : RAM_CTRLR_v2 + GENERIC MAP ( + tech => tech, + Input_SZ_1 => Sample_SZ, + Mem_use => Mem_use) + PORT MAP ( + clk => clk, + rstn => rstn, + ram_write => ram_write_1, + ram_read => ram_read_1, + raddr_rst => raddr_rst_1, + raddr_add1 => raddr_add1_1, + waddr_previous => waddr_previous_1, + sample_in => ram_input, + sample_out => ram_output_1); + + RAM_CTRLR_v2_2 : RAM_CTRLR_v2 + GENERIC MAP ( + tech => tech, + Input_SZ_1 => Sample_SZ, + Mem_use => Mem_use) + PORT MAP ( + clk => clk, + rstn => rstn, + ram_write => ram_write_2, + ram_read => ram_read_2, + raddr_rst => raddr_rst_2, + raddr_add1 => raddr_add1_2, + waddr_previous => waddr_previous_2, + sample_in => ram_input, + sample_out => ram_output_2); + ----------------------------------------------------------------------------- + + IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW + GENERIC MAP ( + Sample_SZ => Sample_SZ, + Coef_SZ => Coef_SZ, + Coef_Nb => Coef_Nb, + Coef_sel_SZ => Coef_sel_SZ) + PORT MAP ( + rstn => rstn, + clk => clk, + virg_pos => virg_pos, + coefs => coefs, + --CTRL + in_sel_src => in_sel_src, + ram_sel_Wdata => ram_sel_Wdata, + -- + ram_input => ram_input, + ram_output => ram_output, + -- + alu_sel_input => alu_sel_input, + alu_sel_coeff => alu_sel_coeff, + alu_ctrl => alu_ctrl, + alu_comp => "00", + --DATA + sample_in => sample_in_s, + sample_out => sample_out_s); + ----------------------------------------------------------------------------- + + + IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL + GENERIC MAP ( + Coef_sel_SZ => Coef_sel_SZ, + Cels_count => Cels_count, + ChanelsCount => ChanelsCount) + PORT MAP ( + rstn => rstn, + clk => clk, + sample_in_val => sample_in_val, + sample_in_rot => sample_in_rotate, + sample_out_val => sample_out_val_s, + sample_out_rot => sample_out_rot_s, + + in_sel_src => in_sel_src, + ram_sel_Wdata => ram_sel_Wdata, + ram_write => ram_write, + ram_read => ram_read, + raddr_rst => raddr_rst, + raddr_add1 => raddr_add1, + waddr_previous => waddr_previous, + alu_sel_input => alu_sel_input, + alu_sel_coeff => alu_sel_coeff, + alu_ctrl => alu_ctrl); + + ----------------------------------------------------------------------------- + -- SAMPLE IN + ----------------------------------------------------------------------------- + loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE + + loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_in_buf(I, J) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF sample_in_val = '1' THEN + sample_in_buf(I, J) <= sample_in(I, J); + ELSIF sample_in_rotate = '1' THEN + sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J); + END IF; + END IF; + END PROCESS; + END GENERATE loop_all_chanel; + + sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J); + + END GENERATE loop_all_sample; + + ----------------------------------------------------------------------------- + -- SAMPLE OUT + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_out_val <= '0'; + sample_out_val_s2 <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + sample_out_val <= sample_out_val_s2; + sample_out_val_s2 <= sample_out_val_s; + END IF; + END PROCESS; + + chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_out_s2(ChanelsCount-1, I) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF sample_out_rot_s = '1' THEN + sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I); + END IF; + END IF; + END PROCESS; + END GENERATE chanel_HIGH; + + chanel_more : IF ChanelsCount > 1 GENERATE + all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE + all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_out_s2(J-1, I) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF sample_out_rot_s = '1' THEN + sample_out_s2(J-1, I) <= sample_out_s2(J, I); + END IF; + END IF; + END PROCESS; + END GENERATE all_bit; + END GENERATE all_chanel; + END GENERATE chanel_more; + + sample_out <= sample_out_s2; +END ar_IIR_CEL_CTRLR_v3; diff --git a/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd b/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd --- a/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd +++ b/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd @@ -31,10 +31,11 @@ ENTITY SYNC_VALID_BIT IS NB_FF_OF_SYNC : INTEGER := 2); PORT ( clk_in : IN STD_LOGIC; - clk_out : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sin : IN STD_LOGIC; - sout : OUT STD_LOGIC); + rstn_in : IN STD_LOGIC; + clk_out : IN STD_LOGIC; + rstn_out : IN STD_LOGIC; + sin : IN STD_LOGIC; + sout : OUT STD_LOGIC); END SYNC_VALID_BIT; ARCHITECTURE beh OF SYNC_VALID_BIT IS @@ -45,7 +46,7 @@ BEGIN -- beh lpp_front_to_level_1: lpp_front_to_level PORT MAP ( clk => clk_in, - rstn => rstn, + rstn => rstn_in, sin => sin, sout => s_1); @@ -54,14 +55,14 @@ BEGIN -- beh NB_FF_OF_SYNC => NB_FF_OF_SYNC) PORT MAP ( clk => clk_out, - rstn => rstn, + rstn => rstn_out, A => s_1, A_sync => s_2); lpp_front_detection_1: lpp_front_detection PORT MAP ( clk => clk_out, - rstn => rstn, + rstn => rstn_out, sin => s_2, sout => sout); diff --git a/lib/lpp/general_purpose/general_purpose.vhd b/lib/lpp/general_purpose/general_purpose.vhd --- a/lib/lpp/general_purpose/general_purpose.vhd +++ b/lib/lpp/general_purpose/general_purpose.vhd @@ -366,15 +366,27 @@ Constant CLR_MAC_V0 : std_logic_vector(3 sout : OUT STD_LOGIC); END COMPONENT; + --COMPONENT SYNC_VALID_BIT + -- GENERIC ( + -- NB_FF_OF_SYNC : INTEGER); + -- PORT ( + -- clk_in : IN STD_LOGIC; + -- clk_out : IN STD_LOGIC; + -- rstn : IN STD_LOGIC; + -- sin : IN STD_LOGIC; + -- sout : OUT STD_LOGIC); + --END COMPONENT; + COMPONENT SYNC_VALID_BIT GENERIC ( NB_FF_OF_SYNC : INTEGER); PORT ( - clk_in : IN STD_LOGIC; - clk_out : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sin : IN STD_LOGIC; - sout : OUT STD_LOGIC); + clk_in : IN STD_LOGIC; + rstn_in : IN STD_LOGIC; + clk_out : IN STD_LOGIC; + rstn_out : IN STD_LOGIC; + sin : IN STD_LOGIC; + sout : OUT STD_LOGIC); END COMPONENT; COMPONENT RR_Arbiter_4 diff --git a/lib/lpp/lfr_management/apb_lfr_management.vhd b/lib/lpp/lfr_management/apb_lfr_management.vhd --- a/lib/lpp/lfr_management/apb_lfr_management.vhd +++ b/lib/lpp/lfr_management/apb_lfr_management.vhd @@ -46,9 +46,10 @@ ENTITY apb_lfr_management IS ); PORT ( - clk25MHz : IN STD_LOGIC; --! Clock - clk24_576MHz : IN STD_LOGIC; --! secondary clock - resetn : IN STD_LOGIC; --! Reset + clk25MHz : IN STD_LOGIC; --! Clock + resetn_25MHz : IN STD_LOGIC; --! Reset + clk24_576MHz : IN STD_LOGIC; --! secondary clock + resetn_24_576MHz : IN STD_LOGIC; --! Reset grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received @@ -155,11 +156,11 @@ BEGIN LFR_soft_rstn <= NOT r.LFR_soft_reset; - PROCESS(resetn, clk25MHz) + PROCESS(resetn_25MHz, clk25MHz) VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); BEGIN - IF resetn = '0' THEN + IF resetn_25MHz = '0' THEN Rdata <= (OTHERS => '0'); r.coarse_time_load <= (OTHERS => '0'); r.soft_reset <= '0'; @@ -324,8 +325,9 @@ BEGIN NB_FF_OF_SYNC => 2) PORT MAP ( clk_in => clk25MHz, + rstn_in => resetn_25MHz, clk_out => clk24_576MHz, - rstn => resetn, + rstn_out => resetn_24_576MHz, sin => tick, sout => new_timecode); @@ -334,8 +336,9 @@ BEGIN NB_FF_OF_SYNC => 2) PORT MAP ( clk_in => clk25MHz, + rstn_in => resetn_25MHz, clk_out => clk24_576MHz, - rstn => resetn, + rstn_out => resetn_24_576MHz, sin => coarsetime_reg_updated, sout => new_coarsetime); @@ -344,8 +347,9 @@ BEGIN NB_FF_OF_SYNC => 2) PORT MAP ( clk_in => clk25MHz, + rstn_in => resetn_25MHz, clk_out => clk24_576MHz, - rstn => resetn, + rstn_out => resetn_24_576MHz, sin => soft_reset, sout => soft_reset_sync); @@ -383,16 +387,17 @@ BEGIN NB_FF_OF_SYNC => 2) PORT MAP ( clk_in => clk24_576MHz, + rstn_in => resetn_24_576MHz, clk_out => clk25MHz, - rstn => resetn, + rstn_out => resetn_25MHz, sin => time_new_49, sout => time_new); - PROCESS (clk25MHz, resetn) + PROCESS (clk25MHz, resetn_25MHz) BEGIN -- PROCESS - IF resetn = '0' THEN -- asynchronous reset (active low) + IF resetn_25MHz = '0' THEN -- asynchronous reset (active low) fine_time_s <= (OTHERS => '0'); coarse_time_s <= (OTHERS => '0'); ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge @@ -404,7 +409,7 @@ BEGIN END PROCESS; - rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE + rstn_LFR_TM <= '0' WHEN resetn_24_576MHz = '0' ELSE '0' WHEN soft_reset_sync = '1' ELSE '1'; @@ -433,15 +438,15 @@ BEGIN -- HK ----------------------------------------------------------------------------- - PROCESS (clk25MHz, resetn) + PROCESS (clk25MHz, resetn_25MHz) CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT) - -- for each HK, the update frequency is freq/3 - -- - -- for 14, the update frequency is - -- 4Hz and update for each - -- HK is 1.33Hz + -- for each HK, the update frequency is freq/3 + -- + -- for 14, the update frequency is + -- 4Hz and update for each + -- HK is 1.33Hz BEGIN -- PROCESS - IF resetn = '0' THEN -- asynchronous reset (active low) + IF resetn_25MHz = '0' THEN -- asynchronous reset (active low) r.HK_temp_0 <= (OTHERS => '0'); r.HK_temp_1 <= (OTHERS => '0'); @@ -459,13 +464,13 @@ BEGIN CASE HK_sel_s IS WHEN "00" => r.HK_temp_0 <= HK_sample; - HK_sel_s <= "01"; + HK_sel_s <= "01"; WHEN "01" => r.HK_temp_1 <= HK_sample; - HK_sel_s <= "10"; + HK_sel_s <= "10"; WHEN "10" => r.HK_temp_2 <= HK_sample; - HK_sel_s <= "00"; + HK_sel_s <= "00"; WHEN OTHERS => NULL; END CASE; END IF; @@ -489,7 +494,7 @@ BEGIN ) PORT MAP( clk => clk25MHz, - rstn => resetn, + rstn => resetn_25MHz, pre => pre, N => N, @@ -509,4 +514,4 @@ BEGIN ); DAC_CAL_EN <= DAC_CAL_EN_s; -END Behavioral; +END Behavioral; \ No newline at end of file diff --git a/lib/lpp/lfr_management/lpp_lfr_management.vhd b/lib/lpp/lfr_management/lpp_lfr_management.vhd --- a/lib/lpp/lfr_management/lpp_lfr_management.vhd +++ b/lib/lpp/lfr_management/lpp_lfr_management.vhd @@ -38,22 +38,23 @@ PACKAGE lpp_lfr_management IS FIRST_DIVISION : INTEGER; NB_SECOND_DESYNC : INTEGER); PORT ( - clk25MHz : IN STD_LOGIC; - clk24_576MHz : IN STD_LOGIC; - resetn : IN STD_LOGIC; - grspw_tick : IN STD_LOGIC; - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - HK_val : IN STD_LOGIC; - HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - DAC_SDO : OUT STD_LOGIC; - DAC_SCK : OUT STD_LOGIC; - DAC_SYNC : OUT STD_LOGIC; - DAC_CAL_EN : OUT STD_LOGIC; - coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - LFR_soft_rstn : OUT STD_LOGIC); + clk25MHz : IN STD_LOGIC; + resetn_25MHz : IN STD_LOGIC; + clk24_576MHz : IN STD_LOGIC; + resetn_24_576MHz : IN STD_LOGIC; + grspw_tick : IN STD_LOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + HK_val : IN STD_LOGIC; + HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + DAC_SDO : OUT STD_LOGIC; + DAC_SCK : OUT STD_LOGIC; + DAC_SYNC : OUT STD_LOGIC; + DAC_CAL_EN : OUT STD_LOGIC; + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + LFR_soft_rstn : OUT STD_LOGIC); END COMPONENT; COMPONENT lfr_time_management @@ -74,7 +75,7 @@ PACKAGE lpp_lfr_management IS COMPONENT coarse_time_counter GENERIC ( - NB_SECOND_DESYNC : INTEGER ); + NB_SECOND_DESYNC : INTEGER); PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; @@ -91,8 +92,8 @@ PACKAGE lpp_lfr_management IS COMPONENT fine_time_counter GENERIC ( - WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0); - FIRST_DIVISION : INTEGER ); + WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0); + FIRST_DIVISION : INTEGER); PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC;