HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r560:8e5e2afea36a

Update SDC for the MINI-LFR boards

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r560:8e5e2afea36a JC

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r560:8e5e2afea36a

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boards/MINI-LFR/MINI_LFR_synthesis.sdc +3 -5

             #
-            define_clock  {clk_50} -name {clk_50}  -freq 100    -clockgroup default_clkgroup -route 5
+            define_clock  -name {clk_50}  -freq 100    -clockgroup default_clkgroup_50 -route 5
-            define_clock  {clk_49} -name {clk_49}  -freq 49.152 -clockgroup default_clkgroup -route 5
+            define_clock  -name {clk_49}  -freq 49.152 -clockgroup default_clkgroup_49 -route 5
             #
             # Clock to Clock
             #
             # Inputs/Outputs
             #
-            define_output_delay -disable     -default  5.00 -improve 0.00 -route 0.00 -ref {clk:r}
-            define_input_delay -disable      -default  5.00 -improve 0.00 -route 0.00 -ref {clk:r}
             #
             #
             # False Path
             #
+            set_false_path -from reset
             #
             # Path Delay
             #
             define_global_attribute          syn_useioff {1}
             define_global_attribute -disable syn_netlist_hierarchy {0}
-            define_attribute          {etx_clk} syn_noclockbuf {1}
             #
             # I/O standards

designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +83 -69

               SIGNAL rstn_25_d2 : STD_LOGIC;
               SIGNAL rstn_25_d3 : STD_LOGIC;
+              SIGNAL rstn_24    : STD_LOGIC;
+              SIGNAL rstn_24_d1 : STD_LOGIC;
+              SIGNAL rstn_24_d2 : STD_LOGIC;
+              SIGNAL rstn_24_d3 : STD_LOGIC;
               SIGNAL rstn_50    : STD_LOGIC;
               SIGNAL rstn_50_d1 : STD_LOGIC;
               SIGNAL rstn_50_d2 : STD_LOGIC;
               --
               SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
-              SIGNAL HK_SEL    : STD_LOGIC_VECTOR( 1 DOWNTO 0);
+              SIGNAL HK_SEL    : STD_LOGIC_VECTOR(1 DOWNTO 0);
             BEGIN  -- beh
               PROCESS (clk_49, reset)
               BEGIN  -- PROCESS
                 IF reset = '0' THEN                 -- asynchronous reset (active low)
-                  clk_24 <= '0';
+                  clk_24     <= '0';
+                  rstn_24_d1 <= '0';
+                  rstn_24_d2 <= '0';
+                  rstn_24_d3 <= '0';
+                  rstn_24    <= '0';
                 ELSIF clk_49'EVENT AND clk_49 = '1' THEN  -- rising clock edge
-                  clk_24 <= NOT clk_24;
+                  clk_24     <= NOT clk_24;
+                  rstn_24_d1 <= '1';
+                  rstn_24_d2 <= rstn_24_d1;
+                  rstn_24_d3 <= rstn_24_d2;
+                  rstn_24    <= rstn_24_d3;
                 END IF;
               END PROCESS;
                 END IF;
               END PROCESS;
-              PROCESS (clk_24, rstn_25)
+              PROCESS (clk_24, rstn_24)
               BEGIN  -- PROCESS
-                IF rstn_25 = '0' THEN               -- asynchronous reset (active low)
+                IF rstn_24 = '0' THEN               -- asynchronous reset (active low)
                   I00_s <= '0';
                 ELSIF clk_24'EVENT AND clk_24 = '1' THEN  -- rising clock edge
                   I00_s <= NOT I00_s;
               nDCD2 <= '1';
               --
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
-                  fabtech         => apa3e,
+                  fabtech           => apa3e,
-                  memtech         => apa3e,
+                  memtech           => apa3e,
-                  padtech         => inferred,
+                  padtech           => inferred,
-                  clktech         => inferred,
+                  clktech           => inferred,
-                  disas           => 0,
+                  disas             => 0,
-                  dbguart         => 0,
+                  dbguart           => 0,
-                  pclow           => 2,
+                  pclow             => 2,
-                  clk_freq        => 25000,
+                  clk_freq          => 25000,
-                  IS_RADHARD      => 0,
+                  IS_RADHARD        => 0,
-                  NB_CPU          => 1,
+                  NB_CPU            => 1,
-                  ENABLE_FPU      => 1,
+                  ENABLE_FPU        => 1,
-                  FPU_NETLIST     => 0,
+                  FPU_NETLIST       => 0,
-                  ENABLE_DSU      => 1,
+                  ENABLE_DSU        => 1,
-                  ENABLE_AHB_UART => 1,
+                  ENABLE_AHB_UART   => 1,
-                  ENABLE_APB_UART => 1,
+                  ENABLE_APB_UART   => 1,
-                  ENABLE_IRQMP    => 1,
+                  ENABLE_IRQMP      => 1,
-                  ENABLE_GPT      => 1,
+                  ENABLE_GPT        => 1,
-                  NB_AHB_MASTER   => NB_AHB_MASTER,
+                  NB_AHB_MASTER     => NB_AHB_MASTER,
-                  NB_AHB_SLAVE    => NB_AHB_SLAVE,
+                  NB_AHB_SLAVE      => NB_AHB_SLAVE,
-                  NB_APB_SLAVE    => NB_APB_SLAVE,
+                  NB_APB_SLAVE      => NB_APB_SLAVE,
-                  ADDRESS_SIZE    => 20,
+                  ADDRESS_SIZE      => 20,
                   USES_IAP_MEMCTRLR => 0)
                 PORT MAP (
-                  clk       => clk_25,
+                  clk         => clk_25,
-                  reset     => rstn_25,
+                  reset       => rstn_25,
-                  errorn    => errorn,
+                  errorn      => errorn,
-                  ahbrxd    => TXD1,
+                  ahbrxd      => TXD1,
-                  ahbtxd    => RXD1,
+                  ahbtxd      => RXD1,
-                  urxd1     => TXD2,
+                  urxd1       => TXD2,
-                  utxd1     => RXD2,
+                  utxd1       => RXD2,
-                  address   => SRAM_A,
+                  address     => SRAM_A,
-                  data      => SRAM_DQ,
+                  data        => SRAM_DQ,
-                  nSRAM_BE0 => SRAM_nBE(0),
+                  nSRAM_BE0   => SRAM_nBE(0),
-                  nSRAM_BE1 => SRAM_nBE(1),
+                  nSRAM_BE1   => SRAM_nBE(1),
-                  nSRAM_BE2 => SRAM_nBE(2),
+                  nSRAM_BE2   => SRAM_nBE(2),
-                  nSRAM_BE3 => SRAM_nBE(3),
+                  nSRAM_BE3   => SRAM_nBE(3),
-                  nSRAM_WE  => SRAM_nWE,
+                  nSRAM_WE    => SRAM_nWE,
-                  nSRAM_CE  => SRAM_CE_s,
+                  nSRAM_CE    => SRAM_CE_s,
-                  nSRAM_OE  => SRAM_nOE,
+                  nSRAM_OE    => SRAM_nOE,
                   nSRAM_READY => '0',
                   SRAM_MBE    => OPEN,
-                  apbi_ext   => apbi_ext,
+                  apbi_ext    => apbi_ext,
-                  apbo_ext   => apbo_ext,
+                  apbo_ext    => apbo_ext,
-                  ahbi_s_ext => ahbi_s_ext,
+                  ahbi_s_ext  => ahbi_s_ext,
-                  ahbo_s_ext => ahbo_s_ext,
+                  ahbo_s_ext  => ahbo_s_ext,
-                  ahbi_m_ext => ahbi_m_ext,
+                  ahbi_m_ext  => ahbi_m_ext,
-                  ahbo_m_ext => ahbo_m_ext);
+                  ahbo_m_ext  => ahbo_m_ext);
               SRAM_CE <= SRAM_CE_s(0);
             -------------------------------------------------------------------------------
                   pindex           => 6,
                   paddr            => 6,
                   pmask            => 16#fff#,
-                  FIRST_DIVISION   => 374,  -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
+                  FIRST_DIVISION   => 374,      -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
-                  clk25MHz      => clk_25,
+                  clk25MHz         => clk_25,
-                  clk24_576MHz  => clk_24,          -- 49.152MHz/2
+                  resetn_25MHz     => rstn_25,      --      TODO
-                  resetn        => rstn_25,
+                  clk24_576MHz     => clk_24,       -- 49.152MHz/2
-                  grspw_tick    => swno.tickout,
+                  resetn_24_576MHz => rstn_24,      --      TODO
-                  apbi          => apbi_ext,
+                  grspw_tick       => swno.tickout,
-                  apbo          => apbo_ext(6),
+                  apbi             => apbi_ext,
-                  HK_sample     => sample_hk,
+                  apbo             => apbo_ext(6),
-                  HK_val        => sample_val,
+                  HK_sample        => sample_hk,
-                  HK_sel        => HK_SEL,
+                  HK_val           => sample_val,
-                  DAC_SDO       => OPEN,
+                  HK_sel           => HK_SEL,
-                  DAC_SCK       => OPEN,
+                  DAC_SDO          => OPEN,
-                  DAC_SYNC      => OPEN,
+                  DAC_SCK          => OPEN,
-                  DAC_CAL_EN    => OPEN,
+                  DAC_SYNC         => OPEN,
-                  coarse_time   => coarse_time,
+                  DAC_CAL_EN       => OPEN,
-                  fine_time     => fine_time,
+                  coarse_time      => coarse_time,
-                  LFR_soft_rstn => LFR_soft_rstn
+                  fine_time        => fine_time,
+                  LFR_soft_rstn    => LFR_soft_rstn
                   );
             -----------------------------------------------------------------------
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"000143")  -- aa.bb.cc version
+                  top_lfr_version        => X"000144")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                 PORT MAP (
                   -- CONV
                   cnv_clk    => clk_24,
-                  cnv_rstn   => rstn_25,
+                  cnv_rstn   => rstn_24,
                   cnv        => ADC_nCS_sig,
                   -- DATA
                   clk        => clk_25,
                            "0010001000100010" WHEN HK_SEL = "01" ELSE
                            "0100010001000100" WHEN HK_SEL = "10" ELSE
                            (OTHERS => '0');
             ----------------------------------------------------------------------
             ---  GPIO  -----------------------------------------------------------

designs/MINI-LFR_WFP_MS/Makefile +1 -1

             SIMTOP=testbench
             PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
             ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
-            ##SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
+            SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
             SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
             BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
             CLEAN=soft-clean

lib/lpp/dsp/cic/cic_lfr_r2.vhd +1 -5

               SIGNAL addr_gen: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL addr_read: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL addr_write: STD_LOGIC_VECTOR(8 DOWNTO 0);
-              SIGNAL addr_write_mux: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL addr_write_s: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL data_we: STD_LOGIC;
               SIGNAL data_we_s: STD_LOGIC;
               SIGNAL data_wen       : STD_LOGIC;
-            --  SIGNAL data_write     : STD_LOGIC_VECTOR(15 DOWNTO 0);
-            --  SIGNAL data_read      : STD_LOGIC_VECTOR(15 DOWNTO 0);
-            --  SIGNAL data_read_pre      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_out_reg16   : sample_vector(8*2-1 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_out_reg256  : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0);
                 END GENERATE all_bits;
               END GENERATE all_channel_out_v;
-            END beh;
+            END beh;
  No newline at end of file

lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd +442 -442

This diff has been collapsed as it changes many lines, (884 lines changed) Show them Hide them
	@@ -1,442 +1,442
	1	------------------------------------------------------------------------------	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--	4	--
	5	-- This program is free software; you can redistribute it and/or modify	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.	8	-- (at your option) any later version.
	9	--	9	--
	10	-- This program is distributed in the hope that it will be useful,	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.	13	-- GNU General Public License for more details.
	14	--	14	--
	15	-- You should have received a copy of the GNU General Public License	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------	18	-------------------------------------------------------------------------------
	19	-- Author : Jean-christophe PELLION	19	-- Author : Jean-christophe PELLION
	20	-- Mail : jean-christophe.pellion@lpp.polytechnique.fr	20	-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
	21	-------------------------------------------------------------------------------	21	-------------------------------------------------------------------------------
	22		22
	23	LIBRARY IEEE;	23	LIBRARY IEEE;
	24	USE IEEE.numeric_std.ALL;	24	USE IEEE.numeric_std.ALL;
	25	USE IEEE.std_logic_1164.ALL;	25	USE IEEE.std_logic_1164.ALL;
	26		26
	27	LIBRARY techmap;	27	LIBRARY techmap;
	28	USE techmap.gencomp.ALL;	28	USE techmap.gencomp.ALL;
	29		29
	30	LIBRARY lpp;	30	LIBRARY lpp;
	31	USE lpp.iir_filter.ALL;	31	USE lpp.iir_filter.ALL;
	32	USE lpp.general_purpose.ALL;	32	USE lpp.general_purpose.ALL;
	33		33
	34	ENTITY IIR_CEL_CTRLR_v3 IS	34	ENTITY IIR_CEL_CTRLR_v3 IS
	35	GENERIC (	35	GENERIC (
	36	tech : INTEGER := 0;	36	tech : INTEGER := 0;
	37	Mem_use : INTEGER := use_RAM;	37	Mem_use : INTEGER := use_RAM;
	38	Sample_SZ : INTEGER := 18;	38	Sample_SZ : INTEGER := 18;
	39	Coef_SZ : INTEGER := 9;	39	Coef_SZ : INTEGER := 9;
	40	Coef_Nb : INTEGER := 25;	40	Coef_Nb : INTEGER := 25;
	41	Coef_sel_SZ : INTEGER := 5;	41	Coef_sel_SZ : INTEGER := 5;
	42	Cels_count : INTEGER := 5;	42	Cels_count : INTEGER := 5;
	43	ChanelsCount : INTEGER := 8);	43	ChanelsCount : INTEGER := 8);
	44	PORT (	44	PORT (
	45	rstn : IN STD_LOGIC;	45	rstn : IN STD_LOGIC;
	46	clk : IN STD_LOGIC;	46	clk : IN STD_LOGIC;
	47		47
	48	virg_pos : IN INTEGER;	48	virg_pos : IN INTEGER;
	49	coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);	49	coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
	50		50
	51	sample_in1_val : IN STD_LOGIC;	51	sample_in1_val : IN STD_LOGIC;
	52	sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);	52	sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
	53	sample_in2_val : IN STD_LOGIC;	53	sample_in2_val : IN STD_LOGIC;
	54	sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);	54	sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
	55		55
	56	sample_out1_val : OUT STD_LOGIC;	56	sample_out1_val : OUT STD_LOGIC;
	57	sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);	57	sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
	58	sample_out2_val : OUT STD_LOGIC;	58	sample_out2_val : OUT STD_LOGIC;
	59	sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));	59	sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
	60	END IIR_CEL_CTRLR_v3;	60	END IIR_CEL_CTRLR_v3;
	61		61
	62	ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS	62	ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS
	63		63
	64	COMPONENT RAM_CTRLR_v2	64	COMPONENT RAM_CTRLR_v2
	65	GENERIC (	65	GENERIC (
	66	tech : INTEGER;	66	tech : INTEGER;
	67	Input_SZ_1 : INTEGER;	67	Input_SZ_1 : INTEGER;
	68	Mem_use : INTEGER);	68	Mem_use : INTEGER);
	69	PORT (	69	PORT (
	70	rstn : IN STD_LOGIC;	70	rstn : IN STD_LOGIC;
	71	clk : IN STD_LOGIC;	71	clk : IN STD_LOGIC;
	72	ram_write : IN STD_LOGIC;	72	ram_write : IN STD_LOGIC;
	73	ram_read : IN STD_LOGIC;	73	ram_read : IN STD_LOGIC;
	74	raddr_rst : IN STD_LOGIC;	74	raddr_rst : IN STD_LOGIC;
	75	raddr_add1 : IN STD_LOGIC;	75	raddr_add1 : IN STD_LOGIC;
	76	waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);	76	waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	77	sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);	77	sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
	78	sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));	78	sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
	79	END COMPONENT;	79	END COMPONENT;
	80		80
	81	COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW	81	COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW
	82	GENERIC (	82	GENERIC (
	83	Sample_SZ : INTEGER;	83	Sample_SZ : INTEGER;
	84	Coef_SZ : INTEGER;	84	Coef_SZ : INTEGER;
	85	Coef_Nb : INTEGER;	85	Coef_Nb : INTEGER;
	86	Coef_sel_SZ : INTEGER);	86	Coef_sel_SZ : INTEGER);
	87	PORT (	87	PORT (
	88	rstn : IN STD_LOGIC;	88	rstn : IN STD_LOGIC;
	89	clk : IN STD_LOGIC;	89	clk : IN STD_LOGIC;
	90	virg_pos : IN INTEGER;	90	virg_pos : IN INTEGER;
	91	coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);	91	coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
	92	in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);	92	in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	93	ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);	93	ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	94	ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);	94	ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
	95	ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);	95	ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
	96	alu_sel_input : IN STD_LOGIC;	96	alu_sel_input : IN STD_LOGIC;
	97	alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);	97	alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
	98	alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);	98	alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
	99	alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);	99	alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	100	sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);	100	sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
	101	sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));	101	sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
	102	END COMPONENT;	102	END COMPONENT;
	103		103
	104	COMPONENT IIR_CEL_CTRLR_v2_CONTROL	104	COMPONENT IIR_CEL_CTRLR_v2_CONTROL
	105	GENERIC (	105	GENERIC (
	106	Coef_sel_SZ : INTEGER;	106	Coef_sel_SZ : INTEGER;
	107	Cels_count : INTEGER;	107	Cels_count : INTEGER;
	108	ChanelsCount : INTEGER);	108	ChanelsCount : INTEGER);
	109	PORT (	109	PORT (
	110	rstn : IN STD_LOGIC;	110	rstn : IN STD_LOGIC;
	111	clk : IN STD_LOGIC;	111	clk : IN STD_LOGIC;
	112	sample_in_val : IN STD_LOGIC;	112	sample_in_val : IN STD_LOGIC;
	113	sample_in_rot : OUT STD_LOGIC;	113	sample_in_rot : OUT STD_LOGIC;
	114	sample_out_val : OUT STD_LOGIC;	114	sample_out_val : OUT STD_LOGIC;
	115	sample_out_rot : OUT STD_LOGIC;	115	sample_out_rot : OUT STD_LOGIC;
	116	in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);	116	in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
	117	ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);	117	ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
	118	ram_write : OUT STD_LOGIC;	118	ram_write : OUT STD_LOGIC;
	119	ram_read : OUT STD_LOGIC;	119	ram_read : OUT STD_LOGIC;
	120	raddr_rst : OUT STD_LOGIC;	120	raddr_rst : OUT STD_LOGIC;
	121	raddr_add1 : OUT STD_LOGIC;	121	raddr_add1 : OUT STD_LOGIC;
	122	waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);	122	waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
	123	alu_sel_input : OUT STD_LOGIC;	123	alu_sel_input : OUT STD_LOGIC;
	124	alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);	124	alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
	125	alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));	125	alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
	126	END COMPONENT;	126	END COMPONENT;
	127		127
	128	SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);	128	SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
	129	SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);	129	SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
	130	SIGNAL ram_write : STD_LOGIC;	130	SIGNAL ram_write : STD_LOGIC;
	131	SIGNAL ram_read : STD_LOGIC;	131	SIGNAL ram_read : STD_LOGIC;
	132	SIGNAL raddr_rst : STD_LOGIC;	132	SIGNAL raddr_rst : STD_LOGIC;
	133	SIGNAL raddr_add1 : STD_LOGIC;	133	SIGNAL raddr_add1 : STD_LOGIC;
	134	SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);	134	SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
	135	SIGNAL alu_sel_input : STD_LOGIC;	135	SIGNAL alu_sel_input : STD_LOGIC;
	136	SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);	136	SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
	137	SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);	137	SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
	138		138
	139	SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);	139	SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
	140	SIGNAL sample_in_rotate : STD_LOGIC;	140	SIGNAL sample_in_rotate : STD_LOGIC;
	141	SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);	141	SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
	142	SIGNAL sample_out_val_s : STD_LOGIC;	142	SIGNAL sample_out_val_s : STD_LOGIC;
	143	SIGNAL sample_out_val_s2 : STD_LOGIC;	143	SIGNAL sample_out_val_s2 : STD_LOGIC;
	144	SIGNAL sample_out_rot_s : STD_LOGIC;	144	SIGNAL sample_out_rot_s : STD_LOGIC;
	145	SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);	145	SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
	146		146
	147	SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);	147	SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
	148		148
	149	SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);	149	SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
	150	SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);	150	SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
	151	--	151	--
	152	SIGNAL sample_in_val : STD_LOGIC;	152	SIGNAL sample_in_val : STD_LOGIC;
	153	SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);	153	SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
	154	SIGNAL sample_out_val : STD_LOGIC;	154	SIGNAL sample_out_val : STD_LOGIC;
	155	SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);	155	SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
	156		156
	157	-----------------------------------------------------------------------------	157	-----------------------------------------------------------------------------
	158	--	158	--
	159	-----------------------------------------------------------------------------	159	-----------------------------------------------------------------------------
	160	SIGNAL CHANNEL_SEL : STD_LOGIC;	160	SIGNAL CHANNEL_SEL : STD_LOGIC;
	161		161
	162	SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);	162	SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
	163	SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);	163	SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
	164		164
	165	SIGNAL ram_write_1 : STD_LOGIC;	165	SIGNAL ram_write_1 : STD_LOGIC;
	166	SIGNAL ram_read_1 : STD_LOGIC;	166	SIGNAL ram_read_1 : STD_LOGIC;
	167	SIGNAL raddr_rst_1 : STD_LOGIC;	167	SIGNAL raddr_rst_1 : STD_LOGIC;
	168	SIGNAL raddr_add1_1 : STD_LOGIC;	168	SIGNAL raddr_add1_1 : STD_LOGIC;
	169	SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);	169	SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
	170		170
	171	SIGNAL ram_write_2 : STD_LOGIC;	171	SIGNAL ram_write_2 : STD_LOGIC;
	172	SIGNAL ram_read_2 : STD_LOGIC;	172	SIGNAL ram_read_2 : STD_LOGIC;
	173	SIGNAL raddr_rst_2 : STD_LOGIC;	173	SIGNAL raddr_rst_2 : STD_LOGIC;
	174	SIGNAL raddr_add1_2 : STD_LOGIC;	174	SIGNAL raddr_add1_2 : STD_LOGIC;
	175	SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0);	175	SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
	176	-----------------------------------------------------------------------------	176	-----------------------------------------------------------------------------
	177	SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0);	177	SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0);
	178	SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0);	178	SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0);
	179	SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0);	179	SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0);
	180	-----------------------------------------------------------------------------	180	-----------------------------------------------------------------------------
	181	TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE);	181	TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE);
	182	SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION;	182	SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION;
	183		183
	184	SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);	184	--SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
	185		185
	186	BEGIN	186	BEGIN
	187		187
	188	-----------------------------------------------------------------------------	188	-----------------------------------------------------------------------------
	189	channel_val(0) <= sample_in1_val;	189	channel_val(0) <= sample_in1_val;
	190	channel_val(1) <= sample_in2_val;	190	channel_val(1) <= sample_in2_val;
	191	all_channel_input_valid: FOR I IN 1 DOWNTO 0 GENERATE	191	all_channel_input_valid : FOR I IN 1 DOWNTO 0 GENERATE
	192	PROCESS (clk, rstn)	192	PROCESS (clk, rstn)
	193	BEGIN -- PROCESS	193	BEGIN -- PROCESS
	194	IF rstn = '0' THEN -- asynchronous reset (active low)	194	IF rstn = '0' THEN -- asynchronous reset (active low)
	195	channel_ready(I) <= '0';	195	channel_ready(I) <= '0';
	196	ELSIF clk'~~event~~ AND clk = '1' THEN -- rising clock edge	196	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	197	IF channel_val(I) = '1' THEN	197	IF channel_val(I) = '1' THEN
	198	channel_ready(I) <= '1';	198	channel_ready(I) <= '1';
	199	ELSIF channel_done(I) = '1' THEN	199	ELSIF channel_done(I) = '1' THEN
	200	channel_ready(I) <= '0';	200	channel_ready(I) <= '0';
	201	END IF;	201	END IF;
	202	END IF;	202	END IF;
	203	END PROCESS;	203	END PROCESS;
	204	END GENERATE all_channel_input_valid;	204	END GENERATE all_channel_input_valid;
	205	-----------------------------------------------------------------------------	205	-----------------------------------------------------------------------------
	206	all_channel_sample_out: FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE	206
	207	all_bit: FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE	207
	208	sample_out_zero(I,J) <= '0';	208	PROCESS (clk, rstn)
	209	END GENERATE all_bit;	209	BEGIN -- PROCESS
	210	END GENERATE all_channel_sample_out;	210	IF rstn = '0' THEN -- asynchronous reset (active low)
	211		211	state_channel_selection <= IDLE;
	212	PROCESS (clk, rstn)	212	CHANNEL_SEL <= '0';
	213	BEGIN -- PROCESS	213	sample_in_val <= '0';
	214	IF rstn = '0' THEN -- asynchronous reset (active low)	214	sample_out1_val <= '0';
	215	state_channel_selection <= IDLE;	215	sample_out2_val <= '0';
	216	CHANNEL_SEL <= '0';	216	all_channel_sample_out : FOR I IN ChanelsCount-1 DOWNTO 0 LOOP
	217	sample_in_val <= '0';	217	all_bit : FOR J IN Sample_SZ-1 DOWNTO 0 LOOP
	218	sample_out1~~_val~~ <= '0';	218	sample_out1(I, J) <= '0';
	219	sample_out2~~_val~~ <= '0';	219	sample_out2(I, J) <= '0';
	220	sample_out1 <= sample_out_zero;	220	END LOOP all_bit;
	221	sample_out2 <= sample_out_zero;	221	END LOOP all_channel_sample_out;
	222	channel_done <= "00";	222	channel_done <= "00";
	223		223
	224	ELSIF clk'~~event~~ AND clk = '1' THEN -- rising clock edge	224	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	225	CASE state_channel_selection IS	225	CASE state_channel_selection IS
	226	WHEN IDLE =>	226	WHEN IDLE =>
	227	CHANNEL_SEL <= '0';	227	CHANNEL_SEL <= '0';
	228	sample_in_val <= '0';	228	sample_in_val <= '0';
	229	sample_out1_val <= '0';	229	sample_out1_val <= '0';
	230	sample_out2_val <= '0';	230	sample_out2_val <= '0';
	231	channel_done <= "00";	231	channel_done <= "00";
	232	IF channel_ready(0) = '1' THEN	232	IF channel_ready(0) = '1' THEN
	233	state_channel_selection <= ONGOING_1;	233	state_channel_selection <= ONGOING_1;
	234	CHANNEL_SEL <= '0';	234	CHANNEL_SEL <= '0';
	235	sample_in_val <= '1';	235	sample_in_val <= '1';
	236	ELSIF channel_ready(1) = '1' THEN	236	ELSIF channel_ready(1) = '1' THEN
	237	state_channel_selection <= ONGOING_2;	237	state_channel_selection <= ONGOING_2;
	238	CHANNEL_SEL <= '1';	238	CHANNEL_SEL <= '1';
	239	sample_in_val <= '1';	239	sample_in_val <= '1';
	240	END IF;	240	END IF;
	241	WHEN ONGOING_1 =>	241	WHEN ONGOING_1 =>
	242	sample_in_val <= '0';	242	sample_in_val <= '0';
	243	IF sample_out_val = '1' THEN	243	IF sample_out_val = '1' THEN
	244	state_channel_selection <= WAIT_STATE;	244	state_channel_selection <= WAIT_STATE;
	245	sample_out1 <= sample_out;	245	sample_out1 <= sample_out;
	246	sample_out1_val <= '1';	246	sample_out1_val <= '1';
	247	channel_done(0) <= '1';	247	channel_done(0) <= '1';
	248	END IF;	248	END IF;
	249	WHEN ONGOING_2 =>	249	WHEN ONGOING_2 =>
	250	sample_in_val <= '0';	250	sample_in_val <= '0';
	251	IF sample_out_val = '1' THEN	251	IF sample_out_val = '1' THEN
	252	state_channel_selection <= WAIT_STATE;	252	state_channel_selection <= WAIT_STATE;
	253	sample_out2 <= sample_out;	253	sample_out2 <= sample_out;
	254	sample_out2_val <= '1';	254	sample_out2_val <= '1';
	255	channel_done(1) <= '1';	255	channel_done(1) <= '1';
	256	END IF;	256	END IF;
	257	WHEN WAIT_STATE =>	257	WHEN WAIT_STATE =>
	258	state_channel_selection <= IDLE;	258	state_channel_selection <= IDLE;
	259	CHANNEL_SEL <= '0';	259	CHANNEL_SEL <= '0';
	260	sample_in_val <= '0';	260	sample_in_val <= '0';
	261	sample_out1_val <= '0';	261	sample_out1_val <= '0';
	262	sample_out2_val <= '0';	262	sample_out2_val <= '0';
	263	channel_done <= "00";	263	channel_done <= "00";
	264		264
	265	WHEN OTHERS => NULL;	265	WHEN OTHERS => NULL;
	266	END CASE;	266	END CASE;
	267		267
	268	END IF;	268	END IF;
	269	END PROCESS;	269	END PROCESS;
	270		270
	271	sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2;	271	sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2;
	272	-----------------------------------------------------------------------------	272	-----------------------------------------------------------------------------
	273	ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE	273	ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE
	274	ram_output_2;	274	ram_output_2;
	275		275
	276	ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0';	276	ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0';
	277	ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0';	277	ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0';
	278	raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1';	278	raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1';
	279	raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0';	279	raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0';
	280	waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00";	280	waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00";
	281		281
	282	ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0';	282	ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0';
	283	ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0';	283	ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0';
	284	raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1';	284	raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1';
	285	raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0';	285	raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0';
	286	waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00";	286	waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00";
	287		287
	288	RAM_CTRLR_v2_1: RAM_CTRLR_v2	288	RAM_CTRLR_v2_1 : RAM_CTRLR_v2
	289	GENERIC MAP (	289	GENERIC MAP (
	290	tech => tech,	290	tech => tech,
	291	Input_SZ_1 => Sample_SZ,	291	Input_SZ_1 => Sample_SZ,
	292	Mem_use => Mem_use)	292	Mem_use => Mem_use)
	293	PORT MAP (	293	PORT MAP (
	294	clk => clk,	294	clk => clk,
	295	rstn => rstn,	295	rstn => rstn,
	296	ram_write => ram_write_1,	296	ram_write => ram_write_1,
	297	ram_read => ram_read_1,	297	ram_read => ram_read_1,
	298	raddr_rst => raddr_rst_1,	298	raddr_rst => raddr_rst_1,
	299	raddr_add1 => raddr_add1_1,	299	raddr_add1 => raddr_add1_1,
	300	waddr_previous => waddr_previous_1,	300	waddr_previous => waddr_previous_1,
	301	sample_in => ram_input,	301	sample_in => ram_input,
	302	sample_out => ram_output_1);	302	sample_out => ram_output_1);
	303		303
	304	RAM_CTRLR_v2_2: RAM_CTRLR_v2	304	RAM_CTRLR_v2_2 : RAM_CTRLR_v2
	305	GENERIC MAP (	305	GENERIC MAP (
	306	tech => tech,	306	tech => tech,
	307	Input_SZ_1 => Sample_SZ,	307	Input_SZ_1 => Sample_SZ,
	308	Mem_use => Mem_use)	308	Mem_use => Mem_use)
	309	PORT MAP (	309	PORT MAP (
	310	clk => clk,	310	clk => clk,
	311	rstn => rstn,	311	rstn => rstn,
	312	ram_write => ram_write_2,	312	ram_write => ram_write_2,
	313	ram_read => ram_read_2,	313	ram_read => ram_read_2,
	314	raddr_rst => raddr_rst_2,	314	raddr_rst => raddr_rst_2,
	315	raddr_add1 => raddr_add1_2,	315	raddr_add1 => raddr_add1_2,
	316	waddr_previous => waddr_previous_2,	316	waddr_previous => waddr_previous_2,
	317	sample_in => ram_input,	317	sample_in => ram_input,
	318	sample_out => ram_output_2);	318	sample_out => ram_output_2);
	319	-----------------------------------------------------------------------------	319	-----------------------------------------------------------------------------
	320		320
	321	IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW	321	IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW
	322	GENERIC MAP (	322	GENERIC MAP (
	323	Sample_SZ => Sample_SZ,	323	Sample_SZ => Sample_SZ,
	324	Coef_SZ => Coef_SZ,	324	Coef_SZ => Coef_SZ,
	325	Coef_Nb => Coef_Nb,	325	Coef_Nb => Coef_Nb,
	326	Coef_sel_SZ => Coef_sel_SZ)	326	Coef_sel_SZ => Coef_sel_SZ)
	327	PORT MAP (	327	PORT MAP (
	328	rstn => rstn,	328	rstn => rstn,
	329	clk => clk,	329	clk => clk,
	330	virg_pos => virg_pos,	330	virg_pos => virg_pos,
	331	coefs => coefs,	331	coefs => coefs,
	332	--CTRL	332	--CTRL
	333	in_sel_src => in_sel_src,	333	in_sel_src => in_sel_src,
	334	ram_sel_Wdata => ram_sel_Wdata,	334	ram_sel_Wdata => ram_sel_Wdata,
	335	--	335	--
	336	ram_input => ram_input,	336	ram_input => ram_input,
	337	ram_output => ram_output,	337	ram_output => ram_output,
	338	--	338	--
	339	alu_sel_input => alu_sel_input,	339	alu_sel_input => alu_sel_input,
	340	alu_sel_coeff => alu_sel_coeff,	340	alu_sel_coeff => alu_sel_coeff,
	341	alu_ctrl => alu_ctrl,	341	alu_ctrl => alu_ctrl,
	342	alu_comp => "00",	342	alu_comp => "00",
	343	--DATA	343	--DATA
	344	sample_in => sample_in_s,	344	sample_in => sample_in_s,
	345	sample_out => sample_out_s);	345	sample_out => sample_out_s);
	346	-----------------------------------------------------------------------------	346	-----------------------------------------------------------------------------
	347		347
	348		348
	349	IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL	349	IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
	350	GENERIC MAP (	350	GENERIC MAP (
	351	Coef_sel_SZ => Coef_sel_SZ,	351	Coef_sel_SZ => Coef_sel_SZ,
	352	Cels_count => Cels_count,	352	Cels_count => Cels_count,
	353	ChanelsCount => ChanelsCount)	353	ChanelsCount => ChanelsCount)
	354	PORT MAP (	354	PORT MAP (
	355	rstn => rstn,	355	rstn => rstn,
	356	clk => clk,	356	clk => clk,
	357	sample_in_val => sample_in_val,	357	sample_in_val => sample_in_val,
	358	sample_in_rot => sample_in_rotate,	358	sample_in_rot => sample_in_rotate,
	359	sample_out_val => sample_out_val_s,	359	sample_out_val => sample_out_val_s,
	360	sample_out_rot => sample_out_rot_s,	360	sample_out_rot => sample_out_rot_s,
	361		361
	362	in_sel_src => in_sel_src,	362	in_sel_src => in_sel_src,
	363	ram_sel_Wdata => ram_sel_Wdata,	363	ram_sel_Wdata => ram_sel_Wdata,
	364	ram_write => ram_write,	364	ram_write => ram_write,
	365	ram_read => ram_read,	365	ram_read => ram_read,
	366	raddr_rst => raddr_rst,	366	raddr_rst => raddr_rst,
	367	raddr_add1 => raddr_add1,	367	raddr_add1 => raddr_add1,
	368	waddr_previous => waddr_previous,	368	waddr_previous => waddr_previous,
	369	alu_sel_input => alu_sel_input,	369	alu_sel_input => alu_sel_input,
	370	alu_sel_coeff => alu_sel_coeff,	370	alu_sel_coeff => alu_sel_coeff,
	371	alu_ctrl => alu_ctrl);	371	alu_ctrl => alu_ctrl);
	372		372
	373	-----------------------------------------------------------------------------	373	-----------------------------------------------------------------------------
	374	-- SAMPLE IN	374	-- SAMPLE IN
	375	-----------------------------------------------------------------------------	375	-----------------------------------------------------------------------------
	376	loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE	376	loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
	377		377
	378	loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE	378	loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
	379	PROCESS (clk, rstn)	379	PROCESS (clk, rstn)
	380	BEGIN -- PROCESS	380	BEGIN -- PROCESS
	381	IF rstn = '0' THEN -- asynchronous reset (active low)	381	IF rstn = '0' THEN -- asynchronous reset (active low)
	382	sample_in_buf(I, J) <= '0';	382	sample_in_buf(I, J) <= '0';
	383	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge	383	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	384	IF sample_in_val = '1' THEN	384	IF sample_in_val = '1' THEN
	385	sample_in_buf(I, J) <= sample_in(I, J);	385	sample_in_buf(I, J) <= sample_in(I, J);
	386	ELSIF sample_in_rotate = '1' THEN	386	ELSIF sample_in_rotate = '1' THEN
	387	sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);	387	sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
	388	END IF;	388	END IF;
	389	END IF;	389	END IF;
	390	END PROCESS;	390	END PROCESS;
	391	END GENERATE loop_all_chanel;	391	END GENERATE loop_all_chanel;
	392		392
	393	sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);	393	sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
	394		394
	395	END GENERATE loop_all_sample;	395	END GENERATE loop_all_sample;
	396		396
	397	-----------------------------------------------------------------------------	397	-----------------------------------------------------------------------------
	398	-- SAMPLE OUT	398	-- SAMPLE OUT
	399	-----------------------------------------------------------------------------	399	-----------------------------------------------------------------------------
	400	PROCESS (clk, rstn)	400	PROCESS (clk, rstn)
	401	BEGIN -- PROCESS	401	BEGIN -- PROCESS
	402	IF rstn = '0' THEN -- asynchronous reset (active low)	402	IF rstn = '0' THEN -- asynchronous reset (active low)
	403	sample_out_val <= '0';	403	sample_out_val <= '0';
	404	sample_out_val_s2 <= '0';	404	sample_out_val_s2 <= '0';
	405	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge	405	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	406	sample_out_val <= sample_out_val_s2;	406	sample_out_val <= sample_out_val_s2;
	407	sample_out_val_s2 <= sample_out_val_s;	407	sample_out_val_s2 <= sample_out_val_s;
	408	END IF;	408	END IF;
	409	END PROCESS;	409	END PROCESS;
	410		410
	411	chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE	411	chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
	412	PROCESS (clk, rstn)	412	PROCESS (clk, rstn)
	413	BEGIN -- PROCESS	413	BEGIN -- PROCESS
	414	IF rstn = '0' THEN -- asynchronous reset (active low)	414	IF rstn = '0' THEN -- asynchronous reset (active low)
	415	sample_out_s2(ChanelsCount-1, I) <= '0';	415	sample_out_s2(ChanelsCount-1, I) <= '0';
	416	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge	416	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	417	IF sample_out_rot_s = '1' THEN	417	IF sample_out_rot_s = '1' THEN
	418	sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);	418	sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
	419	END IF;	419	END IF;
	420	END IF;	420	END IF;
	421	END PROCESS;	421	END PROCESS;
	422	END GENERATE chanel_HIGH;	422	END GENERATE chanel_HIGH;
	423		423
	424	chanel_more : IF ChanelsCount > 1 GENERATE	424	chanel_more : IF ChanelsCount > 1 GENERATE
	425	all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE	425	all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
	426	all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE	426	all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
	427	PROCESS (clk, rstn)	427	PROCESS (clk, rstn)
	428	BEGIN -- PROCESS	428	BEGIN -- PROCESS
	429	IF rstn = '0' THEN -- asynchronous reset (active low)	429	IF rstn = '0' THEN -- asynchronous reset (active low)
	430	sample_out_s2(J-1, I) <= '0';	430	sample_out_s2(J-1, I) <= '0';
	431	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge	431	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	432	IF sample_out_rot_s = '1' THEN	432	IF sample_out_rot_s = '1' THEN
	433	sample_out_s2(J-1, I) <= sample_out_s2(J, I);	433	sample_out_s2(J-1, I) <= sample_out_s2(J, I);
	434	END IF;	434	END IF;
	435	END IF;	435	END IF;
	436	END PROCESS;	436	END PROCESS;
	437	END GENERATE all_bit;	437	END GENERATE all_bit;
	438	END GENERATE all_chanel;	438	END GENERATE all_chanel;
	439	END GENERATE chanel_more;	439	END GENERATE chanel_more;
	440		440
	441	sample_out <= sample_out_s2;	441	sample_out <= sample_out_s2;
	442	END ar_IIR_CEL_CTRLR_v3;	442	END ar_IIR_CEL_CTRLR_v3;

lib/lpp/general_purpose/SYNC_VALID_BIT.vhd +8 -7

                 NB_FF_OF_SYNC : INTEGER := 2);
               PORT (
                 clk_in  : IN  STD_LOGIC;
-                clk_out : IN  STD_LOGIC;
+                rstn_in : IN  STD_LOGIC;
-                rstn    : IN  STD_LOGIC;
+                clk_out  : IN  STD_LOGIC;
-                sin     : IN  STD_LOGIC;
+                rstn_out : IN  STD_LOGIC;
-                sout    : OUT STD_LOGIC);
+                sin      : IN  STD_LOGIC;
+                sout     : OUT STD_LOGIC);
             END SYNC_VALID_BIT;
             ARCHITECTURE beh OF SYNC_VALID_BIT IS
               lpp_front_to_level_1: lpp_front_to_level
                 PORT MAP (
                   clk  => clk_in,
-                  rstn => rstn,
+                  rstn => rstn_in,
                   sin  => sin,
                   sout => s_1);
                   NB_FF_OF_SYNC => NB_FF_OF_SYNC)
                 PORT MAP (
                   clk    => clk_out,
-                  rstn   => rstn,
+                  rstn   => rstn_out,
                   A      => s_1,
                   A_sync => s_2);
               lpp_front_detection_1: lpp_front_detection
                 PORT MAP (
                   clk  => clk_out,
-                  rstn => rstn,
+                  rstn => rstn_out,
                   sin  => s_2,
                   sout => sout);

lib/lpp/general_purpose/general_purpose.vhd +17 -5

@@ -366,15 +366,27 Constant CLR_MAC_V0 : std_logic_vector(3
366	sout : OUT STD_LOGIC);	366	sout : OUT STD_LOGIC);
367	END COMPONENT;	367	END COMPONENT;
368		368
		369	--COMPONENT SYNC_VALID_BIT
		370	-- GENERIC (
		371	-- NB_FF_OF_SYNC : INTEGER);
		372	-- PORT (
		373	-- clk_in : IN STD_LOGIC;
		374	-- clk_out : IN STD_LOGIC;
		375	-- rstn : IN STD_LOGIC;
		376	-- sin : IN STD_LOGIC;
		377	-- sout : OUT STD_LOGIC);
		378	--END COMPONENT;
		379
369	COMPONENT SYNC_VALID_BIT	380	COMPONENT SYNC_VALID_BIT
370	GENERIC (	381	GENERIC (
371	NB_FF_OF_SYNC : INTEGER);	382	NB_FF_OF_SYNC : INTEGER);
372	PORT (	383	PORT (
373	clk_in : IN STD_LOGIC;	384	clk_in : IN STD_LOGIC;
374	~~clk_out~~ : IN STD_LOGIC;	385	rstn_in : IN STD_LOGIC;
375	~~rstn~~ : IN STD_LOGIC;	386	clk_out : IN STD_LOGIC;
376	~~sin~~ : IN STD_LOGIC;	387	rstn_out : IN STD_LOGIC;
377	s~~out~~ : ~~OUT~~ STD_LOGIC);	388	sin : IN STD_LOGIC;
		389	sout : OUT STD_LOGIC);
378	END COMPONENT;	390	END COMPONENT;
379		391
380	COMPONENT RR_Arbiter_4	392	COMPONENT RR_Arbiter_4

lib/lpp/lfr_management/apb_lfr_management.vhd +29 -24

                 );
               PORT (
-                clk25MHz     : IN STD_LOGIC;        --! Clock
+                clk25MHz         : IN STD_LOGIC;    --! Clock
-                clk24_576MHz : IN STD_LOGIC;        --! secondary clock
+                resetn_25MHz     : IN STD_LOGIC;    --! Reset
-                resetn       : IN STD_LOGIC;        --! Reset
+                clk24_576MHz     : IN STD_LOGIC;    --! secondary clock
+                resetn_24_576MHz : IN STD_LOGIC;    --! Reset
                 grspw_tick : IN STD_LOGIC;  --! grspw signal asserted when a valid time-code is received
               LFR_soft_rstn <= NOT r.LFR_soft_reset;
-              PROCESS(resetn, clk25MHz)
+              PROCESS(resetn_25MHz, clk25MHz)
                 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
               BEGIN
-                IF resetn = '0' THEN
+                IF resetn_25MHz = '0' THEN
                   Rdata              <= (OTHERS => '0');
                   r.coarse_time_load <= (OTHERS => '0');
                   r.soft_reset       <= '0';
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
+                  rstn_in    => resetn_25MHz,
                   clk_out => clk24_576MHz,
-                  rstn    => resetn,
+                  rstn_out => resetn_24_576MHz,
                   sin     => tick,
                   sout    => new_timecode);
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
+                  rstn_in    => resetn_25MHz,
                   clk_out => clk24_576MHz,
-                  rstn    => resetn,
+                  rstn_out => resetn_24_576MHz,
                   sin     => coarsetime_reg_updated,
                   sout    => new_coarsetime);
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
+                  rstn_in    => resetn_25MHz,
                   clk_out => clk24_576MHz,
-                  rstn    => resetn,
+                  rstn_out => resetn_24_576MHz,
                   sin     => soft_reset,
                   sout    => soft_reset_sync);
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk24_576MHz,
+                  rstn_in    => resetn_24_576MHz,
                   clk_out => clk25MHz,
-                  rstn    => resetn,
+                  rstn_out => resetn_25MHz,
                   sin     => time_new_49,
                   sout    => time_new);
-              PROCESS (clk25MHz, resetn)
+              PROCESS (clk25MHz, resetn_25MHz)
               BEGIN  -- PROCESS
-                IF resetn = '0' THEN                -- asynchronous reset (active low)
+                IF resetn_25MHz = '0' THEN                -- asynchronous reset (active low)
                   fine_time_s   <= (OTHERS => '0');
                   coarse_time_s <= (OTHERS => '0');
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN  -- rising clock edge
               END PROCESS;
-              rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
+              rstn_LFR_TM <= '0' WHEN resetn_24_576MHz = '0' ELSE
                              '0' WHEN soft_reset_sync = '1' ELSE
                              '1';
               -- HK
               -----------------------------------------------------------------------------
-              PROCESS (clk25MHz, resetn)
+              PROCESS (clk25MHz, resetn_25MHz)
                 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14;  -- freq = 2^(16-BIT)
-                                                                -- for each HK, the update frequency is freq/3
+                                      -- for each HK, the update frequency is freq/3
-                                                                --
+                                      --
-                                                                -- for 14, the update frequency is
+                                      -- for 14, the update frequency is
-                                                                -- 4Hz and update for each
+                                      -- 4Hz and update for each
-                                                                -- HK is 1.33Hz
+                                      -- HK is 1.33Hz
               BEGIN  -- PROCESS
-                IF resetn = '0' THEN                -- asynchronous reset (active low)
+                IF resetn_25MHz = '0' THEN                -- asynchronous reset (active low)
                   r.HK_temp_0 <= (OTHERS => '0');
                   r.HK_temp_1 <= (OTHERS => '0');
                       CASE HK_sel_s IS
                         WHEN "00" =>
                           r.HK_temp_0 <= HK_sample;
-                          HK_sel_s <= "01";
+                          HK_sel_s    <= "01";
                         WHEN "01" =>
                           r.HK_temp_1 <= HK_sample;
-                          HK_sel_s <= "10";
+                          HK_sel_s    <= "10";
                         WHEN "10" =>
                           r.HK_temp_2 <= HK_sample;
-                          HK_sel_s <= "00";
+                          HK_sel_s    <= "00";
                         WHEN OTHERS => NULL;
                       END CASE;
                     END IF;
                   )
                 PORT MAP(
                   clk  => clk25MHz,
-                  rstn => resetn,
+                  rstn => resetn_25MHz,
                   pre           => pre,
                   N             => N,
                   );
               DAC_CAL_EN <= DAC_CAL_EN_s;
-            END Behavioral;
+            END Behavioral;
  No newline at end of file

lib/lpp/lfr_management/lpp_lfr_management.vhd +20 -19

                   FIRST_DIVISION   : INTEGER;
                   NB_SECOND_DESYNC : INTEGER);
                 PORT (
-                  clk25MHz      : IN  STD_LOGIC;
+                  clk25MHz         : IN  STD_LOGIC;
-                  clk24_576MHz  : IN  STD_LOGIC;
+                  resetn_25MHz     : IN  STD_LOGIC;
-                  resetn        : IN  STD_LOGIC;
+                  clk24_576MHz     : IN  STD_LOGIC;
-                  grspw_tick    : IN  STD_LOGIC;
+                  resetn_24_576MHz : IN  STD_LOGIC;
-                  apbi          : IN  apb_slv_in_type;
+                  grspw_tick       : IN  STD_LOGIC;
-                  apbo          : OUT apb_slv_out_type;
+                  apbi             : IN  apb_slv_in_type;
-                  HK_sample     : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+                  apbo             : OUT apb_slv_out_type;
-                  HK_val        : IN  STD_LOGIC;
+                  HK_sample        : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
-                  HK_sel        : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+                  HK_val           : IN  STD_LOGIC;
-                  DAC_SDO    : OUT STD_LOGIC;
+                  HK_sel           : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
-                  DAC_SCK    : OUT STD_LOGIC;
+                  DAC_SDO          : OUT STD_LOGIC;
-                  DAC_SYNC   : OUT STD_LOGIC;
+                  DAC_SCK          : OUT STD_LOGIC;
-                  DAC_CAL_EN : OUT STD_LOGIC;
+                  DAC_SYNC         : OUT STD_LOGIC;
-                  coarse_time   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  DAC_CAL_EN       : OUT STD_LOGIC;
-                  fine_time     : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+                  coarse_time      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-                  LFR_soft_rstn : OUT STD_LOGIC);
+                  fine_time        : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+                  LFR_soft_rstn    : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lfr_time_management
               COMPONENT coarse_time_counter
                 GENERIC (
-                  NB_SECOND_DESYNC : INTEGER );
+                  NB_SECOND_DESYNC : INTEGER);
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
               COMPONENT fine_time_counter
                 GENERIC (
-                  WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0);
+                  WAITING_TIME   : STD_LOGIC_VECTOR(15 DOWNTO 0);
-                  FIRST_DIVISION : INTEGER );
+                  FIRST_DIVISION : INTEGER);
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;

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