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1 | ---------------------------------------------------------------------------------- | |
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2 | -- Company: | |
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3 | -- Engineer: | |
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4 | -- | |
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5 | -- Create Date: 15:20:11 12/08/2013 | |
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6 | -- Design Name: | |
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7 | -- Module Name: GPMC_SLAVE - Behavioral | |
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8 | -- Project Name: | |
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9 | -- Target Devices: | |
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10 | -- Tool versions: | |
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11 | -- Description: | |
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12 | -- | |
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13 | -- Dependencies: | |
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14 | -- | |
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15 | -- Revision: | |
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16 | -- Revision 0.01 - File Created | |
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17 | -- Additional Comments: | |
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18 | -- | |
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19 | ---------------------------------------------------------------------------------- | |
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20 | library IEEE; | |
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21 | use IEEE.STD_LOGIC_1164.ALL; | |
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22 | use IEEE.numeric_std.all; | |
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23 | library grlib, techmap; | |
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24 | use grlib.stdlib.all; | |
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25 | use techmap.gencomp.all; | |
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26 | use techmap.allclkgen.all; | |
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27 | library lpp; | |
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28 | use lpp.general_purpose.all; | |
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29 | ||
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30 | entity GPMC_SLAVE is | |
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31 | generic ( | |
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32 | memtech : integer := 0; | |
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33 | padtech : integer := 0 | |
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34 | ); | |
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35 | Port ( | |
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36 | clk : in STD_LOGIC; | |
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37 | reset : in STD_LOGIC; | |
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38 | GPMC_AD : inout std_logic_vector(15 downto 0); | |
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39 | GPMC_A : in std_logic_vector(19 downto 0); | |
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40 | GPMC_CLK_MUX0 : in std_ulogic; | |
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41 | GPMC_WEN : in std_ulogic; | |
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42 | GPMC_OEN_REN : in std_ulogic; | |
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43 | GPMC_ADVN_ALE : in std_ulogic; | |
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44 | GPMC_CSN : in std_ulogic_vector(2 downto 0); | |
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45 | GPMC_BE0N_CLE : in std_ulogic; | |
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46 | GPMC_BE1N : in std_ulogic; | |
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47 | GPMC_WAIT0 : in std_ulogic; | |
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48 | GPMC_WPN : in std_ulogic | |
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49 | ); | |
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50 | end GPMC_SLAVE; | |
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51 | ||
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52 | architecture Behavioral of GPMC_SLAVE is | |
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53 | constant VectInit : std_logic_vector(15 downto 0):=(others => '0'); | |
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54 | ||
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55 | signal data_out :std_logic_vector(15 downto 0); | |
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56 | signal data_in :std_logic_vector(15 downto 0); | |
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57 | ||
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58 | type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0); | |
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59 | signal RAMarray : RAMarrayT:=(others => VectInit); | |
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60 | signal ramindex : integer range 0 to 255; | |
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61 | ||
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62 | begin | |
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63 | ||
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64 | data_pad : iopadv generic map (tech=> padtech,width => 16) | |
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65 | port map ( | |
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66 | pad => GPMC_AD(15 downto 0), | |
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67 | o => data_in(15 downto 0), | |
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68 | en => GPMC_OEN_REN, | |
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69 | i => data_out(15 downto 0) | |
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70 | ); | |
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71 | ||
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72 | process(reset,GPMC_CLK_MUX0) | |
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73 | begin | |
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74 | if reset = '0' then | |
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75 | data_out <= (others => '0'); | |
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76 | ramindex <= 0; | |
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77 | elsif GPMC_CLK_MUX0'event and GPMC_CLK_MUX0 = '1' then | |
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78 | ramindex <= to_integer(unsigned(GPMC_A)); | |
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79 | data_out <= RAMarray(ramindex); | |
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80 | if GPMC_WEN = '0' then | |
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81 | RAMarray(ramindex) <= data_in; | |
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82 | end if; | |
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83 | end if; | |
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84 | end process; | |
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85 | ||
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86 | end Behavioral; | |
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87 | ||
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88 | ||
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89 | ||
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90 | ||
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91 | ||
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92 | ||
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93 | ||
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94 | ||
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95 | ||
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96 | ||
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97 | ||
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98 | ||
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99 | ||
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100 | ||
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1 | 1 | |
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2 | 2 | NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE; |
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3 | 3 | NET "CLK" LOC = "K20"| slew=FAST | IOSTANDARD=LVTTL; |
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4 | 4 | NET "CLKM" TNM_NET = "clkm_net"; |
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5 |
TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%; |
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6 | ||
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5 | TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%; | |
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6 | ||
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7 | ||
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7 | 8 | NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE; |
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8 |
NET "RESET" LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL; |
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9 | NET "RESET" LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL; | |
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9 | 10 | |
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10 | 11 | NET "DAC_nCLR" LOC = "R11" | IOSTANDARD=LVTTL; |
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11 | 12 | NET "DAC_nCS" LOC = "T12" | IOSTANDARD=LVTTL; |
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12 | 13 | NET "CAL_IN_SCK" LOC = "R13" | IOSTANDARD=LVTTL; |
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13 | 14 | NET "DAC_SDI(0)" LOC = "P5" | IOSTANDARD=LVTTL; |
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14 | 15 | NET "DAC_SDI(1)" LOC = "M5" | IOSTANDARD=LVTTL; |
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15 | 16 | NET "DAC_SDI(2)" LOC = "C8" | IOSTANDARD=LVTTL; |
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16 | 17 | NET "DAC_SDI(3)" LOC = "M6" | IOSTANDARD=LVTTL; |
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17 | 18 | NET "DAC_SDI(4)" LOC = "K22" | IOSTANDARD=LVTTL; |
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18 | 19 | NET "DAC_SDI(5)" LOC = "L22" | IOSTANDARD=LVTTL; |
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19 | 20 | NET "DAC_SDI(6)" LOC = "G19" | IOSTANDARD=LVTTL; |
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20 |
NET "DAC_SDI(7)" LOC = "F20" | IOSTANDARD=LVTTL; |
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21 | NET "DAC_SDI(7)" LOC = "F20" | IOSTANDARD=LVTTL; | |
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21 | 22 | |
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22 | ||
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23 | ||
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23 | 24 | NET "TXD" LOC = "V22"| slew=FAST | IOSTANDARD=LVTTL; |
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24 | 25 | NET "RXD" LOC = "U22"| slew=FAST | IOSTANDARD=LVTTL; |
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25 | 26 | NET "LED(0)" LOC = "AB9"| slew=FAST | IOSTANDARD=LVTTL; |
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26 | 27 | NET "LED(1)" LOC = "AB8"| slew=FAST | IOSTANDARD=LVTTL; |
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27 |
NET "LED(2)" LOC = "AA8"| slew=FAST | IOSTANDARD=LVTTL; |
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28 | ||
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28 | NET "LED(2)" LOC = "AA8"| slew=FAST | IOSTANDARD=LVTTL; | |
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29 | ||
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29 | 30 | NET "urxd1" LOC = "D3" | IOSTANDARD=LVTTL; # Unused PIN |
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30 | 31 | NET "utxd1" LOC = "C4" | IOSTANDARD=LVTTL; # Unused PIN |
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31 | 32 | |
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32 | 33 | NET "sdcke" LOC = "B6" | slew=FAST | IOSTANDARD=LVTTL; # clk en |
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33 | 34 | NET "sdcsn" LOC = "G20"| slew=FAST | IOSTANDARD=LVTTL; # chip sel |
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34 | 35 | NET "sdwen" LOC = "D14"| slew=FAST | IOSTANDARD=LVTTL; # write en |
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35 | 36 | NET "sdrasn" LOC = "H19"| slew=FAST | IOSTANDARD=LVTTL; # row addr stb |
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36 | 37 | NET "sdcasn" LOC = "C14"| slew=FAST | IOSTANDARD=LVTTL; # col addr stb |
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37 | 38 | |
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38 | 39 | NET "sddqm(3)" LOC = "A5" | slew=FAST | IOSTANDARD=LVTTL; # data i/o mask |
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39 | 40 | NET "sddqm(2)" LOC = "D21"| slew=FAST | IOSTANDARD=LVTTL; # data i/o mask |
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40 | 41 | NET "sddqm(1)" LOC = "C7" | slew=FAST | IOSTANDARD=LVTTL; # data i/o mask |
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41 | 42 | NET "sddqm(0)" LOC = "D15"| slew=FAST | IOSTANDARD=LVTTL; # data i/o mask |
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42 | 43 | |
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43 | 44 | NET "sdclk" CLOCK_DEDICATED_ROUTE = FALSE; |
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44 | 45 | NET "sdclk" LOC = "A6" | slew=FAST | IOSTANDARD=LVTTL; # sdram clk output |
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45 | 46 | NET "sdba(1)" LOC = "J20"| slew=FAST | IOSTANDARD=LVTTL; # bank select address |
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46 | 47 | NET "sdba(0)" LOC = "G16"| slew=FAST | IOSTANDARD=LVTTL; # bank select address |
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47 | 48 | |
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48 | 49 | NET "Address(11)" LOC = "H8"| slew=FAST | IOSTANDARD=LVTTL; # sdram address |
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49 | 50 | NET "Address(10)" LOC = "G7"| slew=FAST | IOSTANDARD=LVTTL; # sdram address |
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50 | 51 | NET "Address(9)" LOC = "K7"| slew=FAST | IOSTANDARD=LVTTL; # sdram address |
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51 | 52 | NET "Address(8)" LOC = "H6"| slew=FAST | IOSTANDARD=LVTTL; # sdram address |
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52 | 53 | NET "Address(7)" LOC = "H5"| slew=FAST | IOSTANDARD=LVTTL; # sdram address |
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53 | 54 | NET "Address(6)" LOC = "K8"| slew=FAST | IOSTANDARD=LVTTL; # sdram address |
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54 | 55 | NET "Address(5)" LOC = "G4"| slew=FAST | IOSTANDARD=LVTTL; # sdram address |
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55 | 56 | NET "Address(4)" LOC = "H3"| slew=FAST | IOSTANDARD=LVTTL; # sdram address |
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56 | 57 | NET "Address(3)" LOC = "D2"| slew=FAST | IOSTANDARD=LVTTL; # sdram address |
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57 | 58 | NET "Address(2)" LOC = "B3"| slew=FAST | IOSTANDARD=LVTTL; # sdram address |
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58 | 59 | NET "Address(1)" LOC = "A2"| slew=FAST | IOSTANDARD=LVTTL; # sdram address |
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59 | 60 | NET "Address(0)" LOC = "C22"| slew=FAST | IOSTANDARD=LVTTL; # sdram address |
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60 | 61 | |
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61 | 62 | NET "Data(31)" LOC = "C5" | slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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62 | 63 | NET "Data(30)" LOC = "A4" | slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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63 | 64 | NET "Data(29)" LOC = "A3" | slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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64 | 65 | NET "Data(28)" LOC = "B2" | slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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65 | 66 | NET "Data(27)" LOC = "B1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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66 | 67 | NET "Data(26)" LOC = "C1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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67 | 68 | NET "Data(25)" LOC = "D1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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68 | 69 | NET "Data(24)" LOC = "E1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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69 | 70 | NET "Data(23)" LOC = "J22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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70 | 71 | NET "Data(22)" LOC = "H22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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71 | 72 | NET "Data(21)" LOC = "H21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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72 | 73 | NET "Data(20)" LOC = "G22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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73 | 74 | NET "Data(19)" LOC = "F22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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74 | 75 | NET "Data(18)" LOC = "F21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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75 | 76 | NET "Data(17)" LOC = "E22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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76 | 77 | NET "Data(16)" LOC = "D22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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77 | 78 | NET "Data(15)" LOC = "A7" | slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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78 | 79 | NET "Data(14)" LOC = "B8" | slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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79 | 80 | NET "Data(13)" LOC = "A8" | slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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80 | 81 | NET "Data(12)" LOC = "C9" | slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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81 | 82 | NET "Data(11)" LOC = "A9" | slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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82 | 83 | NET "Data(10)" LOC = "B10"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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83 | 84 | NET "Data(9)" LOC = "A10"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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84 | 85 | NET "Data(8)" LOC = "C11"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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85 | 86 | NET "Data(7)" LOC = "A13"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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86 | 87 | NET "Data(6)" LOC = "C13"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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87 | 88 | NET "Data(5)" LOC = "B22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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88 | 89 | NET "Data(4)" LOC = "B21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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89 | 90 | NET "Data(3)" LOC = "B20"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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90 | 91 | NET "Data(2)" LOC = "A20"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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91 | 92 | NET "Data(1)" LOC = "B18"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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92 | 93 | NET "Data(0)" LOC = "A18"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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93 | 94 | |
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95 | NET "GPMC_AD(0)" LOC = "M1"| slew=FAST | IOSTANDARD=LVTTL; | |
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96 | NET "GPMC_AD(1)" LOC = "M2"| slew=FAST | IOSTANDARD=LVTTL; | |
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97 | NET "GPMC_AD(2)" LOC = "AB3"| slew=FAST | IOSTANDARD=LVTTL; | |
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98 | NET "GPMC_AD(3)" LOC = "AB2"| slew=FAST | IOSTANDARD=LVTTL; | |
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99 | NET "GPMC_AD(4)" LOC = "N1"| slew=FAST | IOSTANDARD=LVTTL; | |
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100 | NET "GPMC_AD(5)" LOC = "N3"| slew=FAST | IOSTANDARD=LVTTL; | |
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101 | NET "GPMC_AD(6)" LOC = "AB5"| slew=FAST | IOSTANDARD=LVTTL; | |
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102 | NET "GPMC_AD(7)" LOC = "AB4"| slew=FAST | IOSTANDARD=LVTTL; | |
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103 | NET "GPMC_AD(8)" LOC = "R1"| slew=FAST | IOSTANDARD=LVTTL; | |
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104 | NET "GPMC_AD(9)" LOC = "V1"| slew=FAST | IOSTANDARD=LVTTL; | |
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105 | NET "GPMC_AD(10)" LOC = "U3"| slew=FAST | IOSTANDARD=LVTTL; | |
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106 | NET "GPMC_AD(11)" LOC = "T1"| slew=FAST | IOSTANDARD=LVTTL; | |
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107 | NET "GPMC_AD(12)" LOC = "V2"| slew=FAST | IOSTANDARD=LVTTL; | |
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108 | NET "GPMC_AD(13)" LOC = "W1"| slew=FAST | IOSTANDARD=LVTTL; | |
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109 | NET "GPMC_AD(14)" LOC = "T2"| slew=FAST | IOSTANDARD=LVTTL; | |
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110 | NET "GPMC_AD(15)" LOC = "U1"| slew=FAST | IOSTANDARD=LVTTL; | |
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111 | ||
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112 | ||
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113 | ||
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114 | NET "GPMC_A(0)" LOC = "N4"| slew=FAST | IOSTANDARD=LVTTL; | |
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115 | NET "GPMC_A(1)" LOC = "N6"| slew=FAST | IOSTANDARD=LVTTL; | |
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116 | NET "GPMC_A(2)" LOC = "P3"| slew=FAST | IOSTANDARD=LVTTL; | |
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117 | NET "GPMC_A(3)" LOC = "P4"| slew=FAST | IOSTANDARD=LVTTL; | |
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118 | NET "GPMC_A(4)" LOC = "R4"| slew=FAST | IOSTANDARD=LVTTL; | |
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119 | NET "GPMC_A(5)" LOC = "T5"| slew=FAST | IOSTANDARD=LVTTL; | |
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120 | NET "GPMC_A(6)" LOC = "T6"| slew=FAST | IOSTANDARD=LVTTL; | |
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121 | NET "GPMC_A(7)" LOC = "T3"| slew=FAST | IOSTANDARD=LVTTL; | |
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122 | NET "GPMC_A(8)" LOC = "L1"| slew=FAST | IOSTANDARD=LVTTL; | |
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123 | NET "GPMC_A(9)" LOC = "K1"| slew=FAST | IOSTANDARD=LVTTL; | |
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124 | NET "GPMC_A(10)" LOC = "L3"| slew=FAST | IOSTANDARD=LVTTL; | |
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125 | NET "GPMC_A(11)" LOC = "K2"| slew=FAST | IOSTANDARD=LVTTL; | |
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126 | NET "GPMC_A(12)" LOC = "F1"| slew=FAST | IOSTANDARD=LVTTL; | |
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127 | NET "GPMC_A(13)" LOC = "F2"| slew=FAST | IOSTANDARD=LVTTL; | |
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128 | NET "GPMC_A(14)" LOC = "G3"| slew=FAST | IOSTANDARD=LVTTL; | |
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129 | NET "GPMC_A(15)" LOC = "H2"| slew=FAST | IOSTANDARD=LVTTL; | |
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130 | NET "GPMC_A(16)" LOC = "G1"| slew=FAST | IOSTANDARD=LVTTL; | |
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131 | NET "GPMC_A(17)" LOC = "H1"| slew=FAST | IOSTANDARD=LVTTL; | |
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132 | NET "GPMC_A(18)" LOC = "J1"| slew=FAST | IOSTANDARD=LVTTL; | |
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133 | NET "GPMC_A(19)" LOC = "J3"| slew=FAST | IOSTANDARD=LVTTL; | |
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134 | ||
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135 | NET "GPMC_CLK_MUX0" CLOCK_DEDICATED_ROUTE = FALSE; | |
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136 | NET "GPMC_CLK_MUX0" LOC = "R3"| slew=FAST | IOSTANDARD=LVTTL; | |
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137 | NET "GPMC_WEN" LOC = "W3"| slew=FAST | IOSTANDARD=LVTTL; | |
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138 | NET "GPMC_OEN_REN" LOC = "Y2"| slew=FAST | IOSTANDARD=LVTTL; | |
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139 | NET "GPMC_ADVN_ALE" LOC = "AA2"| slew=FAST | IOSTANDARD=LVTTL; | |
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140 | NET "GPMC_CSN(0)" LOC = "M3"| slew=FAST | IOSTANDARD=LVTTL; | |
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141 | NET "GPMC_CSN(1)" LOC = "P1"| slew=FAST | IOSTANDARD=LVTTL; | |
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142 | NET "GPMC_CSN(2)" LOC = "P2"| slew=FAST | IOSTANDARD=LVTTL; | |
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143 | NET "GPMC_BE0N_CLE" LOC = "Y1"| slew=FAST | IOSTANDARD=LVTTL; | |
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144 | NET "GPMC_BE1N" LOC = "AB21"| slew=FAST | IOSTANDARD=LVTTL; | |
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145 | NET "GPMC_WAIT0" LOC = "AA21"| slew=FAST | IOSTANDARD=LVTTL; | |
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146 | NET "GPMC_WPN" LOC = "W22"| slew=FAST | IOSTANDARD=LVTTL; | |
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94 | 147 | |
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95 | 148 | |
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96 | 149 | |
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97 | 150 | |
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98 | 151 | |
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99 | 152 | |
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100 | 153 | |
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101 | 154 | |
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102 | 155 | |
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103 | 156 | |
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104 | 157 | |
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105 | 158 | |
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106 | 159 | |
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107 | 160 | |
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108 | 161 | |
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109 | 162 | |
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163 | ||
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164 | ||
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165 | ||
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166 | ||
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167 | ||
| @@ -1,330 +1,364 | |||
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1 | 1 | library ieee; |
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2 | 2 | use ieee.std_logic_1164.all; |
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3 | 3 | use IEEE.numeric_std.all; |
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4 | 4 | library grlib, techmap; |
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5 | 5 | use grlib.amba.all; |
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6 | 6 | use grlib.amba.all; |
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7 | 7 | use grlib.stdlib.all; |
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8 | 8 | use techmap.gencomp.all; |
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9 | 9 | use techmap.allclkgen.all; |
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10 | 10 | library gaisler; |
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11 | 11 | use gaisler.memctrl.all; |
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12 | 12 | use gaisler.leon3.all; |
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13 | 13 | use gaisler.uart.all; |
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14 | 14 | use gaisler.misc.all; |
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15 | 15 | library esa; |
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16 | 16 | use esa.memoryctrl.all; |
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17 | 17 | --use gaisler.sim.all; |
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18 | 18 | library lpp; |
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19 | 19 | use lpp.lpp_ad_conv.all; |
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20 | 20 | use lpp.lpp_amba.all; |
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21 | 21 | use lpp.apb_devices_list.all; |
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22 | 22 | use lpp.general_purpose.all; |
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23 | 23 | use lpp.lpp_cna.all; |
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24 | 24 | |
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25 | Library UNISIM; | |
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25 | Library UNISIM; | |
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26 | 26 | use UNISIM.vcomponents.all; |
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27 | 27 | |
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28 | 28 | |
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29 | 29 | use work.config.all; |
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30 | 30 | --================================================================== |
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31 | 31 | -- |
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32 | 32 | -- |
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33 | 33 | -- FPGA FREQ = 100MHz |
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34 | 34 | -- |
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35 | 35 | -- |
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36 | 36 | --================================================================== |
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37 | 37 | |
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38 | 38 | entity BeagleSynth is |
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39 | 39 | generic ( |
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40 | 40 | fabtech : integer := CFG_FABTECH; |
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41 | 41 | memtech : integer := CFG_MEMTECH; |
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42 | 42 | padtech : integer := CFG_PADTECH; |
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43 | 43 | clktech : integer := CFG_CLKTECH |
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44 | 44 | ); |
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45 | 45 | port ( |
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46 | reset : in std_ulogic; | |
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47 | clk : in std_ulogic; | |
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48 |
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49 |
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50 |
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51 |
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52 |
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53 |
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54 |
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55 |
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56 |
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46 | reset : in std_ulogic; | |
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47 | clk : in std_ulogic; | |
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48 | DAC_nCLR : out std_ulogic; | |
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49 | DAC_nCS : out std_ulogic; | |
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50 | CAL_IN_SCK : out std_ulogic; | |
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51 | DAC_SDI : out std_logic_vector(7 downto 0); | |
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52 | TXD : out std_ulogic; | |
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53 | RXD : in std_ulogic; | |
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54 | urxd1 : in std_ulogic; | |
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55 | utxd1 : out std_ulogic; | |
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56 | LED : out std_ulogic_vector(2 downto 0); | |
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57 | -------------------------------------------------------- | |
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58 | ---- Beaglebone GPMC | |
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59 | -------------------------------------------------------- | |
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60 | GPMC_AD : inout std_logic_vector(15 downto 0); | |
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61 | GPMC_A : in std_logic_vector(19 downto 0); | |
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62 | GPMC_CLK_MUX0 : in std_ulogic; | |
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63 | GPMC_WEN : in std_ulogic; | |
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64 | GPMC_OEN_REN : in std_ulogic; | |
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65 | GPMC_ADVN_ALE : in std_ulogic; | |
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66 | GPMC_CSN : in std_ulogic_vector(2 downto 0); | |
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67 | GPMC_BE0N_CLE : in std_ulogic; | |
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68 | GPMC_BE1N : in std_ulogic; | |
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69 | GPMC_WAIT0 : in std_ulogic; | |
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70 | GPMC_WPN : in std_ulogic; | |
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71 | ||
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57 | 72 | -------------------------------------------------------- |
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58 | 73 | ---- SDRAM |
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59 | 74 | ---- For SDRAM config have a look on leon3-altera-ep1c20 |
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60 | 75 | ---- design from GRLIB, the IS42S32400E is similar to |
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61 | 76 | ---- MT48LC4M32B2. |
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62 | 77 | -------------------------------------------------------- |
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63 | 78 | sdcke : out std_logic; -- clk en |
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64 | 79 | sdcsn : out std_logic; -- chip sel |
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65 | 80 | sdwen : out std_logic; -- write en |
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66 | 81 | sdrasn : out std_logic; -- row addr stb |
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67 | 82 | sdcasn : out std_logic; -- col addr stb |
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68 | 83 | sddqm : out std_logic_vector (3 downto 0); -- data i/o mask |
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69 | 84 | sdclk : out std_logic; -- sdram clk output |
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70 | 85 | sdba : out std_logic_vector (1 downto 0); -- bank select address |
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71 | 86 | Address : out std_logic_vector(11 downto 0); -- sdram address |
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72 | 87 | Data : inout std_logic_vector(31 downto 0) -- optional sdram data |
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73 | 88 | ); |
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74 | 89 | end; |
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75 | 90 | |
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76 | 91 | architecture rtl of BeagleSynth is |
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77 | 92 | constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ |
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78 | 93 | CFG_GRETH+CFG_AHB_JTAG; |
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79 | 94 | constant maxahbm : integer := maxahbmsp; |
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80 | 95 | constant IOAEN : integer := CFG_CAN; |
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81 | 96 | constant boardfreq : integer := 100000; |
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82 | 97 | |
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83 | 98 | signal clk2x : std_ulogic; |
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84 | 99 | signal lclk : std_ulogic; |
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85 | 100 | signal clkm : std_ulogic; |
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86 | 101 | signal rstn : std_ulogic; |
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87 | 102 | signal rst : std_ulogic; |
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88 | 103 | signal rstraw : std_ulogic; |
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89 | 104 | signal pciclk : std_ulogic; |
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90 | 105 | signal sdclkl : std_ulogic; |
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91 | 106 | signal sdclkl_DDR2 : std_ulogic; |
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92 | 107 | signal cgi : clkgen_in_type; |
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93 | 108 | signal cgo : clkgen_out_type; |
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94 | 109 | |
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95 | 110 | --- AHB / APB |
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96 | 111 | signal apbi : apb_slv_in_type; |
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97 | 112 | signal apbo : apb_slv_out_vector := (others => apb_none); |
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98 | 113 | signal ahbsi : ahb_slv_in_type; |
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99 | 114 | signal ahbso : ahb_slv_out_vector := (others => ahbs_none); |
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100 | 115 | signal ahbmi : ahb_mst_in_type; |
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101 | 116 | signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); |
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102 | 117 | |
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103 | 118 | --- MEM CTRLR |
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104 | 119 | signal sdi : sdctrl_in_type; |
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105 | 120 | signal sdo : sdctrl_out_type; |
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106 | 121 | |
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107 | 122 | --UART |
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108 | 123 | signal ahbuarti : uart_in_type; |
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109 | 124 | signal ahbuarto : uart_out_type; |
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110 | 125 | signal apbuarti : uart_in_type; |
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111 | 126 | signal apbuarto : uart_out_type; |
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112 | 127 | |
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113 | 128 | signal led2int : std_logic; |
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114 | 129 | |
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115 | 130 | |
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116 | 131 | signal DAC0_DATA : std_logic_vector(15 downto 0); |
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117 | 132 | signal DAC1_DATA : std_logic_vector(15 downto 0); |
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118 | 133 | signal DAC2_DATA : std_logic_vector(15 downto 0); |
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119 | 134 | signal DAC3_DATA : std_logic_vector(15 downto 0); |
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120 | 135 | signal DAC4_DATA : std_logic_vector(15 downto 0); |
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121 | 136 | signal DAC5_DATA : std_logic_vector(15 downto 0); |
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122 | 137 | signal DAC6_DATA : std_logic_vector(15 downto 0); |
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123 | 138 | signal DAC7_DATA : std_logic_vector(15 downto 0); |
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124 | 139 | |
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125 | 140 | signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0); |
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126 | 141 | signal smpclk : std_logic; |
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127 | 142 | signal smpclk_reg : std_logic; |
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128 | 143 | signal DAC_SDO : std_logic; |
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129 | 144 | |
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145 | signal gpmc_clk : std_logic; | |
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130 | 146 | begin |
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131 | 147 | |
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132 | 148 | DAC_nCLR <= '1'; |
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133 | 149 | --DAC_nCS <= SYNC; |
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134 | 150 | --CAL_IN_SCK <= '1'; |
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135 | 151 | --DAC_SDI <= (others =>'1'); |
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136 | 152 | |
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137 | 153 | resetn_pad : inpad generic map (tech => padtech) port map (reset, rst); |
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138 | 154 | rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw); |
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139 | 155 | --rstn <= reset; |
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140 | 156 | --lclk <= clk; |
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141 | 157 | clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk); |
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142 | 158 | |
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143 | 159 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; |
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144 | 160 | clkgen0 : clkgen -- clock generator |
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145 | 161 | generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq) |
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146 | 162 | port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open); |
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147 | 163 | |
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148 | 164 | -- sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2); |
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149 | 165 | --sdclk <= sdclkl; |
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150 | 166 | sdclk <= sdclkl_DDR2; |
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151 | 167 | |
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152 | 168 | LED(1) <= not cgo.clklock; |
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153 | 169 | LED(0) <= cgo.clklock; |
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154 | 170 | |
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155 | 171 | ODDR2_inst : ODDR2 |
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156 | 172 | generic map( |
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157 | 173 | DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" |
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158 | 174 | INIT => '0', -- Sets initial state of the Q output to '0' or '1' |
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159 | 175 | SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset |
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160 | 176 | port map ( |
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161 | 177 | Q => sdclkl_DDR2, -- 1-bit output data |
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162 | 178 | C0 => sdclkl, -- 1-bit clock input |
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163 | 179 | C1 => not sdclkl, -- 1-bit clock input |
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164 | 180 | CE => '1', -- 1-bit clock enable input |
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165 | 181 | D0 => '1', -- 1-bit data input (associated with C0) |
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166 | 182 | D1 => '0', -- 1-bit data input (associated with C1) |
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167 | 183 | R => '0', -- 1-bit reset input |
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168 | 184 | S => '0' -- 1-bit set input |
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169 | 185 | ); |
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170 | 186 | |
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171 | 187 | ---------------------------------------------------------------------- |
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172 | 188 | --- AHB CONTROLLER ------------------------------------------------- |
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173 | 189 | ---------------------------------------------------------------------- |
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174 | 190 | |
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175 | 191 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
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176 | 192 | generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, |
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177 | 193 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, |
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178 | 194 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) |
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179 | 195 | port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); |
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180 | 196 | |
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181 | 197 | ---------------------------------------------------------------------- |
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182 | 198 | --- AHB UART ------------------------------------------------------- |
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183 | 199 | ---------------------------------------------------------------------- |
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184 | 200 | |
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185 | 201 | dcomgen : if CFG_AHB_UART = 1 generate |
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186 | 202 | dcom0: ahbuart -- Debug UART |
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187 | 203 | generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) |
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188 | 204 | port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); |
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189 | 205 | ahbuarti.rxd <= RXD; |
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190 | 206 | TXD <= ahbuarto.txd; |
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191 | 207 | end generate; |
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192 | 208 | nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; |
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193 | 209 | |
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194 | 210 | ---------------------------------------------------------------------- |
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195 | 211 | --- APB Bridge ----------------------------------------------------- |
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196 | 212 | ---------------------------------------------------------------------- |
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197 | 213 | |
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198 | 214 | apb0 : apbctrl -- AHB/APB bridge |
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199 | 215 | generic map (hindex => 1, haddr => CFG_APBADDR) |
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200 | 216 | port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); |
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201 | 217 | |
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202 | 218 | ---------------------------------------------------------------------- |
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203 | 219 | --- APB UART ------------------------------------------------------- |
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204 | 220 | ---------------------------------------------------------------------- |
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205 | 221 | |
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206 | 222 | ua1 : if CFG_UART1_ENABLE /= 0 generate |
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207 | 223 | uart1 : apbuart -- UART 1 |
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208 | 224 | generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART, |
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209 | 225 | fifosize => CFG_UART1_FIFO) |
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210 | 226 | port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); |
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211 | 227 | apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; |
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212 | 228 | apbuarti.ctsn <= '0'; |
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213 | 229 | end generate; |
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214 | 230 | noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; |
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215 | 231 | |
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216 | 232 | |
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217 | 233 | |
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218 | 234 | |
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219 | 235 | --div0: Clk_divider |
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220 | 236 | -- generic map( 100000000,1) |
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221 | 237 | -- Port map( clkm,rstn,LED(2)); |
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222 | 238 | |
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223 | 239 | LED(2) <= led2int; |
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224 | 240 | |
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225 | 241 | process(clkm,rstn) |
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226 | 242 | begin |
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227 | 243 | if rstn = '0' then |
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228 | 244 | led2int <= '0'; |
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229 | 245 | elsif clkm'event and clkm='1' then |
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230 | 246 | led2int <= not led2int; |
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231 | 247 | end if; |
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232 | 248 | end process; |
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233 | 249 | |
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234 | 250 | |
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235 | 251 | |
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236 | 252 | |
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237 | 253 | sdc : sdctrl |
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238 | 254 | generic map (hindex => 0, haddr => 16#600#, hmask => 16#F00#,ioaddr => 1, pwron => 0, |
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239 | 255 | invclk => 0,sdbits =>32) |
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240 | 256 | port map (rstn, clkm, ahbsi, ahbso(0), sdi, sdo); |
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241 | 257 | |
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242 | 258 | |
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243 | 259 | |
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244 | 260 | --Alternative data pad instantiation with vectored bdrive |
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245 | 261 | sd_pad : iopadvv generic map (tech=> padtech,width => 32) |
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246 | 262 | port map ( |
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247 | 263 | data(31 downto 0), |
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248 | 264 | sdo.data(31 downto 0), |
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249 | 265 | sdo.vbdrive(31 downto 0), |
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250 | 266 | sdi.data(31 downto 0)); |
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251 | 267 | |
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252 | 268 | |
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253 | 269 | -- connect memory controller outputs to entity output signals |
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254 | 270 | Address <= sdo.address(13 downto 2); |
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255 | 271 | --sdba <= sdo.address(16 downto 15); |
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256 | 272 | sdba <= "00"; |
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257 | 273 | sdcke <= sdo.sdcke(0); |
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258 | 274 | sdwen <= sdo.sdwen; |
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259 | 275 | sdcsn <= sdo.sdcsn(0); |
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260 | 276 | sdrasn <= sdo.rasn; |
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261 | 277 | sdcasn <= sdo.casn; |
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262 | 278 | sddqm <= sdo.dqm(3 downto 0); |
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263 | 279 | |
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264 | 280 | |
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265 | 281 | DAC0 : DAC8581 |
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266 | 282 | generic map(100,8) |
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267 | 283 | Port map( |
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268 | 284 | clk => clkm, |
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269 | 285 | rstn => rstn, |
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270 | 286 | smpclk => smpclk, |
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271 | 287 | sclk => CAL_IN_SCK, |
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272 | 288 | csn => DAC_nCS, |
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273 | 289 | sdo => DAC_SDI, |
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274 | 290 | smp_in => DAC_DATA |
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275 | 291 | ); |
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276 | 292 | |
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277 | 293 | |
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278 | 294 | |
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279 | 295 | smpclk0: Clk_divider |
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280 | 296 | GENERIC map(OSC_freqHz => 50000000, |
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281 | 297 | TargetFreq_Hz => 256000) |
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282 | 298 | PORT map( clk => clkm, |
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283 | 299 | reset => rstn, |
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284 | 300 | clk_divided => smpclk |
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285 | 301 | ); |
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286 | 302 | |
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287 | 303 | all_bits: FOR I in 15 downto 0 GENERATE |
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288 | 304 | DAC_DATA(0,I) <= DAC0_DATA(I); |
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289 | 305 | DAC_DATA(1,I) <= DAC1_DATA(I); |
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290 | 306 | DAC_DATA(2,I) <= DAC2_DATA(I); |
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291 | 307 | DAC_DATA(3,I) <= DAC3_DATA(I); |
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292 | 308 | DAC_DATA(4,I) <= DAC4_DATA(I); |
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293 | 309 | DAC_DATA(5,I) <= DAC5_DATA(I); |
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294 | 310 | DAC_DATA(6,I) <= DAC6_DATA(I); |
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295 | 311 | DAC_DATA(7,I) <= DAC7_DATA(I); |
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296 | 312 | end GENERATE; |
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297 | 313 | |
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298 | 314 | process(clkm,rstn) |
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299 | 315 | begin |
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300 | 316 | if rstn ='0' then |
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301 | 317 | DAC0_DATA <= X"0000"; |
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302 | 318 | DAC1_DATA <= X"0000"; |
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303 | 319 | DAC2_DATA <= X"0000"; |
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304 | 320 | DAC3_DATA <= X"0000"; |
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305 | 321 | DAC4_DATA <= X"0000"; |
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306 | 322 | DAC5_DATA <= X"0000"; |
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307 | 323 | DAC6_DATA <= X"0000"; |
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308 | 324 | DAC7_DATA <= X"0000"; |
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309 | 325 | smpclk_reg <= smpclk; |
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310 | 326 | elsif clkm'event and clkm = '1' then |
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311 | 327 | smpclk_reg <= smpclk; |
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312 | 328 | if smpclk_reg = '0' and smpclk = '1' then |
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313 | 329 | DAC0_DATA <= std_logic_vector( UNSIGNED(DAC0_DATA) +1); |
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314 | 330 | DAC1_DATA <= std_logic_vector( UNSIGNED(DAC1_DATA) +2); |
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315 | 331 | DAC2_DATA <= std_logic_vector( UNSIGNED(DAC2_DATA) +3); |
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316 | 332 | DAC3_DATA <= std_logic_vector( UNSIGNED(DAC3_DATA) +4); |
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317 | 333 | DAC4_DATA <= std_logic_vector( UNSIGNED(DAC4_DATA) +5); |
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318 | 334 | DAC5_DATA <= std_logic_vector( UNSIGNED(DAC5_DATA) +6); |
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319 | 335 | DAC6_DATA <= std_logic_vector( UNSIGNED(DAC6_DATA) +7); |
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320 | 336 | DAC7_DATA <= std_logic_vector( UNSIGNED(DAC7_DATA) +8); |
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321 | 337 | -- DAC_DATA <= "0100000000000000"; |
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322 | 338 | end if; |
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323 | 339 | end if; |
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324 | 340 | end process; |
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325 | 341 | |
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342 | gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk); | |
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343 | GPMCS0: entity work.GPMC_SLAVE | |
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344 | generic map(memtech,padtech) | |
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345 | Port map( | |
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346 | clk => clkm, | |
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347 | reset => rstn, | |
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348 | GPMC_AD => GPMC_AD, | |
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349 | GPMC_A => GPMC_A, | |
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350 | GPMC_CLK_MUX0 => gpmc_clk, | |
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351 | GPMC_WEN => GPMC_WEN, | |
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352 | GPMC_OEN_REN => GPMC_OEN_REN, | |
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353 | GPMC_ADVN_ALE => GPMC_ADVN_ALE, | |
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354 | GPMC_CSN => GPMC_CSN, | |
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355 | GPMC_BE0N_CLE => GPMC_BE0N_CLE, | |
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356 | GPMC_BE1N => GPMC_BE1N, | |
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357 | GPMC_WAIT0 => GPMC_WAIT0, | |
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358 | GPMC_WPN => GPMC_WAIT0 | |
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359 | ); | |
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326 | 360 | |
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327 | 361 | end rtl; |
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328 | 362 | |
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329 | 363 | |
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330 | 364 | |
| @@ -1,49 +1,49 | |||
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1 | 1 | include .config |
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2 | 2 | |
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3 | 3 | #GRLIB=$(GRLIB) |
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4 | 4 | TOP=BeagleSynth |
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5 | 5 | BOARD=BeagleSynth |
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6 | 6 | #BOARD=SP601 |
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7 | 7 | include ../../boards/$(BOARD)/Makefile.inc |
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8 | 8 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) |
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9 | 9 | #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf |
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10 | 10 | UCF=../../boards/$(BOARD)/default.ucf |
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11 | 11 | QSF=../../boards/$(BOARD)/$(TOP).qsf |
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12 | 12 | EFFORT=high |
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13 | 13 | ISEMAPOPT="-timing" |
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14 | 14 | XSTOPT="" |
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15 | 15 | SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0" |
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16 | 16 | VHDLOPTSYNFILES= |
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17 | 17 | |
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18 | 18 | |
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19 | 19 | VHDLSYNFILES= \ |
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20 | config.vhd BeagleSynth.vhd BeagleSynth_MCTRL.vhd | |
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20 | config.vhd BeagleSynth.vhd BeagleSynth_MCTRL.vhd GPMC_SLAVE.vhd | |
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21 | 21 | #VHDLSIMFILES=testbench.vhd |
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22 | 22 | #SIMTOP=testbench |
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23 | 23 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc |
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24 | 24 | SDCFILE=default.sdc |
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25 | 25 | BITGEN=../../boards/$(BOARD)/default.ut |
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26 | 26 | CLEAN=soft-clean |
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27 | 27 | VCOMOPT=-explicit |
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28 | 28 | TECHLIBS = secureip unisim |
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29 | 29 | |
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30 | 30 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ |
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31 | 31 | tmtc openchip cypress ihp gleichmann gsi fmf spansion |
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32 | 32 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \ |
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33 | 33 | leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \ |
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34 | 34 | ac97 hcan usb |
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35 | 35 | DIRADD = |
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36 | 36 | FILEADD = |
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37 | 37 | FILESKIP = grcan.vhd ddr2.v mobile_ddr.v |
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38 | 38 | |
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39 | 39 | include $(GRLIB)/bin/Makefile |
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40 | 40 | include $(GRLIB)/software/leon3/Makefile |
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41 | 41 | |
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42 | 42 | |
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43 | 43 | ################## project specific targets ########################## |
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44 | 44 | |
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45 | 45 | flash: |
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46 | 46 | xc3sprog -c ftdi -p 1 BeagleSynth.bit |
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47 | 47 | |
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48 | 48 | ram: |
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49 | 49 | xc3sprog -c ftdi -p 0 BeagleSynth.bit |
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1 | NO CONTENT: file was removed |
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