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update APB_REG
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r373:8b7232d194b4 JC
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@@ -1,436 +1,439
1 1 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3
4 4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 5 TOP=TB
6 6
7 7 CMD_VLIB=vlib
8 8 CMD_VMAP=vmap
9 9 CMD_VCOM=@vcom -quiet -93 -work
10 10
11 11 ################## project specific targets ##########################
12 12
13 13 all:
14 14 @echo "make vsim"
15 15 @echo "make libs"
16 16 @echo "make clean"
17 17 @echo "make vcom_grlib vcom_lpp vcom_tb"
18 18
19 19 run:
20 20 @vsim work.TB -do run.do
21 21 # @vsim work.TB
22 22 # @vsim lpp.lpp_lfr_ms
23 23
24 24 vsim: libs vcom run
25 25
26 26 libs:
27 27 @$(CMD_VLIB) modelsim
28 28 @$(CMD_VMAP) modelsim modelsim
29 29 @$(CMD_VLIB) modelsim/techmap
30 30 @$(CMD_VMAP) techmap modelsim/techmap
31 31 @$(CMD_VLIB) modelsim/grlib
32 32 @$(CMD_VMAP) grlib modelsim/grlib
33 33 @$(CMD_VLIB) modelsim/gaisler
34 34 @$(CMD_VMAP) gaisler modelsim/gaisler
35 35 @$(CMD_VLIB) modelsim/work
36 36 @$(CMD_VMAP) work modelsim/work
37 37 @$(CMD_VLIB) modelsim/lpp
38 38 @$(CMD_VMAP) lpp modelsim/lpp
39 39 @echo "libs done"
40 40
41 41
42 42 clean:
43 43 @rm -Rf modelsim
44 44 @rm -Rf modelsim.ini
45 45 @rm -Rf *~
46 46 @rm -Rf transcript
47 47 @rm -Rf wlft*
48 48 @rm -Rf *.wlf
49 49 @rm -Rf vish_stacktrace.vstf
50 50 @rm -Rf libs.do
51 51
52 52 vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb
53 53
54 54
55 55 vcom_tb:
56 56 ## $(CMD_VCOM) lpp lpp_memory.vhd
57 57 ## $(CMD_VCOM) lpp lppFIFOxN.vhd
58 58 ## $(CMD_VCOM) lpp lpp_FIFO.vhd
59 59 ## $(CMD_VCOM) lpp lpp_lfr_ms.vhd
60 60 $(CMD_VCOM) work TB.vhd
61 61 @echo "vcom done"
62 62
63 63 vcom_grlib:
64 64 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd
65 65 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd
66 66 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd
67 67 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd
68 68 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd
69 69 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd
70 70 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd
71 71 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd
72 72 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd
73 73 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd
74 74 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd
75 75 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd
76 76 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd
77 77 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd
78 78 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd
79 79 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd
80 80 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd
81 81 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd
82 82 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd
83 83 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd
84 84 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd
85 85 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd
86 86 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd
87 87 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd
88 88 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd
89 89 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd
90 90 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd
91 91 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd
92 92 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd
93 93 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd
94 94 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd
95 95 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd
96 96 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd
97 97 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd
98 98 @echo "vcom grlib done"
99 99
100 100 vcom_gaisler:
101 101 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd
102 102 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd
103 103 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd
104 104 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd
105 105 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd
106 106 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd
107 107 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd
108 108 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd
109 109 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd
110 110 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd
111 111 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd
112 112 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd
113 113 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd
114 114 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd
115 115 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd
116 116 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd
117 117 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd
118 118 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd
119 119 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd
120 120 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd
121 121 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd
122 122 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd
123 123 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd
124 124 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd
125 125 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd
126 126 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd
127 127 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd
128 128 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd
129 129 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd
130 130 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd
131 131 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd
132 132 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd
133 133 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd
134 134 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd
135 135 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd
136 136 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd
137 137 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd
138 138 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd
139 139 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd
140 140 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd
141 141 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd
142 142 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd
143 143 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd
144 144 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd
145 145 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd
146 146 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd
147 147 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd
148 148 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd
149 149 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd
150 150 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd
151 151 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd
152 152 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd
153 153 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd
154 154 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd
155 155 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd
156 156 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd
157 157 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd
158 158 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd
159 159 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd
160 160 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd
161 161 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd
162 162 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd
163 163 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd
164 164 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd
165 165 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd
166 166 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd
167 167 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd
168 168 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd
169 169 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd
170 170 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd
171 171 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd
172 172 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd
173 173 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd
174 174 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd
175 175 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd
176 176 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd
177 177 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd
178 178 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd
179 179 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd
180 180 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd
181 181 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd
182 182 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd
183 183 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd
184 184 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd
185 185 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd
186 186 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd
187 187 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd
188 188 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd
189 189 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd
190 190 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd
191 191 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd
192 192 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd
193 193 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd
194 194 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd
195 195 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd
196 196 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd
197 197 ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd
198 198 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd
199 199 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd
200 200 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd
201 201 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd
202 202 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd
203 203 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd
204 204 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd
205 205 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd
206 206 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd
207 207 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd
208 208 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd
209 209 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd
210 210 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd
211 211 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd
212 212 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd
213 213 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd
214 214 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd
215 215 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd
216 216 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd
217 217 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd
218 218 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd
219 219 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd
220 220 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd
221 221 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd
222 222 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd
223 223 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd
224 224 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd
225 225 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd
226 226 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd
227 227 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd
228 228 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd
229 229 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd
230 230 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd
231 231 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd
232 232 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd
233 233 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd
234 234 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd
235 235 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd
236 236 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd
237 237 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd
238 238 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd
239 239 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd
240 240 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd
241 241 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd
242 242 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd
243 243 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd
244 244 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd
245 245 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd
246 246 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd
247 247 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd
248 248 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd
249 249 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd
250 250 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd
251 251 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd
252 252 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd
253 253 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd
254 254 @echo "vcom gaisler done"
255 255
256 256 vcom_techmap:
257 257 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd
258 258 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd
259 259 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd
260 260 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd
261 261 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd
262 262 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd
263 263 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd
264 264 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd
265 265 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd
266 266 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd
267 267 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd
268 268 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd
269 269 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd
270 270 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd
271 271 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd
272 272 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd
273 273 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd
274 274 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd
275 275 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd
276 276 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd
277 277 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd
278 278 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd
279 279 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd
280 280 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd
281 281 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd
282 282 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd
283 283 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd
284 284 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd
285 285 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd
286 286 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd
287 287 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd
288 288 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd
289 289 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd
290 290 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd
291 291 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd
292 292 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd
293 293 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd
294 294 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd
295 295 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd
296 296 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd
297 297 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd
298 298 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd
299 299 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd
300 300 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd
301 301 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd
302 302 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd
303 303 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd
304 304 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd
305 305 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd
306 306 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd
307 307 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd
308 308 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd
309 309 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd
310 310 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd
311 311 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd
312 312 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd
313 313 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd
314 314 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd
315 315 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd
316 316 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd
317 317 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd
318 318 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd
319 319 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd
320 320 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd
321 321 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd
322 322 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd
323 323 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd
324 324 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd
325 325 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd
326 326 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd
327 327 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd
328 328 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd
329 329 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd
330 330 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd
331 331 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd
332 332 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd
333 333 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd
334 334 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd
335 335 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd
336 336 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd
337 337 @echo "vcom techmap done"
338 338
339 339 vcom_lpp:
340 340 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd
341 341 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd
342 342 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
343 343 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd
344 344 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
345 345 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
346 346 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
347 347 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
348 348 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
349 349 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
350 350 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
351 351 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
352 352 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
353 353 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
354 354 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
355 355 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
356 356 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
357 357 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
358 358 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
359 359 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
360 360 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
361 361 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
362 362 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
363 363 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
364 364 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
365 365 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
366 366 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
367 367 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
368 368 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
369 369 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
370 370 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
371 371 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
372 372 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
373 373 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
374 374 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd
375 375 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd
376 376 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
377 377 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd
378 378 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd
379 379 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd
380 380 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd
381 381 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd
382 382 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
383 383 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd
384 384 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd
385 385 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd
386 386 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd
387 387 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd
388 388 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_memory.vhd
389 389 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lppFIFOxN.vhd
390 390 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO.vhd
391 391 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd
392 392 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd
393 393 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd
394 394 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd
395 395 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd
396 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd
397 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
396 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd
397 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
398 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
399 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd
400 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd
398 401 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
399 402 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
400 403 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd
401 404 @echo "vcom lpp done"
402 405
403 406 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
404 407 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
405 408 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
406 409 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
407 410 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
408 411 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
409 412 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
410 413 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
411 414 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
412 415 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
413 416 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
414 417 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
415 418 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
416 419 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
417 420 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
418 421 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
419 422 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
420 423 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
421 424 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
422 425 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
423 426 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
424 427 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
425 428 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
426 429 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
427 430 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
428 431 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
429 432 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd
430 433 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd
431 434 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd
432 435 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd
433 436 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd
434 437 # @echo "vcom lpp done"
435 438
436 439 #include Makefile_vcom_lpp
Show file before | Show file after | Hide comments
@@ -1,321 +1,422
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE IEEE.NUMERIC_STD.ALL;
26 26
27 27 LIBRARY lpp;
28 28 USE lpp.lpp_lfr_pkg.ALL;
29 29 USE lpp.lpp_memory.ALL;
30 30 USE lpp.iir_filter.ALL;
31 31 USE lpp.spectral_matrix_package.ALL;
32 32 use lpp.lpp_fft.all;
33 33 use lpp.fft_components.all;
34 34
35 LIBRARY grlib;
36 USE grlib.amba.ALL;
37 USE grlib.stdlib.ALL;
38 USE grlib.devices.ALL;
39 USE GRLIB.DMA2AHB_Package.ALL;
40
35 41 ENTITY TB IS
36 42
37 43
38 44 END TB;
39 45
40 46
41 47 ARCHITECTURE beh OF TB IS
42 48
43 49 -----------------------------------------------------------------------------
44 50 SIGNAL clk25MHz : STD_LOGIC := '0';
45 51 SIGNAL rstn : STD_LOGIC := '0';
46 52
47 53 -----------------------------------------------------------------------------
48 54 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
49 55 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
50 56 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
51 57 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
52 58 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
53 59 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
54 60 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
55 61 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
56 62 SIGNAL dma_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
57 63 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
58 64 SIGNAL dma_valid : STD_LOGIC;
59 65 SIGNAL dma_valid_burst : STD_LOGIC;
60 66 SIGNAL dma_ren : STD_LOGIC;
61 67 SIGNAL dma_done : STD_LOGIC;
62 68 SIGNAL ready_matrix_f0 : STD_LOGIC;
63 69 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
64 70 SIGNAL ready_matrix_f1 : STD_LOGIC;
65 71 SIGNAL ready_matrix_f2 : STD_LOGIC;
66 72 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
67 73 SIGNAL error_bad_component_error : STD_LOGIC;
68 74 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
69 75 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
70 76 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
71 77 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
72 78 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
73 79 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
74 80 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
75 81 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
76 82 SIGNAL config_active_interruption_onError : STD_LOGIC;
77 83 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 84 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
79 85 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
80 86 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
81 87 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
82 88 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
83 89 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
84 90 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
85 91
86 92 -----------------------------------------------------------------------------
87 93 SIGNAL clk49_152MHz : STD_LOGIC := '0';
88 94 SIGNAL sample_counter_24k : INTEGER;
89 95 SIGNAL s_24576Hz : STD_LOGIC;
90 96
91 97 SIGNAL s_24_sync_reg_0 : STD_LOGIC;
92 98 SIGNAL s_24_sync_reg_1 : STD_LOGIC;
93 99
94 100 SIGNAL s_24576Hz_sync : STD_LOGIC;
95 101
96 102 SIGNAL sample_counter_f1 : INTEGER;
97 103 SIGNAL sample_counter_f2 : INTEGER;
98 104 --
99 105 SIGNAL sample_f0_val : STD_LOGIC;
100 106 SIGNAL sample_f1_val : STD_LOGIC;
101 107 SIGNAL sample_f2_val : STD_LOGIC;
102 108
103 109 -----------------------------------------------------------------------------
104 110 SIGNAL ren_counter : INTEGER;
105 111
112 SIGNAL error_buffer_full : STD_LOGIC;
113 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
114 -----------------------------------------------------------------------------
115 SIGNAL apbi : apb_slv_in_type;
116 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
120
106 121 BEGIN -- beh
107 122
108 123 clk25MHz <= NOT clk25MHz AFTER 20 ns;
109 124 clk25MHz <= NOT clk25MHz AFTER 20 ns;
110 125 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
111 126
112 127 PROCESS
113 128 BEGIN -- PROCESS
114 129 WAIT UNTIL clk25MHz = '1';
115 130 WAIT UNTIL clk25MHz = '1';
116 131 WAIT UNTIL clk25MHz = '1';
117 132 rstn <= '1';
118 133 WAIT UNTIL clk25MHz = '1';
119 134
120 135
121 136 WAIT FOR 100 ms;
122 137
123 138 REPORT "*** END simulation ***" SEVERITY failure;
124 139 WAIT;
125 140
126 141 END PROCESS;
127 142
128 143
129 144 -----------------------------------------------------------------------------
130 145 PROCESS (clk49_152MHz, rstn)
131 146 BEGIN -- PROCESS
132 147 IF rstn = '0' THEN -- asynchronous reset (active low)
133 148 sample_counter_24k <= 0;
134 149 s_24576Hz <= '0';
135 150 ELSIF clk49_152MHz'event AND clk49_152MHz = '1' THEN -- rising clock edge
136 151 IF sample_counter_24k = 0 THEN
137 152 sample_counter_24k <= 2000;
138 153 s_24576Hz <= NOT s_24576Hz;
139 154 ELSE
140 155 sample_counter_24k <= sample_counter_24k - 1;
141 156 END IF;
142 157 END IF;
143 158 END PROCESS;
144 159
145 160 PROCESS (clk25MHz, rstn)
146 161 BEGIN -- PROCESS
147 162 IF rstn = '0' THEN -- asynchronous reset (active low)
148 163 s_24_sync_reg_0 <= '0';
149 164 s_24_sync_reg_1 <= '0';
150 165 s_24576Hz_sync <= '0';
151 166 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
152 167 s_24_sync_reg_0 <= s_24576Hz;
153 168 s_24_sync_reg_1 <= s_24_sync_reg_0;
154 169 s_24576Hz_sync <= s_24_sync_reg_0 XOR s_24_sync_reg_1;
155 170 END IF;
156 171 END PROCESS;
157 172
158 173 PROCESS (clk25MHz, rstn)
159 174 BEGIN -- PROCESS
160 175 IF rstn = '0' THEN -- asynchronous reset (active low)
161 176 sample_f0_val <= '0';
162 177 sample_f1_val <= '0';
163 178 sample_f2_val <= '0';
164 179
165 180 sample_counter_f1 <= 0;
166 181 sample_counter_f2 <= 0;
167 182 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
168 183 IF s_24576Hz_sync = '1' THEN
169 184 sample_f0_val <= '1';
170 185 IF sample_counter_f1 = 0 THEN
171 186 sample_f1_val <= '1';
172 187 sample_counter_f1 <= 5;
173 188 ELSE
174 189 sample_f1_val <= '0';
175 190 sample_counter_f1 <= sample_counter_f1 -1;
176 191 END IF;
177 192 IF sample_counter_f2 = 0 THEN
178 193 sample_f2_val <= '1';
179 194 sample_counter_f2 <= 95;
180 195 ELSE
181 196 sample_f2_val <= '0';
182 197 sample_counter_f2 <= sample_counter_f2 -1;
183 198 END IF;
184 199 ELSE
185 200 sample_f0_val <= '0';
186 201 sample_f1_val <= '0';
187 202 sample_f2_val <= '0';
188 203 END IF;
189 204 END IF;
190 205 END PROCESS;
191 206
192 207
193 208
194 209 -----------------------------------------------------------------------------
195 210 coarse_time <= (OTHERS => '0');
196 211 fine_time <= (OTHERS => '0');
197 212
198 213 sample_f0_wdata <= X"A000" & X"A111" & X"A222" & X"A333" & X"A444";
199 214 sample_f1_wdata <= X"B000" & X"B111" & X"B222" & X"B333" & X"B444";
200 215 sample_f2_wdata <= X"C000" & X"C111" & X"C222" & X"C333" & X"C444";
201 216
202 217 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val);
203 218 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val);
204 219 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val);
205 220 -----------------------------------------------------------------------------
206 221
207 222 lpp_lfr_ms_1: lpp_lfr_ms
208 223 GENERIC MAP (
209 224 Mem_use => use_CEL)
210 225 PORT MAP (
211 226 clk => clk25MHz,
212 227 rstn => rstn,
213 228 --
214 229 coarse_time => coarse_time,
215 230 fine_time => fine_time,
216 231 --
217 232 sample_f0_wen => sample_f0_wen,
218 233 sample_f0_wdata => sample_f0_wdata,
219 234 sample_f1_wen => sample_f1_wen,
220 235 sample_f1_wdata => sample_f1_wdata,
221 236 sample_f2_wen => sample_f2_wen,
222 237 sample_f2_wdata => sample_f2_wdata,
223 238 --
224 239 dma_addr => dma_addr,
225 240 dma_data => dma_data,
226 241 dma_valid => dma_valid,
227 242 dma_valid_burst => dma_valid_burst,
228 243 dma_ren => dma_ren,
229 244 dma_done => dma_done,
230 245
231 246 ready_matrix_f0 => ready_matrix_f0,
232 247 -- ready_matrix_f0_1 => ready_matrix_f0_1,
233 248 ready_matrix_f1 => ready_matrix_f1,
234 249 ready_matrix_f2 => ready_matrix_f2,
235 250 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
236 251 error_bad_component_error => error_bad_component_error,
237 error_buffer_full => OPEN,
238 error_input_fifo_write => OPEN,
252 error_buffer_full => error_buffer_full,
253 error_input_fifo_write => error_input_fifo_write,
239 254
240 255 debug_reg => debug_reg,
241 256 status_ready_matrix_f0 => status_ready_matrix_f0,
242 257 -- status_ready_matrix_f0 => status_ready_matrix_f0_1,
243 258 status_ready_matrix_f1 => status_ready_matrix_f1,
244 259 status_ready_matrix_f2 => status_ready_matrix_f2,
245 260 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
246 261 -- status_error_bad_component_error => status_error_bad_component_error,
247 262 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
248 263 config_active_interruption_onError => config_active_interruption_onError,
249 264 addr_matrix_f0 => addr_matrix_f0,
250 265 -- addr_matrix_f0_1 => addr_matrix_f0_1,
251 266 addr_matrix_f1 => addr_matrix_f1,
252 267 addr_matrix_f2 => addr_matrix_f2,
253 268 matrix_time_f0 => matrix_time_f0,
254 269 -- matrix_time_f0_1 => matrix_time_f0_1,
255 270 matrix_time_f1 => matrix_time_f1,
256 271 matrix_time_f2 => matrix_time_f2);
257 272
273
274
275
276 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
277 GENERIC MAP (
278 nb_data_by_buffer_size => 11,
279 nb_word_by_buffer_size => 11,
280 nb_snapshot_param_size => 11,
281 delta_vector_size => 20,
282 delta_vector_size_f0_2 => 7,
283 pindex => 4,
284 paddr => 4,
285 pmask => 16#fff#,
286 pirq_ms => 0,
287 pirq_wfp => 1,
288 top_lfr_version => (OTHERS => '0')
289 )
290 PORT MAP (
291 HCLK => clk25MHz,
292 HRESETn => rstn,
293 apbi => apbi,
294 apbo => OPEN,
295
296 run_ms => OPEN,
297
298 ready_matrix_f0 => ready_matrix_f0,
299 ready_matrix_f1 => ready_matrix_f1,
300 ready_matrix_f2 => ready_matrix_f2,
301 error_bad_component_error => error_bad_component_error,
302 error_buffer_full => error_buffer_full, -- TODO
303 error_input_fifo_write => error_input_fifo_write, -- TODO
304 status_ready_matrix_f0 => status_ready_matrix_f0,
305 status_ready_matrix_f1 => status_ready_matrix_f1,
306 status_ready_matrix_f2 => status_ready_matrix_f2,
307 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
308 config_active_interruption_onError => config_active_interruption_onError,
309
310 matrix_time_f0 => matrix_time_f0,
311 matrix_time_f1 => matrix_time_f1,
312 matrix_time_f2 => matrix_time_f2,
313
314 addr_matrix_f0 => addr_matrix_f0,
315 addr_matrix_f1 => addr_matrix_f1,
316 addr_matrix_f2 => addr_matrix_f2,
317 -------------------------------------------------------------------------
318 status_full => status_full,
319 status_full_ack => status_full_ack,
320 status_full_err => status_full_err,
321 status_new_err => status_new_err,
322 data_shaping_BW => OPEN,
323 data_shaping_SP0 => OPEN,
324 data_shaping_SP1 => OPEN,
325 data_shaping_R0 => OPEN,
326 data_shaping_R1 => OPEN,
327 delta_snapshot => OPEN,
328 delta_f0 => OPEN,
329 delta_f0_2 => OPEN,
330 delta_f1 => OPEN,
331 delta_f2 => OPEN,
332 nb_data_by_buffer => OPEN,
333 nb_word_by_buffer => OPEN,
334 nb_snapshot_param => OPEN,
335 enable_f0 => OPEN,
336 enable_f1 => OPEN,
337 enable_f2 => OPEN,
338 enable_f3 => OPEN,
339 burst_f0 => OPEN,
340 burst_f1 => OPEN,
341 burst_f2 => OPEN,
342 run => OPEN,
343 addr_data_f0 => OPEN,
344 addr_data_f1 => OPEN,
345 addr_data_f2 => OPEN,
346 addr_data_f3 => OPEN,
347 start_date => OPEN);
348
349
350
351
352
353
354
355
356
357
258 358
259 359
260 360
261 361
262 PROCESS (clk25MHz, rstn)
263 BEGIN -- PROCESS
264 IF rstn = '0' THEN -- asynchronous reset (active low)
265 status_ready_matrix_f0 <= '0';
266 -- status_ready_matrix_f0_1 <= '0';
267 status_ready_matrix_f1 <= '0';
268 status_ready_matrix_f2 <= '0';
269 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
270 status_ready_matrix_f0 <= status_ready_matrix_f0 OR ready_matrix_f0;
271 -- status_ready_matrix_f0_1 <= status_ready_matrix_f0_1 OR ready_matrix_f0_1;
272 status_ready_matrix_f1 <= status_ready_matrix_f1 OR ready_matrix_f1;
273 status_ready_matrix_f2 <= status_ready_matrix_f2 OR ready_matrix_f2;
274 END IF;
275 END PROCESS;
276
362
363
364 -- PROCESS (clk25MHz, rstn)
365 -- BEGIN -- PROCESS
366 -- IF rstn = '0' THEN -- asynchronous reset (active low)
367 -- status_ready_matrix_f0 <= '0';
368 ---- status_ready_matrix_f0_1 <= '0';
369 -- status_ready_matrix_f1 <= '0';
370 -- status_ready_matrix_f2 <= '0';
371 -- ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
372 -- status_ready_matrix_f0 <= status_ready_matrix_f0 OR ready_matrix_f0;
373 ---- status_ready_matrix_f0_1 <= status_ready_matrix_f0_1 OR ready_matrix_f0_1;
374 -- status_ready_matrix_f1 <= status_ready_matrix_f1 OR ready_matrix_f1;
375 -- status_ready_matrix_f2 <= status_ready_matrix_f2 OR ready_matrix_f2;
376 -- END IF;
377 -- END PROCESS;
277 378
278 379
279 380
280 381 -- status_error_anticipating_empty_fifo <= '0';
281 382 -- status_error_bad_component_error <= '0';
282 383
283 config_active_interruption_onNewMatrix <= '0';
284 config_active_interruption_onError <= '0';
285 addr_matrix_f0 <= (OTHERS => '0');
384 -- config_active_interruption_onNewMatrix <= '0';
385 -- config_active_interruption_onError <= '0';
386 -- addr_matrix_f0 <= (OTHERS => '0');
286 387 -- addr_matrix_f0_1 <= (OTHERS => '0');
287 addr_matrix_f1 <= (OTHERS => '0');
288 addr_matrix_f2 <= (OTHERS => '0');
388 -- addr_matrix_f1 <= (OTHERS => '0');
389 -- addr_matrix_f2 <= (OTHERS => '0');
289 390
290 391
291 392 PROCESS (clk25MHz, rstn)
292 393 BEGIN -- PROCESS
293 394 IF rstn = '0' THEN -- asynchronous reset (active low)
294 395
295 396 dma_ren <= '1';
296 397 dma_done <= '0';
297 398 ren_counter <= 0;
298 399 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
299 400 dma_ren <= '1';
300 401 dma_done <= '0';
301 402
302 403 IF dma_valid_burst = '1' THEN
303 404 ren_counter <= 17;
304 405 END IF;
305 406
306 407 IF ren_counter > 1 THEN
307 408 ren_counter <= ren_counter - 1;
308 409 dma_ren <= '0';
309 410 END IF;
310 411
311 412 IF ren_counter = 1 THEN
312 413 ren_counter <= 0;
313 414 dma_done <= '1';
314 415 END IF;
315 416
316 417 END IF;
317 418 END PROCESS;
318 419
319 420
320 421 END beh;
321 422
Show file before | Show file after | Hide comments
@@ -1,716 +1,722
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 12 USE lpp.lpp_top_lfr_pkg.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY lpp_lfr IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 nb_data_by_buffer_size : INTEGER := 11;
29 29 nb_word_by_buffer_size : INTEGER := 11;
30 30 nb_snapshot_param_size : INTEGER := 11;
31 31 delta_vector_size : INTEGER := 20;
32 32 delta_vector_size_f0_2 : INTEGER := 7;
33 33
34 34 pindex : INTEGER := 4;
35 35 paddr : INTEGER := 4;
36 36 pmask : INTEGER := 16#fff#;
37 37 pirq_ms : INTEGER := 0;
38 38 pirq_wfp : INTEGER := 1;
39 39
40 40 hindex : INTEGER := 2;
41 41
42 42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43 43
44 44 );
45 45 PORT (
46 46 clk : IN STD_LOGIC;
47 47 rstn : IN STD_LOGIC;
48 48 -- SAMPLE
49 49 sample_B : IN Samples(2 DOWNTO 0);
50 50 sample_E : IN Samples(4 DOWNTO 0);
51 51 sample_val : IN STD_LOGIC;
52 52 -- APB
53 53 apbi : IN apb_slv_in_type;
54 54 apbo : OUT apb_slv_out_type;
55 55 -- AHB
56 56 ahbi : IN AHB_Mst_In_Type;
57 57 ahbo : OUT AHB_Mst_Out_Type;
58 58 -- TIME
59 59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 61 --
62 62 data_shaping_BW : OUT STD_LOGIC;
63 63 --
64 64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65 65
66 66 --debug
67 67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 68 --debug_f0_data_valid : OUT STD_LOGIC;
69 69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 70 --debug_f1_data_valid : OUT STD_LOGIC;
71 71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 72 --debug_f2_data_valid : OUT STD_LOGIC;
73 73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 74 --debug_f3_data_valid : OUT STD_LOGIC;
75 75
76 76 ---- debug FIFO_IN
77 77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
79 79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
81 81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
83 83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
85 85
86 86 ----debug FIFO OUT
87 87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
89 89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
91 91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
93 93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
95 95
96 96 ----debug DMA IN
97 97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
99 99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
101 101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
103 103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
105 105 );
106 106 END lpp_lfr;
107 107
108 108 ARCHITECTURE beh OF lpp_lfr IS
109 109 --SIGNAL sample : Samples14v(7 DOWNTO 0);
110 110 SIGNAL sample_s : Samples(7 DOWNTO 0);
111 111 --
112 112 SIGNAL data_shaping_SP0 : STD_LOGIC;
113 113 SIGNAL data_shaping_SP1 : STD_LOGIC;
114 114 SIGNAL data_shaping_R0 : STD_LOGIC;
115 115 SIGNAL data_shaping_R1 : STD_LOGIC;
116 116 --
117 117 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 118 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
120 120 --
121 121 SIGNAL sample_f0_val : STD_LOGIC;
122 122 SIGNAL sample_f1_val : STD_LOGIC;
123 123 SIGNAL sample_f2_val : STD_LOGIC;
124 124 SIGNAL sample_f3_val : STD_LOGIC;
125 125 --
126 126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 130 --
131 131 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 132 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 133 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
134 134
135 135 -- SM
136 136 SIGNAL ready_matrix_f0 : STD_LOGIC;
137 137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
138 138 SIGNAL ready_matrix_f1 : STD_LOGIC;
139 139 SIGNAL ready_matrix_f2 : STD_LOGIC;
140 140 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
141 141 SIGNAL error_bad_component_error : STD_LOGIC;
142 142 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 143 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
144 144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
145 145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
146 146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
147 147 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
148 148 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
149 149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
150 150 SIGNAL config_active_interruption_onError : STD_LOGIC;
151 151 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 152 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 155
156 156 -- WFP
157 157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
164 164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 166
167 167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
168 168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
169 169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
170 170 SIGNAL enable_f0 : STD_LOGIC;
171 171 SIGNAL enable_f1 : STD_LOGIC;
172 172 SIGNAL enable_f2 : STD_LOGIC;
173 173 SIGNAL enable_f3 : STD_LOGIC;
174 174 SIGNAL burst_f0 : STD_LOGIC;
175 175 SIGNAL burst_f1 : STD_LOGIC;
176 176 SIGNAL burst_f2 : STD_LOGIC;
177 177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 181
182 182 SIGNAL run : STD_LOGIC;
183 183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
184 184
185 185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
188 188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
189 189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
190 190 --f1
191 191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
194 194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
195 195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
196 196 --f2
197 197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
200 200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
201 201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
202 202 --f3
203 203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
206 206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
207 207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
208 208
209 209 -----------------------------------------------------------------------------
210 210 --
211 211 -----------------------------------------------------------------------------
212 212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
214 214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
215 215 --f1
216 216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
218 218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
219 219 --f2
220 220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
222 222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
223 223 --f3
224 224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
226 226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
227 227
228 228 -----------------------------------------------------------------------------
229 229 -- DMA RR
230 230 -----------------------------------------------------------------------------
231 231 SIGNAL dma_sel_valid : STD_LOGIC;
232 232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
236 236
237 237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
239 239
240 240 -----------------------------------------------------------------------------
241 241 -- DMA_REG
242 242 -----------------------------------------------------------------------------
243 243 SIGNAL ongoing_reg : STD_LOGIC;
244 244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
245 245 SIGNAL dma_send_reg : STD_LOGIC;
246 246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
247 247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
249 249
250 250
251 251 -----------------------------------------------------------------------------
252 252 -- DMA
253 253 -----------------------------------------------------------------------------
254 254 SIGNAL dma_send : STD_LOGIC;
255 255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
256 256 SIGNAL dma_done : STD_LOGIC;
257 257 SIGNAL dma_ren : STD_LOGIC;
258 258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
261 261
262 262 -----------------------------------------------------------------------------
263 263 -- MS
264 264 -----------------------------------------------------------------------------
265 265
266 266 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
267 267 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
268 268 SIGNAL data_ms_valid : STD_LOGIC;
269 269 SIGNAL data_ms_valid_burst : STD_LOGIC;
270 270 SIGNAL data_ms_ren : STD_LOGIC;
271 271 SIGNAL data_ms_done : STD_LOGIC;
272 272
273 273 SIGNAL run_ms : STD_LOGIC;
274 274 SIGNAL ms_softandhard_rstn : STD_LOGIC;
275 275
276 276 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
277 277 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
278 278 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
279 279 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
280 280
281 281
282 282 SIGNAL error_buffer_full : STD_LOGIC;
283 283 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
284
284
285 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
286
285 287 BEGIN
286 288
287 289 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
288 290 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
289 291
290 292 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
291 293 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
292 294 --END GENERATE all_channel;
293 295
294 296 -----------------------------------------------------------------------------
295 297 lpp_lfr_filter_1 : lpp_lfr_filter
296 298 GENERIC MAP (
297 299 Mem_use => Mem_use)
298 300 PORT MAP (
299 301 sample => sample_s,
300 302 sample_val => sample_val,
301 303 clk => clk,
302 304 rstn => rstn,
303 305 data_shaping_SP0 => data_shaping_SP0,
304 306 data_shaping_SP1 => data_shaping_SP1,
305 307 data_shaping_R0 => data_shaping_R0,
306 308 data_shaping_R1 => data_shaping_R1,
307 309 sample_f0_val => sample_f0_val,
308 310 sample_f1_val => sample_f1_val,
309 311 sample_f2_val => sample_f2_val,
310 312 sample_f3_val => sample_f3_val,
311 313 sample_f0_wdata => sample_f0_data,
312 314 sample_f1_wdata => sample_f1_data,
313 315 sample_f2_wdata => sample_f2_data,
314 316 sample_f3_wdata => sample_f3_data);
315 317
316 318 -----------------------------------------------------------------------------
317 319 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
318 320 GENERIC MAP (
319 321 nb_data_by_buffer_size => nb_data_by_buffer_size,
320 322 nb_word_by_buffer_size => nb_word_by_buffer_size,
321 323 nb_snapshot_param_size => nb_snapshot_param_size,
322 324 delta_vector_size => delta_vector_size,
323 325 delta_vector_size_f0_2 => delta_vector_size_f0_2,
324 326 pindex => pindex,
325 327 paddr => paddr,
326 328 pmask => pmask,
327 329 pirq_ms => pirq_ms,
328 330 pirq_wfp => pirq_wfp,
329 331 top_lfr_version => top_lfr_version)
330 332 PORT MAP (
331 333 HCLK => clk,
332 334 HRESETn => rstn,
333 335 apbi => apbi,
334 336 apbo => apbo,
335 337
336 338 run_ms => run_ms,
337 339
338 340 ready_matrix_f0 => ready_matrix_f0,
339 341 -- ready_matrix_f0_1 => ready_matrix_f0_1,
340 342 ready_matrix_f1 => ready_matrix_f1,
341 343 ready_matrix_f2 => ready_matrix_f2,
342 344 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
343 345 error_bad_component_error => error_bad_component_error,
344 346 error_buffer_full => error_buffer_full, -- TODO
345 347 error_input_fifo_write => error_input_fifo_write, -- TODO
346 348 -- debug_reg => debug_reg,
347 349 status_ready_matrix_f0 => status_ready_matrix_f0,
348 350 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
349 351 status_ready_matrix_f1 => status_ready_matrix_f1,
350 352 status_ready_matrix_f2 => status_ready_matrix_f2,
351 353 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
352 354 -- status_error_bad_component_error => status_error_bad_component_error,
353 355 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
354 356 config_active_interruption_onError => config_active_interruption_onError,
355 357
356 358 matrix_time_f0 => matrix_time_f0,
357 359 -- matrix_time_f0_1 => matrix_time_f0_1,
358 360 matrix_time_f1 => matrix_time_f1,
359 361 matrix_time_f2 => matrix_time_f2,
360 362
361 363 addr_matrix_f0 => addr_matrix_f0,
362 364 -- addr_matrix_f0_1 => addr_matrix_f0_1,
363 365 addr_matrix_f1 => addr_matrix_f1,
364 366 addr_matrix_f2 => addr_matrix_f2,
365 367 -------------------------------------------------------------------------
366 368 status_full => status_full,
367 369 status_full_ack => status_full_ack,
368 370 status_full_err => status_full_err,
369 371 status_new_err => status_new_err,
370 372 data_shaping_BW => data_shaping_BW,
371 373 data_shaping_SP0 => data_shaping_SP0,
372 374 data_shaping_SP1 => data_shaping_SP1,
373 375 data_shaping_R0 => data_shaping_R0,
374 376 data_shaping_R1 => data_shaping_R1,
375 377 delta_snapshot => delta_snapshot,
376 378 delta_f0 => delta_f0,
377 379 delta_f0_2 => delta_f0_2,
378 380 delta_f1 => delta_f1,
379 381 delta_f2 => delta_f2,
380 382 nb_data_by_buffer => nb_data_by_buffer,
381 383 nb_word_by_buffer => nb_word_by_buffer,
382 384 nb_snapshot_param => nb_snapshot_param,
383 385 enable_f0 => enable_f0,
384 386 enable_f1 => enable_f1,
385 387 enable_f2 => enable_f2,
386 388 enable_f3 => enable_f3,
387 389 burst_f0 => burst_f0,
388 390 burst_f1 => burst_f1,
389 391 burst_f2 => burst_f2,
390 392 run => run,
391 393 addr_data_f0 => addr_data_f0,
392 394 addr_data_f1 => addr_data_f1,
393 395 addr_data_f2 => addr_data_f2,
394 396 addr_data_f3 => addr_data_f3,
395 397 start_date => start_date);
396 398
397 399 -----------------------------------------------------------------------------
398 400 -----------------------------------------------------------------------------
399 401 lpp_waveform_1 : lpp_waveform
400 402 GENERIC MAP (
401 403 tech => inferred,
402 404 data_size => 6*16,
403 405 nb_data_by_buffer_size => nb_data_by_buffer_size,
404 406 nb_word_by_buffer_size => nb_word_by_buffer_size,
405 407 nb_snapshot_param_size => nb_snapshot_param_size,
406 408 delta_vector_size => delta_vector_size,
407 409 delta_vector_size_f0_2 => delta_vector_size_f0_2
408 410 )
409 411 PORT MAP (
410 412 clk => clk,
411 413 rstn => rstn,
412 414
413 415 reg_run => run,
414 416 reg_start_date => start_date,
415 417 reg_delta_snapshot => delta_snapshot,
416 418 reg_delta_f0 => delta_f0,
417 419 reg_delta_f0_2 => delta_f0_2,
418 420 reg_delta_f1 => delta_f1,
419 421 reg_delta_f2 => delta_f2,
420 422
421 423 enable_f0 => enable_f0,
422 424 enable_f1 => enable_f1,
423 425 enable_f2 => enable_f2,
424 426 enable_f3 => enable_f3,
425 427 burst_f0 => burst_f0,
426 428 burst_f1 => burst_f1,
427 429 burst_f2 => burst_f2,
428 430
429 431 nb_data_by_buffer => nb_data_by_buffer,
430 432 nb_word_by_buffer => nb_word_by_buffer,
431 433 nb_snapshot_param => nb_snapshot_param,
432 434 status_full => status_full,
433 435 status_full_ack => status_full_ack,
434 436 status_full_err => status_full_err,
435 437 status_new_err => status_new_err,
436 438
437 439 coarse_time => coarse_time,
438 440 fine_time => fine_time,
439 441
440 442 --f0
441 443 addr_data_f0 => addr_data_f0,
442 444 data_f0_in_valid => sample_f0_val,
443 445 data_f0_in => sample_f0_data,
444 446 --f1
445 447 addr_data_f1 => addr_data_f1,
446 448 data_f1_in_valid => sample_f1_val,
447 449 data_f1_in => sample_f1_data,
448 450 --f2
449 451 addr_data_f2 => addr_data_f2,
450 452 data_f2_in_valid => sample_f2_val,
451 453 data_f2_in => sample_f2_data,
452 454 --f3
453 455 addr_data_f3 => addr_data_f3,
454 456 data_f3_in_valid => sample_f3_val,
455 457 data_f3_in => sample_f3_data,
456 458 -- OUTPUT -- DMA interface
457 459 --f0
458 460 data_f0_addr_out => data_f0_addr_out_s,
459 461 data_f0_data_out => data_f0_data_out,
460 462 data_f0_data_out_valid => data_f0_data_out_valid_s,
461 463 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
462 464 data_f0_data_out_ren => data_f0_data_out_ren,
463 465 --f1
464 466 data_f1_addr_out => data_f1_addr_out_s,
465 467 data_f1_data_out => data_f1_data_out,
466 468 data_f1_data_out_valid => data_f1_data_out_valid_s,
467 469 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
468 470 data_f1_data_out_ren => data_f1_data_out_ren,
469 471 --f2
470 472 data_f2_addr_out => data_f2_addr_out_s,
471 473 data_f2_data_out => data_f2_data_out,
472 474 data_f2_data_out_valid => data_f2_data_out_valid_s,
473 475 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
474 476 data_f2_data_out_ren => data_f2_data_out_ren,
475 477 --f3
476 478 data_f3_addr_out => data_f3_addr_out_s,
477 479 data_f3_data_out => data_f3_data_out,
478 480 data_f3_data_out_valid => data_f3_data_out_valid_s,
479 481 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
480 482 data_f3_data_out_ren => data_f3_data_out_ren ,
481 483
482 484 -------------------------------------------------------------------------
483 485 observation_reg => OPEN
484 486
485 487 );
486 488
487 489
488 490 -----------------------------------------------------------------------------
489 491 -- TEMP
490 492 -----------------------------------------------------------------------------
491 493
492 494 PROCESS (clk, rstn)
493 495 BEGIN -- PROCESS
494 496 IF rstn = '0' THEN -- asynchronous reset (active low)
495 497 data_f0_data_out_valid <= '0';
496 498 data_f0_data_out_valid_burst <= '0';
497 499 data_f1_data_out_valid <= '0';
498 500 data_f1_data_out_valid_burst <= '0';
499 501 data_f2_data_out_valid <= '0';
500 502 data_f2_data_out_valid_burst <= '0';
501 503 data_f3_data_out_valid <= '0';
502 504 data_f3_data_out_valid_burst <= '0';
503 505 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
504 506 data_f0_data_out_valid <= data_f0_data_out_valid_s;
505 507 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
506 508 data_f1_data_out_valid <= data_f1_data_out_valid_s;
507 509 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
508 510 data_f2_data_out_valid <= data_f2_data_out_valid_s;
509 511 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
510 512 data_f3_data_out_valid <= data_f3_data_out_valid_s;
511 513 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
512 514 END IF;
513 515 END PROCESS;
514 516
515 517 data_f0_addr_out <= data_f0_addr_out_s;
516 518 data_f1_addr_out <= data_f1_addr_out_s;
517 519 data_f2_addr_out <= data_f2_addr_out_s;
518 520 data_f3_addr_out <= data_f3_addr_out_s;
519 521
520 522 -----------------------------------------------------------------------------
521 523 -- RoundRobin Selection For DMA
522 524 -----------------------------------------------------------------------------
523 525
524 526 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
525 527 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
526 528 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
527 529 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
528 530
529 531 RR_Arbiter_4_1 : RR_Arbiter_4
530 532 PORT MAP (
531 533 clk => clk,
532 534 rstn => rstn,
533 535 in_valid => dma_rr_valid,
534 536 out_grant => dma_rr_grant_s);
535 537
536 538 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
537 539 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
538 540 dma_rr_valid_ms(2) <= '0';
539 541 dma_rr_valid_ms(3) <= '0';
540 542
541 543 RR_Arbiter_4_2 : RR_Arbiter_4
542 544 PORT MAP (
543 545 clk => clk,
544 546 rstn => rstn,
545 547 in_valid => dma_rr_valid_ms,
546 548 out_grant => dma_rr_grant_ms);
547 549
548 550 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
549 551
550 552
551 553 -----------------------------------------------------------------------------
552 554 -- in : dma_rr_grant
553 555 -- send
554 556 -- out : dma_sel
555 557 -- dma_valid_burst
556 558 -- dma_sel_valid
557 559 -----------------------------------------------------------------------------
558 560 PROCESS (clk, rstn)
559 561 BEGIN -- PROCESS
560 562 IF rstn = '0' THEN -- asynchronous reset (active low)
561 563 dma_sel <= (OTHERS => '0');
562 564 dma_send <= '0';
563 565 dma_valid_burst <= '0';
564 566 data_ms_done <= '0';
565 567 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
566 568 IF run = '1' THEN
567 569 data_ms_done <= '0';
568 570 IF dma_sel = "00000" OR dma_done = '1' THEN
569 571 dma_sel <= dma_rr_grant;
570 572 IF dma_rr_grant(0) = '1' THEN
571 573 dma_send <= '1';
572 574 dma_valid_burst <= data_f0_data_out_valid_burst;
573 575 dma_sel_valid <= data_f0_data_out_valid;
574 576 ELSIF dma_rr_grant(1) = '1' THEN
575 577 dma_send <= '1';
576 578 dma_valid_burst <= data_f1_data_out_valid_burst;
577 579 dma_sel_valid <= data_f1_data_out_valid;
578 580 ELSIF dma_rr_grant(2) = '1' THEN
579 581 dma_send <= '1';
580 582 dma_valid_burst <= data_f2_data_out_valid_burst;
581 583 dma_sel_valid <= data_f2_data_out_valid;
582 584 ELSIF dma_rr_grant(3) = '1' THEN
583 585 dma_send <= '1';
584 586 dma_valid_burst <= data_f3_data_out_valid_burst;
585 587 dma_sel_valid <= data_f3_data_out_valid;
586 588 ELSIF dma_rr_grant(4) = '1' THEN
587 589 dma_send <= '1';
588 590 dma_valid_burst <= data_ms_valid_burst;
589 591 dma_sel_valid <= data_ms_valid;
590 592 END IF;
591 593
592 594 IF dma_sel(4) = '1' THEN
593 595 data_ms_done <= '1';
594 596 END IF;
595 597 ELSE
596 598 dma_sel <= dma_sel;
597 599 dma_send <= '0';
598 600 END IF;
599 601 ELSE
600 602 data_ms_done <= '0';
601 603 dma_sel <= (OTHERS => '0');
602 604 dma_send <= '0';
603 605 dma_valid_burst <= '0';
604 606 END IF;
605 607 END IF;
606 608 END PROCESS;
607 609
608 610
609 611 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
610 612 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
611 613 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
612 614 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
613 615 data_ms_addr;
614 616
615 617 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
616 618 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
617 619 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
618 620 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
619 621 data_ms_data;
620 622
621 623 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
622 624 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
623 625 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
624 626 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
625 627 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
626 628
627 629 dma_data_2 <= dma_data;
628 630
629 631
630 632 -----------------------------------------------------------------------------
631 633 -- DMA
632 634 -----------------------------------------------------------------------------
633 635 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
634 636 GENERIC MAP (
635 637 tech => inferred,
636 638 hindex => hindex)
637 639 PORT MAP (
638 640 HCLK => clk,
639 641 HRESETn => rstn,
640 642 run => run,
641 643 AHB_Master_In => ahbi,
642 644 AHB_Master_Out => ahbo,
643 645
644 646 send => dma_send,
645 647 valid_burst => dma_valid_burst,
646 648 done => dma_done,
647 649 ren => dma_ren,
648 650 address => dma_address,
649 651 data => dma_data_2);
650 652
651 653 -----------------------------------------------------------------------------
652 654 -- Matrix Spectral
653 655 -----------------------------------------------------------------------------
654 656 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
655 657 NOT(sample_f0_val) & NOT(sample_f0_val);
656 658 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
657 659 NOT(sample_f1_val) & NOT(sample_f1_val);
658 660 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
659 661 NOT(sample_f3_val) & NOT(sample_f3_val);
660 662
661 663 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
662 664 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
663 665 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
664 666
665 667 -------------------------------------------------------------------------------
666 668
667 669 ms_softandhard_rstn <= rstn AND run_ms AND run;
668 670
669 671 -----------------------------------------------------------------------------
670 672 lpp_lfr_ms_1 : lpp_lfr_ms
671 673 GENERIC MAP (
672 674 Mem_use => Mem_use)
673 675 PORT MAP (
674 676 clk => clk,
675 677 rstn => ms_softandhard_rstn, --rstn,
676 678
677 679 coarse_time => coarse_time,
678 680 fine_time => fine_time,
679 681
680 682 sample_f0_wen => sample_f0_wen,
681 683 sample_f0_wdata => sample_f0_wdata,
682 684 sample_f1_wen => sample_f1_wen,
683 685 sample_f1_wdata => sample_f1_wdata,
684 686 sample_f2_wen => sample_f3_wen, -- TODO
685 687 sample_f2_wdata => sample_f3_wdata,-- TODO
686 688
687 689 dma_addr => data_ms_addr, --
688 690 dma_data => data_ms_data, --
689 691 dma_valid => data_ms_valid, --
690 692 dma_valid_burst => data_ms_valid_burst, --
691 693 dma_ren => data_ms_ren, --
692 694 dma_done => data_ms_done, --
693 695
694 696 ready_matrix_f0 => ready_matrix_f0,
695 697 ready_matrix_f1 => ready_matrix_f1,
696 698 ready_matrix_f2 => ready_matrix_f2,
697 699 error_bad_component_error => error_bad_component_error,
698 700 error_buffer_full => error_buffer_full,
699 701 error_input_fifo_write => error_input_fifo_write,
700 702
701 debug_reg => observation_reg,
703 debug_reg => debug_ms,--observation_reg,
702 704
703 705 status_ready_matrix_f0 => status_ready_matrix_f0,
704 706 status_ready_matrix_f1 => status_ready_matrix_f1,
705 707 status_ready_matrix_f2 => status_ready_matrix_f2,
706 708 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
707 709 config_active_interruption_onError => config_active_interruption_onError,
708 710 addr_matrix_f0 => addr_matrix_f0,
709 711 addr_matrix_f1 => addr_matrix_f1,
710 712 addr_matrix_f2 => addr_matrix_f2,
711 713
712 714 matrix_time_f0 => matrix_time_f0,
713 715 matrix_time_f1 => matrix_time_f1,
714 716 matrix_time_f2 => matrix_time_f2);
715 717
718 -----------------------------------------------------------------------------
719 observation_reg(31 DOWNTO 0) <= debug_ms(30 DOWNTO 0) & ms_softandhard_rstn;
720
721
716 722 END beh;
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@@ -1,683 +1,675
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26 LIBRARY grlib;
27 27 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30 LIBRARY lpp;
31 31 USE lpp.lpp_lfr_pkg.ALL;
32 USE lpp.lpp_amba.ALL;
32 --USE lpp.lpp_amba.ALL;
33 33 USE lpp.apb_devices_list.ALL;
34 34 USE lpp.lpp_memory.ALL;
35 35 LIBRARY techmap;
36 36 USE techmap.gencomp.ALL;
37 37
38 38 ENTITY lpp_lfr_apbreg IS
39 39 GENERIC (
40 40 nb_data_by_buffer_size : INTEGER := 11;
41 41 nb_word_by_buffer_size : INTEGER := 11;
42 42 nb_snapshot_param_size : INTEGER := 11;
43 43 delta_vector_size : INTEGER := 20;
44 44 delta_vector_size_f0_2 : INTEGER := 3;
45 45
46 46 pindex : INTEGER := 4;
47 47 paddr : INTEGER := 4;
48 48 pmask : INTEGER := 16#fff#;
49 49 pirq_ms : INTEGER := 0;
50 50 pirq_wfp : INTEGER := 1;
51 51 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
52 52 PORT (
53 53 -- AMBA AHB system signals
54 54 HCLK : IN STD_ULOGIC;
55 55 HRESETn : IN STD_ULOGIC;
56 56
57 57 -- AMBA APB Slave Interface
58 58 apbi : IN apb_slv_in_type;
59 59 apbo : OUT apb_slv_out_type;
60 60
61 61 ---------------------------------------------------------------------------
62 62 -- Spectral Matrix Reg
63 63 run_ms : OUT STD_LOGIC;
64 64 -- IN
65 65 ready_matrix_f0 : IN STD_LOGIC;
66 66 ready_matrix_f1 : IN STD_LOGIC;
67 67 ready_matrix_f2 : IN STD_LOGIC;
68 68
69 69 error_bad_component_error : IN STD_LOGIC;
70 70 error_buffer_full : IN STD_LOGIC; -- TODO
71 71 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
72 72
73 73 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 74
75 75 -- OUT
76 76 status_ready_matrix_f0 : OUT STD_LOGIC;
77 77 status_ready_matrix_f1 : OUT STD_LOGIC;
78 78 status_ready_matrix_f2 : OUT STD_LOGIC;
79 79
80 80 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
81 81 config_active_interruption_onError : OUT STD_LOGIC;
82 82
83 83 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86
87 87 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
88 88 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
89 89 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
90 90
91 91 ---------------------------------------------------------------------------
92 92 ---------------------------------------------------------------------------
93 93 -- WaveForm picker Reg
94 94 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
95 95 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
96 96 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
97 97 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
98 98
99 99 -- OUT
100 100 data_shaping_BW : OUT STD_LOGIC;
101 101 data_shaping_SP0 : OUT STD_LOGIC;
102 102 data_shaping_SP1 : OUT STD_LOGIC;
103 103 data_shaping_R0 : OUT STD_LOGIC;
104 104 data_shaping_R1 : OUT STD_LOGIC;
105 105
106 106 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
107 107 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
108 108 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
109 109 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
110 110 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
111 111 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
112 112 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
113 113 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
114 114
115 115 enable_f0 : OUT STD_LOGIC;
116 116 enable_f1 : OUT STD_LOGIC;
117 117 enable_f2 : OUT STD_LOGIC;
118 118 enable_f3 : OUT STD_LOGIC;
119 119
120 120 burst_f0 : OUT STD_LOGIC;
121 121 burst_f1 : OUT STD_LOGIC;
122 122 burst_f2 : OUT STD_LOGIC;
123 123
124 124 run : OUT STD_LOGIC;
125 125
126 126 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 127 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 128 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 129 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 130 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
131 131 ---------------------------------------------------------------------------
132 132 );
133 133
134 134 END lpp_lfr_apbreg;
135 135
136 136 ARCHITECTURE beh OF lpp_lfr_apbreg IS
137 137
138 138 CONSTANT REVISION : INTEGER := 1;
139
139
140 140 CONSTANT pconfig : apb_config_type := (
141 141 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
142 142 1 => apb_iobar(paddr, pmask));
143
143
144 144 TYPE lpp_SpectralMatrix_regs IS RECORD
145 145 config_active_interruption_onNewMatrix : STD_LOGIC;
146 146 config_active_interruption_onError : STD_LOGIC;
147 147 config_ms_run : STD_LOGIC;
148 148 status_ready_matrix_f0_0 : STD_LOGIC;
149 149 status_ready_matrix_f1_0 : STD_LOGIC;
150 150 status_ready_matrix_f2_0 : STD_LOGIC;
151 151 status_ready_matrix_f0_1 : STD_LOGIC;
152 152 status_ready_matrix_f1_1 : STD_LOGIC;
153 153 status_ready_matrix_f2_1 : STD_LOGIC;
154 154 status_error_bad_component_error : STD_LOGIC;
155 155 status_error_buffer_full : STD_LOGIC;
156 156 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
157 157
158 158 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 159 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 160 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 161 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 162 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
163 163 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
164 164
165 165 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
166 166 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
167 167 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
168 168 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
169 169 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
170 170 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
171 171 END RECORD;
172 172 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
173 173
174 174 TYPE lpp_WaveformPicker_regs IS RECORD
175 175 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 176 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
177 177 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 178 data_shaping_BW : STD_LOGIC;
179 179 data_shaping_SP0 : STD_LOGIC;
180 180 data_shaping_SP1 : STD_LOGIC;
181 181 data_shaping_R0 : STD_LOGIC;
182 182 data_shaping_R1 : STD_LOGIC;
183 183 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
184 184 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
185 185 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
186 186 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
187 187 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
188 188 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
189 189 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
190 190 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
191 191 enable_f0 : STD_LOGIC;
192 192 enable_f1 : STD_LOGIC;
193 193 enable_f2 : STD_LOGIC;
194 194 enable_f3 : STD_LOGIC;
195 195 burst_f0 : STD_LOGIC;
196 196 burst_f1 : STD_LOGIC;
197 197 burst_f2 : STD_LOGIC;
198 198 run : STD_LOGIC;
199 199 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
200 200 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
201 201 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 202 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 203 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
204 204 END RECORD;
205 205 SIGNAL reg_wp : lpp_WaveformPicker_regs;
206 206
207 207 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 208
209 209 -----------------------------------------------------------------------------
210 210 -- IRQ
211 211 -----------------------------------------------------------------------------
212 212 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
213 213 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
214 214 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
215 215 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
216 216 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
217 217 SIGNAL ored_irq_wfp : STD_LOGIC;
218 218
219 219 -----------------------------------------------------------------------------
220 220 --
221 221 -----------------------------------------------------------------------------
222 222 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
223 223 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 224 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
225 225
226 226 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
227 227 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
228 228 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
229 229
230 230 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
231 231 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
232 232 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
233 233
234 234 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
235 235 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
236 236 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
237 237
238 238 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
239 239 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
240 240 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
241 241
242 242 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
243 243 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
244 244 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
245 245
246 246 BEGIN -- beh
247 247
248 248 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
249 249 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
250 250 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
251 251
252 252 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
253 253 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
254 254
255 255
256 256 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
257 257 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
258 258 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
259 259
260 260
261 261 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
262 262 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
263 263 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
264 264 data_shaping_R0 <= reg_wp.data_shaping_R0;
265 265 data_shaping_R1 <= reg_wp.data_shaping_R1;
266 266
267 267 delta_snapshot <= reg_wp.delta_snapshot;
268 268 delta_f0 <= reg_wp.delta_f0;
269 269 delta_f0_2 <= reg_wp.delta_f0_2;
270 270 delta_f1 <= reg_wp.delta_f1;
271 271 delta_f2 <= reg_wp.delta_f2;
272 272 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
273 273 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
274 274 nb_snapshot_param <= reg_wp.nb_snapshot_param;
275 275
276 276 enable_f0 <= reg_wp.enable_f0;
277 277 enable_f1 <= reg_wp.enable_f1;
278 278 enable_f2 <= reg_wp.enable_f2;
279 279 enable_f3 <= reg_wp.enable_f3;
280 280
281 281 burst_f0 <= reg_wp.burst_f0;
282 282 burst_f1 <= reg_wp.burst_f1;
283 283 burst_f2 <= reg_wp.burst_f2;
284 284
285 285 run <= reg_wp.run;
286 286
287 287 addr_data_f0 <= reg_wp.addr_data_f0;
288 288 addr_data_f1 <= reg_wp.addr_data_f1;
289 289 addr_data_f2 <= reg_wp.addr_data_f2;
290 290 addr_data_f3 <= reg_wp.addr_data_f3;
291 291
292 292 start_date <= reg_wp.start_date;
293 293
294 294 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
295 295 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
296 296 BEGIN -- PROCESS lpp_dma_top
297 297 IF HRESETn = '0' THEN -- asynchronous reset (active low)
298 298 reg_sp.config_active_interruption_onNewMatrix <= '0';
299 299 reg_sp.config_active_interruption_onError <= '0';
300 300 reg_sp.config_ms_run <= '1';
301 301 reg_sp.status_ready_matrix_f0_0 <= '0';
302 302 reg_sp.status_ready_matrix_f1_0 <= '0';
303 303 reg_sp.status_ready_matrix_f2_0 <= '0';
304 304 reg_sp.status_ready_matrix_f0_1 <= '0';
305 305 reg_sp.status_ready_matrix_f1_1 <= '0';
306 306 reg_sp.status_ready_matrix_f2_1 <= '0';
307 307 reg_sp.status_error_bad_component_error <= '0';
308 308 reg_sp.status_error_buffer_full <= '0';
309 309 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
310 310
311 311 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
312 312 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
313 313 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
314 314
315 315 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
316 316 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
317 317 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
318 318
319 reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
320 reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
321 reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
319 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
320 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
321 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
322 322
323 reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
324 reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
325 reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
323 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
324 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
325 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
326 326
327 327 prdata <= (OTHERS => '0');
328 328
329 329 apbo.pirq <= (OTHERS => '0');
330 330
331 331 status_full_ack <= (OTHERS => '0');
332 332
333 333 reg_wp.data_shaping_BW <= '0';
334 334 reg_wp.data_shaping_SP0 <= '0';
335 335 reg_wp.data_shaping_SP1 <= '0';
336 336 reg_wp.data_shaping_R0 <= '0';
337 337 reg_wp.data_shaping_R1 <= '0';
338 338 reg_wp.enable_f0 <= '0';
339 339 reg_wp.enable_f1 <= '0';
340 340 reg_wp.enable_f2 <= '0';
341 341 reg_wp.enable_f3 <= '0';
342 342 reg_wp.burst_f0 <= '0';
343 343 reg_wp.burst_f1 <= '0';
344 344 reg_wp.burst_f2 <= '0';
345 345 reg_wp.run <= '0';
346 346 reg_wp.addr_data_f0 <= (OTHERS => '0');
347 347 reg_wp.addr_data_f1 <= (OTHERS => '0');
348 348 reg_wp.addr_data_f2 <= (OTHERS => '0');
349 349 reg_wp.addr_data_f3 <= (OTHERS => '0');
350 350 reg_wp.status_full <= (OTHERS => '0');
351 351 reg_wp.status_full_err <= (OTHERS => '0');
352 352 reg_wp.status_new_err <= (OTHERS => '0');
353 353 reg_wp.delta_snapshot <= (OTHERS => '0');
354 354 reg_wp.delta_f0 <= (OTHERS => '0');
355 355 reg_wp.delta_f0_2 <= (OTHERS => '0');
356 356 reg_wp.delta_f1 <= (OTHERS => '0');
357 357 reg_wp.delta_f2 <= (OTHERS => '0');
358 358 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
359 359 reg_wp.nb_snapshot_param <= (OTHERS => '0');
360 360 reg_wp.start_date <= (OTHERS => '0');
361 361
362 362 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
363
364 reg_sp.time_matrix_f0_0 <= reg0_matrix_time_f0; -- ok
365 reg_sp.time_matrix_f1_0 <= reg0_matrix_time_f1; -- ok
366 reg_sp.time_matrix_f2_0 <= reg0_matrix_time_f2; -- ok
367
368 reg_sp.time_matrix_f0_1 <= reg1_matrix_time_f0; -- ok
369 reg_sp.time_matrix_f1_1 <= reg1_matrix_time_f1; -- ok
370 reg_sp.time_matrix_f2_1 <= reg1_matrix_time_f2; -- ok
371 363
372 364 status_full_ack <= (OTHERS => '0');
373 365
374 366 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
375 367 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
376 368 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
377 369
378 370 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
379 371 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
380 372 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
381 373
382 374 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
383 375
384 376 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
385 377 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
386 378 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
387 379 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
388 380
389 381
390 382
391 383 all_status : FOR I IN 3 DOWNTO 0 LOOP
392 384 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
393 385 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
394 386 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run;
395 387 END LOOP all_status;
396 388
397 389 paddr := "000000";
398 390 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
399 391 prdata <= (OTHERS => '0');
400 392 IF apbi.psel(pindex) = '1' THEN
401 393 -- APB DMA READ --
402 394 CASE paddr(7 DOWNTO 2) IS
403 395 --0
404 396 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
405 397 prdata(1) <= reg_sp.config_active_interruption_onError;
406 398 prdata(2) <= reg_sp.config_ms_run;
407 399 --1
408 400 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
409 401 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
410 402 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
411 403 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
412 404 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
413 405 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
414 406 prdata(6) <= reg_sp.status_error_bad_component_error;
415 407 prdata(7) <= reg_sp.status_error_buffer_full;
416 408 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
417 409 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
418 410 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
419 411 --2
420 412 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
421 413 --3
422 414 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
423 415 --4
424 416 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
425 417 --5
426 418 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
427 419 --6
428 420 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
429 421 --7
430 422 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
431 423 --8
432 424 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
433 425 --9
434 426 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
435 427 --10
436 428 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
437 429 --11
438 430 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
439 431 --12
440 432 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
441 433 --13
442 434 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
443 435 --14
444 436 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
445 437 --15
446 438 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
447 439 --16
448 440 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
449 441 --17
450 442 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
451 443 --18
452 444 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
453 445 --19
454 446 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
455 447 ---------------------------------------------------------------------
456 448 --20
457 449 WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW;
458 450 prdata(1) <= reg_wp.data_shaping_SP0;
459 451 prdata(2) <= reg_wp.data_shaping_SP1;
460 452 prdata(3) <= reg_wp.data_shaping_R0;
461 453 prdata(4) <= reg_wp.data_shaping_R1;
462 454 --21
463 455 WHEN "010101" => prdata(0) <= reg_wp.enable_f0;
464 456 prdata(1) <= reg_wp.enable_f1;
465 457 prdata(2) <= reg_wp.enable_f2;
466 458 prdata(3) <= reg_wp.enable_f3;
467 459 prdata(4) <= reg_wp.burst_f0;
468 460 prdata(5) <= reg_wp.burst_f1;
469 461 prdata(6) <= reg_wp.burst_f2;
470 462 prdata(7) <= reg_wp.run;
471 463 --22
472 464 WHEN "010110" => prdata <= reg_wp.addr_data_f0;
473 465 --23
474 466 WHEN "010111" => prdata <= reg_wp.addr_data_f1;
475 467 --24
476 468 WHEN "011000" => prdata <= reg_wp.addr_data_f2;
477 469 --25
478 470 WHEN "011001" => prdata <= reg_wp.addr_data_f3;
479 471 --26
480 472 WHEN "011010" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
481 473 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
482 474 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
483 475 --27
484 476 WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
485 477 --28
486 478 WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
487 479 --29
488 480 WHEN "011101" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
489 481 --30
490 482 WHEN "011110" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
491 483 --31
492 484 WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
493 485 --32
494 486 WHEN "100000" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
495 487 --33
496 488 WHEN "100001" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
497 489 --34
498 490 WHEN "100010" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
499 491 --35
500 492 WHEN "100011" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
501 493 ----------------------------------------------------
502 494 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
503 495 WHEN OTHERS => NULL;
504 496
505 497 END CASE;
506 498 IF (apbi.pwrite AND apbi.penable) = '1' THEN
507 499 -- APB DMA WRITE --
508 500 CASE paddr(7 DOWNTO 2) IS
509 501 --
510 502 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
511 503 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
512 504 reg_sp.config_ms_run <= apbi.pwdata(2);
513 505 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
514 506 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
515 507 reg_sp.status_ready_matrix_f1_0 <= apbi.pwdata(2);
516 508 reg_sp.status_ready_matrix_f1_1 <= apbi.pwdata(3);
517 509 reg_sp.status_ready_matrix_f2_0 <= apbi.pwdata(4);
518 510 reg_sp.status_ready_matrix_f2_1 <= apbi.pwdata(5);
519 511 reg_sp.status_error_bad_component_error <= apbi.pwdata(6);
520 512 reg_sp.status_error_buffer_full <= apbi.pwdata(7);
521 513 reg_sp.status_error_input_fifo_write(0) <= apbi.pwdata(8);
522 514 reg_sp.status_error_input_fifo_write(1) <= apbi.pwdata(9);
523 515 reg_sp.status_error_input_fifo_write(2) <= apbi.pwdata(10);
524 516 --2
525 517 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
526 518 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
527 519 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
528 520 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
529 521 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
530 522 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
531 523 --8 to 19
532 524 --20
533 525 WHEN "010100" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
534 526 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
535 527 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
536 528 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
537 529 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
538 530 WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0);
539 531 reg_wp.enable_f1 <= apbi.pwdata(1);
540 532 reg_wp.enable_f2 <= apbi.pwdata(2);
541 533 reg_wp.enable_f3 <= apbi.pwdata(3);
542 534 reg_wp.burst_f0 <= apbi.pwdata(4);
543 535 reg_wp.burst_f1 <= apbi.pwdata(5);
544 536 reg_wp.burst_f2 <= apbi.pwdata(6);
545 537 reg_wp.run <= apbi.pwdata(7);
546 538 --22
547 539 WHEN "010110" => reg_wp.addr_data_f0 <= apbi.pwdata;
548 540 WHEN "010111" => reg_wp.addr_data_f1 <= apbi.pwdata;
549 541 WHEN "011000" => reg_wp.addr_data_f2 <= apbi.pwdata;
550 542 WHEN "011001" => reg_wp.addr_data_f3 <= apbi.pwdata;
551 543 --26
552 544 WHEN "011010" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
553 545 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
554 546 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
555 547 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
556 548 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
557 549 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
558 550 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
559 551 WHEN "011011" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
560 552 WHEN "011100" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
561 553 WHEN "011101" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
562 554 WHEN "011110" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
563 555 WHEN "011111" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
564 556 WHEN "100000" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
565 557 WHEN "100001" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
566 558 WHEN "100010" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
567 559 WHEN "100011" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
568 560 --
569 561 WHEN OTHERS => NULL;
570 562 END CASE;
571 563 END IF;
572 564 END IF;
573 565
574 566 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
575 567 ready_matrix_f1 OR
576 568 ready_matrix_f2)
577 569 )
578 570 OR
579 571 (reg_sp.config_active_interruption_onError AND (
580 572 error_bad_component_error
581 573 OR error_buffer_full
582 574 OR error_input_fifo_write(0)
583 575 OR error_input_fifo_write(1)
584 576 OR error_input_fifo_write(2))
585 577 ));
586 578
587 579 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
588 580
589 581 END IF;
590 582 END PROCESS lpp_lfr_apbreg;
591 583
592 584 apbo.pindex <= pindex;
593 585 apbo.pconfig <= pconfig;
594 586 apbo.prdata <= prdata;
595 587
596 588 -----------------------------------------------------------------------------
597 589 -- IRQ
598 590 -----------------------------------------------------------------------------
599 591 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
600 592
601 593 PROCESS (HCLK, HRESETn)
602 594 BEGIN -- PROCESS
603 595 IF HRESETn = '0' THEN -- asynchronous reset (active low)
604 596 irq_wfp_reg <= (OTHERS => '0');
605 597 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
606 598 irq_wfp_reg <= irq_wfp_reg_s;
607 599 END IF;
608 600 END PROCESS;
609 601
610 602 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
611 603 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
612 604 END GENERATE all_irq_wfp;
613 605
614 606 irq_wfp_ZERO <= (OTHERS => '0');
615 607 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
616 608
617 609 run_ms <= reg_sp.config_ms_run;
618 610
619 611 -----------------------------------------------------------------------------
620 612 --
621 613 -----------------------------------------------------------------------------
622 614 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
623 615 PORT MAP (
624 616 clk => HCLK,
625 617 rstn => HRESETn,
626 618
627 619 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
628 620 reg0_ready_matrix => reg0_ready_matrix_f0,
629 reg0_addr_matrix => reg0_addr_matrix_f0,
630 reg0_matrix_time => reg0_matrix_time_f0,
621 reg0_addr_matrix => reg_sp.addr_matrix_f0_0,--reg0_addr_matrix_f0,
622 reg0_matrix_time => reg_sp.time_matrix_f0_0,--reg0_matrix_time_f0,
631 623
632 624 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
633 625 reg1_ready_matrix => reg1_ready_matrix_f0,
634 reg1_addr_matrix => reg1_addr_matrix_f0,
635 reg1_matrix_time => reg1_matrix_time_f0,
626 reg1_addr_matrix => reg_sp.addr_matrix_f0_1,--reg1_addr_matrix_f0,
627 reg1_matrix_time => reg_sp.time_matrix_f0_1,--reg1_matrix_time_f0,
636 628
637 629 ready_matrix => ready_matrix_f0,
638 630 status_ready_matrix => status_ready_matrix_f0,
639 631 addr_matrix => addr_matrix_f0,
640 632 matrix_time => matrix_time_f0);
641 633
642 634 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
643 635 PORT MAP (
644 636 clk => HCLK,
645 637 rstn => HRESETn,
646 638
647 639 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
648 640 reg0_ready_matrix => reg0_ready_matrix_f1,
649 reg0_addr_matrix => reg0_addr_matrix_f1,
650 reg0_matrix_time => reg0_matrix_time_f1,
641 reg0_addr_matrix => reg_sp.addr_matrix_f1_0,--reg0_addr_matrix_f1,
642 reg0_matrix_time => reg_sp.time_matrix_f1_0,--reg0_matrix_time_f1,
651 643
652 644 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
653 645 reg1_ready_matrix => reg1_ready_matrix_f1,
654 reg1_addr_matrix => reg1_addr_matrix_f1,
655 reg1_matrix_time => reg1_matrix_time_f1,
646 reg1_addr_matrix => reg_sp.addr_matrix_f1_1,--reg1_addr_matrix_f1,
647 reg1_matrix_time => reg_sp.time_matrix_f1_1,--reg1_matrix_time_f1,
656 648
657 649 ready_matrix => ready_matrix_f1,
658 650 status_ready_matrix => status_ready_matrix_f1,
659 651 addr_matrix => addr_matrix_f1,
660 652 matrix_time => matrix_time_f1);
661 653
662 654 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
663 655 PORT MAP (
664 656 clk => HCLK,
665 657 rstn => HRESETn,
666 658
667 659 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
668 660 reg0_ready_matrix => reg0_ready_matrix_f2,
669 reg0_addr_matrix => reg0_addr_matrix_f2,
670 reg0_matrix_time => reg0_matrix_time_f2,
661 reg0_addr_matrix => reg_sp.addr_matrix_f2_0,--reg0_addr_matrix_f2,
662 reg0_matrix_time => reg_sp.time_matrix_f2_0,--reg0_matrix_time_f2,
671 663
672 664 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
673 665 reg1_ready_matrix => reg1_ready_matrix_f2,
674 reg1_addr_matrix => reg1_addr_matrix_f2,
675 reg1_matrix_time => reg1_matrix_time_f2,
666 reg1_addr_matrix => reg_sp.addr_matrix_f2_1,--reg1_addr_matrix_f2,
667 reg1_matrix_time => reg_sp.time_matrix_f2_1,--reg1_matrix_time_f2,
676 668
677 669 ready_matrix => ready_matrix_f2,
678 670 status_ready_matrix => status_ready_matrix_f2,
679 671 addr_matrix => addr_matrix_f2,
680 672 matrix_time => matrix_time_f2);
681 673
682 674
683 END beh; No newline at end of file
675 END beh;
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@@ -1,81 +1,93
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23
24 24 LIBRARY ieee;
25 25 USE ieee.std_logic_1164.ALL;
26 26
27 27 ENTITY lpp_apbreg_ms_pointer IS
28 28
29 29 PORT (
30 30 clk : IN STD_LOGIC;
31 31 rstn : IN STD_LOGIC;
32 32
33 33 -- REG 0
34 34 reg0_status_ready_matrix : IN STD_LOGIC;
35 35 reg0_ready_matrix : OUT STD_LOGIC;
36 36 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
37 37 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
38 38
39 39 -- REG 1
40 40 reg1_status_ready_matrix : IN STD_LOGIC;
41 41 reg1_ready_matrix : OUT STD_LOGIC;
42 42 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
43 43 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
44 44
45 45 -- SpectralMatrix
46 46 ready_matrix : IN STD_LOGIC;
47 47 status_ready_matrix : OUT STD_LOGIC;
48 48 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
49 49 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
50 50 );
51 51
52 52 END lpp_apbreg_ms_pointer;
53 53
54 54 ARCHITECTURE beh OF lpp_apbreg_ms_pointer IS
55 55
56 56 SIGNAL current_reg : STD_LOGIC;
57 57
58 58 BEGIN -- beh
59 59
60 60 PROCESS (clk, rstn)
61 61 BEGIN -- PROCESS
62 62 IF rstn = '0' THEN -- asynchronous reset (active low)
63 63 current_reg <= '0';
64 reg0_matrix_time <= (OTHERS => '0');
65 reg1_matrix_time <= (OTHERS => '0');
64 66
65 67 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
66 68 IF ready_matrix = '1' THEN
67 69 current_reg <= NOT current_reg;
68 70 END IF;
71 IF current_reg = '0' THEN
72 reg0_matrix_time <= matrix_time;
73 END IF;
74 IF current_reg = '1' THEN
75 reg1_matrix_time <= matrix_time;
76 END IF;
77
69 78 END IF;
70 79 END PROCESS;
71 80
72 81 addr_matrix <= reg0_addr_matrix WHEN current_reg = '0' ELSE
73 82 reg1_addr_matrix;
74 83
75 84 status_ready_matrix <= reg0_status_ready_matrix WHEN current_reg = '0' ELSE
76 85 reg1_status_ready_matrix;
77 86
78 87 reg0_ready_matrix <= ready_matrix WHEN current_reg = '0' ELSE '0';
79 88 reg1_ready_matrix <= ready_matrix WHEN current_reg = '1' ELSE '0';
80 89
81 END beh; No newline at end of file
90
91
92
93 END beh;
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