HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r373:8b7232d194b4

update APB_REG

pellion -

r373:8b7232d194b4 JC

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r373:8b7232d194b4

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designs/Validation_LFR_SpectralMatrix/Makefile +5 -2

             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd
-            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd

designs/Validation_LFR_SpectralMatrix/TB.vhd +123 -22

@@ -32,6 +32,12 USE lpp.spectral_matrix_package.ALL;
32	use lpp.lpp_fft.all;	32	use lpp.lpp_fft.all;
33	use lpp.fft_components.all;	33	use lpp.fft_components.all;
34		34
		35	LIBRARY grlib;
		36	USE grlib.amba.ALL;
		37	USE grlib.stdlib.ALL;
		38	USE grlib.devices.ALL;
		39	USE GRLIB.DMA2AHB_Package.ALL;
		40
35	ENTITY TB IS	41	ENTITY TB IS
36		42
37		43
@@ -103,6 +109,15 ARCHITECTURE beh OF TB IS
103	-----------------------------------------------------------------------------	109	-----------------------------------------------------------------------------
104	SIGNAL ren_counter : INTEGER;	110	SIGNAL ren_counter : INTEGER;
105		111
		112	SIGNAL error_buffer_full : STD_LOGIC;
		113	SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
		114	-----------------------------------------------------------------------------
		115	SIGNAL apbi : apb_slv_in_type;
		116	SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
		117	SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
		118	SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
		119	SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
		120
106	BEGIN -- beh	121	BEGIN -- beh
107		122
108	clk25MHz <= NOT clk25MHz AFTER 20 ns;	123	clk25MHz <= NOT clk25MHz AFTER 20 ns;
@@ -234,8 +249,8 BEGIN -- beh
234	ready_matrix_f2 => ready_matrix_f2,	249	ready_matrix_f2 => ready_matrix_f2,
235	-- error_anticipating_empty_fifo => error_anticipating_empty_fifo,	250	-- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
236	error_bad_component_error => error_bad_component_error,	251	error_bad_component_error => error_bad_component_error,
237	error_buffer_full => ~~OPEN~~,	252	error_buffer_full => error_buffer_full,
238	error_input_fifo_write => ~~OPEN~~,	253	error_input_fifo_write => error_input_fifo_write,
239		254
240	debug_reg => debug_reg,	255	debug_reg => debug_reg,
241	status_ready_matrix_f0 => status_ready_matrix_f0,	256	status_ready_matrix_f0 => status_ready_matrix_f0,
@@ -255,37 +270,123 BEGIN -- beh
255	matrix_time_f1 => matrix_time_f1,	270	matrix_time_f1 => matrix_time_f1,
256	matrix_time_f2 => matrix_time_f2);	271	matrix_time_f2 => matrix_time_f2);
257		272
		273
		274
		275
		276	lpp_lfr_apbreg_1 : lpp_lfr_apbreg
		277	GENERIC MAP (
		278	nb_data_by_buffer_size => 11,
		279	nb_word_by_buffer_size => 11,
		280	nb_snapshot_param_size => 11,
		281	delta_vector_size => 20,
		282	delta_vector_size_f0_2 => 7,
		283	pindex => 4,
		284	paddr => 4,
		285	pmask => 16#fff#,
		286	pirq_ms => 0,
		287	pirq_wfp => 1,
		288	top_lfr_version => (OTHERS => '0')
		289	)
		290	PORT MAP (
		291	HCLK => clk25MHz,
		292	HRESETn => rstn,
		293	apbi => apbi,
		294	apbo => OPEN,
		295
		296	run_ms => OPEN,
		297
		298	ready_matrix_f0 => ready_matrix_f0,
		299	ready_matrix_f1 => ready_matrix_f1,
		300	ready_matrix_f2 => ready_matrix_f2,
		301	error_bad_component_error => error_bad_component_error,
		302	error_buffer_full => error_buffer_full, -- TODO
		303	error_input_fifo_write => error_input_fifo_write, -- TODO
		304	status_ready_matrix_f0 => status_ready_matrix_f0,
		305	status_ready_matrix_f1 => status_ready_matrix_f1,
		306	status_ready_matrix_f2 => status_ready_matrix_f2,
		307	config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
		308	config_active_interruption_onError => config_active_interruption_onError,
		309
		310	matrix_time_f0 => matrix_time_f0,
		311	matrix_time_f1 => matrix_time_f1,
		312	matrix_time_f2 => matrix_time_f2,
		313
		314	addr_matrix_f0 => addr_matrix_f0,
		315	addr_matrix_f1 => addr_matrix_f1,
		316	addr_matrix_f2 => addr_matrix_f2,
		317	-------------------------------------------------------------------------
		318	status_full => status_full,
		319	status_full_ack => status_full_ack,
		320	status_full_err => status_full_err,
		321	status_new_err => status_new_err,
		322	data_shaping_BW => OPEN,
		323	data_shaping_SP0 => OPEN,
		324	data_shaping_SP1 => OPEN,
		325	data_shaping_R0 => OPEN,
		326	data_shaping_R1 => OPEN,
		327	delta_snapshot => OPEN,
		328	delta_f0 => OPEN,
		329	delta_f0_2 => OPEN,
		330	delta_f1 => OPEN,
		331	delta_f2 => OPEN,
		332	nb_data_by_buffer => OPEN,
		333	nb_word_by_buffer => OPEN,
		334	nb_snapshot_param => OPEN,
		335	enable_f0 => OPEN,
		336	enable_f1 => OPEN,
		337	enable_f2 => OPEN,
		338	enable_f3 => OPEN,
		339	burst_f0 => OPEN,
		340	burst_f1 => OPEN,
		341	burst_f2 => OPEN,
		342	run => OPEN,
		343	addr_data_f0 => OPEN,
		344	addr_data_f1 => OPEN,
		345	addr_data_f2 => OPEN,
		346	addr_data_f3 => OPEN,
		347	start_date => OPEN);
		348
		349
		350
		351
		352
		353
		354
		355
		356
		357
258		358
259		359
260		360
261		361
262	PROCESS (clk25MHz, rstn)	362
263	BEGIN -- PROCESS	363
264	IF rstn = '0' THEN -- asynchronous reset (active low)	364	-- PROCESS (clk25MHz, rstn)
265	status_ready_matrix_f0 <= '0';	365	-- BEGIN -- PROCESS
266	-- status_ready_matrix_f0_1 <= '0';	366	-- IF rstn = '0' THEN -- asynchronous reset (active low)
267	status_ready_matrix_f1 <= '0';	367	-- status_ready_matrix_f0 <= '0';
268	status_ready_matrix_f2 <= '0';	368	---- status_ready_matrix_f0_1 <= '0';
269	ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge	369	-- status_ready_matrix_f1 <= '0';
270	status_ready_matrix_f0 <= ~~status_ready_matrix_f0~~ OR ~~ready_matrix_f0~~;	370	-- status_ready_matrix_f2 <= '0';
271	-- status_ready_matrix_f0_1 <= status_ready_matrix_f0_1 OR ready_matrix_f0_1;	371	-- ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
272	status_ready_matrix_f1 <= status_ready_matrix_f1 OR ready_matrix_f1;	372	-- status_ready_matrix_f0 <= status_ready_matrix_f0 OR ready_matrix_f0;
273	status_ready_matrix_f2 <= status_ready_matrix_f2 OR ready_matrix_f2;	373	---- status_ready_matrix_f0_1 <= status_ready_matrix_f0_1 OR ready_matrix_f0_1;
274	END IF;	374	-- status_ready_matrix_f1 <= status_ready_matrix_f1 OR ready_matrix_f1;
275	END PROCESS;	375	-- status_ready_matrix_f2 <= status_ready_matrix_f2 OR ready_matrix_f2;
276		376	-- END IF;
		377	-- END PROCESS;
277		378
278		379
279		380
280	-- status_error_anticipating_empty_fifo <= '0';	381	-- status_error_anticipating_empty_fifo <= '0';
281	-- status_error_bad_component_error <= '0';	382	-- status_error_bad_component_error <= '0';
282		383
283	config_active_interruption_onNewMatrix <= '0';	384	-- config_active_interruption_onNewMatrix <= '0';
284	config_active_interruption_onError <= '0';	385	-- config_active_interruption_onError <= '0';
285	addr_matrix_f0 <= (OTHERS => '0');	386	-- addr_matrix_f0 <= (OTHERS => '0');
286	-- addr_matrix_f0_1 <= (OTHERS => '0');	387	-- addr_matrix_f0_1 <= (OTHERS => '0');
287	addr_matrix_f1 <= (OTHERS => '0');	388	-- addr_matrix_f1 <= (OTHERS => '0');
288	addr_matrix_f2 <= (OTHERS => '0');	389	-- addr_matrix_f2 <= (OTHERS => '0');
289		390
290		391
291	PROCESS (clk25MHz, rstn)	392	PROCESS (clk25MHz, rstn)

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +8 -2

               SIGNAL error_buffer_full         :  STD_LOGIC;
               SIGNAL error_input_fifo_write    :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+              SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
             BEGIN
               sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
                   error_buffer_full                      => error_buffer_full,
                   error_input_fifo_write                 => error_input_fifo_write,
-                  debug_reg                              => observation_reg,
+                  debug_reg                              => debug_ms,--observation_reg,
                   status_ready_matrix_f0                 => status_ready_matrix_f0,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
                   matrix_time_f1                         => matrix_time_f1,
                   matrix_time_f2                         => matrix_time_f2);
+              -----------------------------------------------------------------------------
+              observation_reg(31 DOWNTO 0) <= debug_ms(30 DOWNTO 0) & ms_softandhard_rstn;
             END beh;

lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +22 -30

             USE grlib.devices.ALL;
             LIBRARY lpp;
             USE lpp.lpp_lfr_pkg.ALL;
-            USE lpp.lpp_amba.ALL;
+            --USE lpp.lpp_amba.ALL;
             USE lpp.apb_devices_list.ALL;
             USE lpp.lpp_memory.ALL;
             LIBRARY techmap;
             ARCHITECTURE beh OF lpp_lfr_apbreg IS
               CONSTANT REVISION : INTEGER := 1;
               CONSTANT pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
 => apb_iobar(paddr, pmask));
               TYPE lpp_SpectralMatrix_regs IS RECORD
                 config_active_interruption_onNewMatrix : STD_LOGIC;
                 config_active_interruption_onError     : STD_LOGIC;
                   reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
                   reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
-                  reg_sp.time_matrix_f0_0 <= (OTHERS => '0');  -- ok
+            --      reg_sp.time_matrix_f0_0 <= (OTHERS => '0');  -- ok
-                  reg_sp.time_matrix_f1_0 <= (OTHERS => '0');  -- ok
+            --      reg_sp.time_matrix_f1_0 <= (OTHERS => '0');  -- ok
-                  reg_sp.time_matrix_f2_0 <= (OTHERS => '0');  -- ok
+            --      reg_sp.time_matrix_f2_0 <= (OTHERS => '0');  -- ok
-                  reg_sp.time_matrix_f0_1 <= (OTHERS => '0');  -- ok
+            --      reg_sp.time_matrix_f0_1 <= (OTHERS => '0');  -- ok
-                  reg_sp.time_matrix_f1_1 <= (OTHERS => '0');  -- ok
+                  --reg_sp.time_matrix_f1_1 <= (OTHERS => '0');  -- ok
-                  reg_sp.time_matrix_f2_1 <= (OTHERS => '0');  -- ok
+            --      reg_sp.time_matrix_f2_1 <= (OTHERS => '0');  -- ok
                   prdata <= (OTHERS => '0');
                   reg_wp.start_date        <= (OTHERS => '0');
                 ELSIF HCLK'EVENT AND HCLK = '1' THEN  -- rising clock edge
-                  reg_sp.time_matrix_f0_0 <= reg0_matrix_time_f0;  -- ok
-                  reg_sp.time_matrix_f1_0 <= reg0_matrix_time_f1;  -- ok
-                  reg_sp.time_matrix_f2_0 <= reg0_matrix_time_f2;  -- ok
-                  reg_sp.time_matrix_f0_1 <= reg1_matrix_time_f0;  -- ok
-                  reg_sp.time_matrix_f1_1 <= reg1_matrix_time_f1;  -- ok
-                  reg_sp.time_matrix_f2_1 <= reg1_matrix_time_f2;  -- ok
                   status_full_ack <= (OTHERS => '0');
                   reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
                   reg0_ready_matrix        => reg0_ready_matrix_f0,
-                  reg0_addr_matrix         => reg0_addr_matrix_f0,
+                  reg0_addr_matrix         => reg_sp.addr_matrix_f0_0,--reg0_addr_matrix_f0,
-                  reg0_matrix_time         => reg0_matrix_time_f0,
+                  reg0_matrix_time         => reg_sp.time_matrix_f0_0,--reg0_matrix_time_f0,
                   reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
                   reg1_ready_matrix        => reg1_ready_matrix_f0,
-                  reg1_addr_matrix         => reg1_addr_matrix_f0,
+                  reg1_addr_matrix         => reg_sp.addr_matrix_f0_1,--reg1_addr_matrix_f0,
-                  reg1_matrix_time         => reg1_matrix_time_f0,
+                  reg1_matrix_time         => reg_sp.time_matrix_f0_1,--reg1_matrix_time_f0,
                   ready_matrix              => ready_matrix_f0,
                   status_ready_matrix       => status_ready_matrix_f0,
                   reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
                   reg0_ready_matrix        => reg0_ready_matrix_f1,
-                  reg0_addr_matrix         => reg0_addr_matrix_f1,
+                  reg0_addr_matrix         => reg_sp.addr_matrix_f1_0,--reg0_addr_matrix_f1,
-                  reg0_matrix_time         => reg0_matrix_time_f1,
+                  reg0_matrix_time         => reg_sp.time_matrix_f1_0,--reg0_matrix_time_f1,
                   reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
                   reg1_ready_matrix        => reg1_ready_matrix_f1,
-                  reg1_addr_matrix         => reg1_addr_matrix_f1,
+                  reg1_addr_matrix         => reg_sp.addr_matrix_f1_1,--reg1_addr_matrix_f1,
-                  reg1_matrix_time         => reg1_matrix_time_f1,
+                  reg1_matrix_time         => reg_sp.time_matrix_f1_1,--reg1_matrix_time_f1,
                   ready_matrix              => ready_matrix_f1,
                   status_ready_matrix       => status_ready_matrix_f1,
                   reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
                   reg0_ready_matrix        => reg0_ready_matrix_f2,
-                  reg0_addr_matrix         => reg0_addr_matrix_f2,
+                  reg0_addr_matrix         => reg_sp.addr_matrix_f2_0,--reg0_addr_matrix_f2,
-                  reg0_matrix_time         => reg0_matrix_time_f2,
+                  reg0_matrix_time         => reg_sp.time_matrix_f2_0,--reg0_matrix_time_f2,
                   reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
                   reg1_ready_matrix        => reg1_ready_matrix_f2,
-                  reg1_addr_matrix         => reg1_addr_matrix_f2,
+                  reg1_addr_matrix         => reg_sp.addr_matrix_f2_1,--reg1_addr_matrix_f2,
-                  reg1_matrix_time         => reg1_matrix_time_f2,
+                  reg1_matrix_time         => reg_sp.time_matrix_f2_1,--reg1_matrix_time_f2,
                   ready_matrix              => ready_matrix_f2,
                   status_ready_matrix       => status_ready_matrix_f2,
                   matrix_time               => matrix_time_f2);
-            END beh;
  No newline at end of file
+            END beh;

lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd +13 -1

               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   current_reg <= '0';
+                  reg0_matrix_time <= (OTHERS => '0');
+                  reg1_matrix_time <= (OTHERS => '0');
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF ready_matrix = '1' THEN
                     current_reg <= NOT current_reg;
                   END IF;
+                  IF current_reg = '0' THEN
+                    reg0_matrix_time <= matrix_time;
+                  END IF;
+                  IF current_reg = '1' THEN
+                    reg1_matrix_time <= matrix_time;
+                  END IF;
                 END IF;
               END PROCESS;
               reg0_ready_matrix <= ready_matrix WHEN current_reg = '0' ELSE '0';
               reg1_ready_matrix <= ready_matrix WHEN current_reg = '1' ELSE '0';
-            END beh;
  No newline at end of file
+            END beh;

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