# HG changeset patch # User pellion # Date 2014-06-02 10:29:58 # Node ID 8b7232d194b40857413e8ddf100c0f78624f75e4 # Parent c3da3d61f364706a4080a0d7daed48f0057dee5a update APB_REG diff --git a/designs/Validation_LFR_SpectralMatrix/Makefile b/designs/Validation_LFR_SpectralMatrix/Makefile --- a/designs/Validation_LFR_SpectralMatrix/Makefile +++ b/designs/Validation_LFR_SpectralMatrix/Makefile @@ -393,8 +393,11 @@ vcom_lpp: $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd diff --git a/designs/Validation_LFR_SpectralMatrix/TB.vhd b/designs/Validation_LFR_SpectralMatrix/TB.vhd --- a/designs/Validation_LFR_SpectralMatrix/TB.vhd +++ b/designs/Validation_LFR_SpectralMatrix/TB.vhd @@ -32,6 +32,12 @@ USE lpp.spectral_matrix_package.ALL; use lpp.lpp_fft.all; use lpp.fft_components.all; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + ENTITY TB IS @@ -103,6 +109,15 @@ ARCHITECTURE beh OF TB IS ----------------------------------------------------------------------------- SIGNAL ren_counter : INTEGER; + SIGNAL error_buffer_full : STD_LOGIC; + SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL apbi : apb_slv_in_type; + SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + BEGIN -- beh clk25MHz <= NOT clk25MHz AFTER 20 ns; @@ -234,8 +249,8 @@ BEGIN -- beh ready_matrix_f2 => ready_matrix_f2, -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, error_bad_component_error => error_bad_component_error, - error_buffer_full => OPEN, - error_input_fifo_write => OPEN, + error_buffer_full => error_buffer_full, + error_input_fifo_write => error_input_fifo_write, debug_reg => debug_reg, status_ready_matrix_f0 => status_ready_matrix_f0, @@ -255,37 +270,123 @@ BEGIN -- beh matrix_time_f1 => matrix_time_f1, matrix_time_f2 => matrix_time_f2); + + + + lpp_lfr_apbreg_1 : lpp_lfr_apbreg + GENERIC MAP ( + nb_data_by_buffer_size => 11, + nb_word_by_buffer_size => 11, + nb_snapshot_param_size => 11, + delta_vector_size => 20, + delta_vector_size_f0_2 => 7, + pindex => 4, + paddr => 4, + pmask => 16#fff#, + pirq_ms => 0, + pirq_wfp => 1, + top_lfr_version => (OTHERS => '0') + ) + PORT MAP ( + HCLK => clk25MHz, + HRESETn => rstn, + apbi => apbi, + apbo => OPEN, + + run_ms => OPEN, + + ready_matrix_f0 => ready_matrix_f0, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_bad_component_error => error_bad_component_error, + error_buffer_full => error_buffer_full, -- TODO + error_input_fifo_write => error_input_fifo_write, -- TODO + status_ready_matrix_f0 => status_ready_matrix_f0, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + + matrix_time_f0 => matrix_time_f0, + matrix_time_f1 => matrix_time_f1, + matrix_time_f2 => matrix_time_f2, + + addr_matrix_f0 => addr_matrix_f0, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2, + ------------------------------------------------------------------------- + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + status_new_err => status_new_err, + data_shaping_BW => OPEN, + data_shaping_SP0 => OPEN, + data_shaping_SP1 => OPEN, + data_shaping_R0 => OPEN, + data_shaping_R1 => OPEN, + delta_snapshot => OPEN, + delta_f0 => OPEN, + delta_f0_2 => OPEN, + delta_f1 => OPEN, + delta_f2 => OPEN, + nb_data_by_buffer => OPEN, + nb_word_by_buffer => OPEN, + nb_snapshot_param => OPEN, + enable_f0 => OPEN, + enable_f1 => OPEN, + enable_f2 => OPEN, + enable_f3 => OPEN, + burst_f0 => OPEN, + burst_f1 => OPEN, + burst_f2 => OPEN, + run => OPEN, + addr_data_f0 => OPEN, + addr_data_f1 => OPEN, + addr_data_f2 => OPEN, + addr_data_f3 => OPEN, + start_date => OPEN); + + + + + + + + + + - PROCESS (clk25MHz, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - status_ready_matrix_f0 <= '0'; --- status_ready_matrix_f0_1 <= '0'; - status_ready_matrix_f1 <= '0'; - status_ready_matrix_f2 <= '0'; - ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge - status_ready_matrix_f0 <= status_ready_matrix_f0 OR ready_matrix_f0; --- status_ready_matrix_f0_1 <= status_ready_matrix_f0_1 OR ready_matrix_f0_1; - status_ready_matrix_f1 <= status_ready_matrix_f1 OR ready_matrix_f1; - status_ready_matrix_f2 <= status_ready_matrix_f2 OR ready_matrix_f2; - END IF; - END PROCESS; - + + +-- PROCESS (clk25MHz, rstn) +-- BEGIN -- PROCESS +-- IF rstn = '0' THEN -- asynchronous reset (active low) +-- status_ready_matrix_f0 <= '0'; +---- status_ready_matrix_f0_1 <= '0'; +-- status_ready_matrix_f1 <= '0'; +-- status_ready_matrix_f2 <= '0'; +-- ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge +-- status_ready_matrix_f0 <= status_ready_matrix_f0 OR ready_matrix_f0; +---- status_ready_matrix_f0_1 <= status_ready_matrix_f0_1 OR ready_matrix_f0_1; +-- status_ready_matrix_f1 <= status_ready_matrix_f1 OR ready_matrix_f1; +-- status_ready_matrix_f2 <= status_ready_matrix_f2 OR ready_matrix_f2; +-- END IF; +-- END PROCESS; -- status_error_anticipating_empty_fifo <= '0'; -- status_error_bad_component_error <= '0'; - config_active_interruption_onNewMatrix <= '0'; - config_active_interruption_onError <= '0'; - addr_matrix_f0 <= (OTHERS => '0'); +-- config_active_interruption_onNewMatrix <= '0'; +-- config_active_interruption_onError <= '0'; +-- addr_matrix_f0 <= (OTHERS => '0'); -- addr_matrix_f0_1 <= (OTHERS => '0'); - addr_matrix_f1 <= (OTHERS => '0'); - addr_matrix_f2 <= (OTHERS => '0'); +-- addr_matrix_f1 <= (OTHERS => '0'); +-- addr_matrix_f2 <= (OTHERS => '0'); PROCESS (clk25MHz, rstn) diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -281,7 +281,9 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL error_buffer_full : STD_LOGIC; SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); - + + SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0); + BEGIN sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); @@ -698,7 +700,7 @@ BEGIN error_buffer_full => error_buffer_full, error_input_fifo_write => error_input_fifo_write, - debug_reg => observation_reg, + debug_reg => debug_ms,--observation_reg, status_ready_matrix_f0 => status_ready_matrix_f0, status_ready_matrix_f1 => status_ready_matrix_f1, @@ -713,4 +715,8 @@ BEGIN matrix_time_f1 => matrix_time_f1, matrix_time_f2 => matrix_time_f2); + ----------------------------------------------------------------------------- + observation_reg(31 DOWNTO 0) <= debug_ms(30 DOWNTO 0) & ms_softandhard_rstn; + + END beh; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -29,7 +29,7 @@ USE grlib.stdlib.ALL; USE grlib.devices.ALL; LIBRARY lpp; USE lpp.lpp_lfr_pkg.ALL; -USE lpp.lpp_amba.ALL; +--USE lpp.lpp_amba.ALL; USE lpp.apb_devices_list.ALL; USE lpp.lpp_memory.ALL; LIBRARY techmap; @@ -136,11 +136,11 @@ END lpp_lfr_apbreg; ARCHITECTURE beh OF lpp_lfr_apbreg IS CONSTANT REVISION : INTEGER := 1; - + CONSTANT pconfig : apb_config_type := ( 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), 1 => apb_iobar(paddr, pmask)); - + TYPE lpp_SpectralMatrix_regs IS RECORD config_active_interruption_onNewMatrix : STD_LOGIC; config_active_interruption_onError : STD_LOGIC; @@ -316,13 +316,13 @@ BEGIN -- beh reg_sp.addr_matrix_f1_1 <= (OTHERS => '0'); reg_sp.addr_matrix_f2_1 <= (OTHERS => '0'); - reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok - reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok - reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok +-- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok +-- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok +-- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok - reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok - reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok - reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok +-- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok + --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok +-- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok prdata <= (OTHERS => '0'); @@ -360,14 +360,6 @@ BEGIN -- beh reg_wp.start_date <= (OTHERS => '0'); ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge - - reg_sp.time_matrix_f0_0 <= reg0_matrix_time_f0; -- ok - reg_sp.time_matrix_f1_0 <= reg0_matrix_time_f1; -- ok - reg_sp.time_matrix_f2_0 <= reg0_matrix_time_f2; -- ok - - reg_sp.time_matrix_f0_1 <= reg1_matrix_time_f0; -- ok - reg_sp.time_matrix_f1_1 <= reg1_matrix_time_f1; -- ok - reg_sp.time_matrix_f2_1 <= reg1_matrix_time_f2; -- ok status_full_ack <= (OTHERS => '0'); @@ -626,13 +618,13 @@ BEGIN -- beh reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0, reg0_ready_matrix => reg0_ready_matrix_f0, - reg0_addr_matrix => reg0_addr_matrix_f0, - reg0_matrix_time => reg0_matrix_time_f0, + reg0_addr_matrix => reg_sp.addr_matrix_f0_0,--reg0_addr_matrix_f0, + reg0_matrix_time => reg_sp.time_matrix_f0_0,--reg0_matrix_time_f0, reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1, reg1_ready_matrix => reg1_ready_matrix_f0, - reg1_addr_matrix => reg1_addr_matrix_f0, - reg1_matrix_time => reg1_matrix_time_f0, + reg1_addr_matrix => reg_sp.addr_matrix_f0_1,--reg1_addr_matrix_f0, + reg1_matrix_time => reg_sp.time_matrix_f0_1,--reg1_matrix_time_f0, ready_matrix => ready_matrix_f0, status_ready_matrix => status_ready_matrix_f0, @@ -646,13 +638,13 @@ BEGIN -- beh reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, reg0_ready_matrix => reg0_ready_matrix_f1, - reg0_addr_matrix => reg0_addr_matrix_f1, - reg0_matrix_time => reg0_matrix_time_f1, + reg0_addr_matrix => reg_sp.addr_matrix_f1_0,--reg0_addr_matrix_f1, + reg0_matrix_time => reg_sp.time_matrix_f1_0,--reg0_matrix_time_f1, reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1, reg1_ready_matrix => reg1_ready_matrix_f1, - reg1_addr_matrix => reg1_addr_matrix_f1, - reg1_matrix_time => reg1_matrix_time_f1, + reg1_addr_matrix => reg_sp.addr_matrix_f1_1,--reg1_addr_matrix_f1, + reg1_matrix_time => reg_sp.time_matrix_f1_1,--reg1_matrix_time_f1, ready_matrix => ready_matrix_f1, status_ready_matrix => status_ready_matrix_f1, @@ -666,13 +658,13 @@ BEGIN -- beh reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, reg0_ready_matrix => reg0_ready_matrix_f2, - reg0_addr_matrix => reg0_addr_matrix_f2, - reg0_matrix_time => reg0_matrix_time_f2, + reg0_addr_matrix => reg_sp.addr_matrix_f2_0,--reg0_addr_matrix_f2, + reg0_matrix_time => reg_sp.time_matrix_f2_0,--reg0_matrix_time_f2, reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1, reg1_ready_matrix => reg1_ready_matrix_f2, - reg1_addr_matrix => reg1_addr_matrix_f2, - reg1_matrix_time => reg1_matrix_time_f2, + reg1_addr_matrix => reg_sp.addr_matrix_f2_1,--reg1_addr_matrix_f2, + reg1_matrix_time => reg_sp.time_matrix_f2_1,--reg1_matrix_time_f2, ready_matrix => ready_matrix_f2, status_ready_matrix => status_ready_matrix_f2, @@ -680,4 +672,4 @@ BEGIN -- beh matrix_time => matrix_time_f2); -END beh; \ No newline at end of file +END beh; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd @@ -61,11 +61,20 @@ BEGIN -- beh BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) current_reg <= '0'; + reg0_matrix_time <= (OTHERS => '0'); + reg1_matrix_time <= (OTHERS => '0'); ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge IF ready_matrix = '1' THEN current_reg <= NOT current_reg; END IF; + IF current_reg = '0' THEN + reg0_matrix_time <= matrix_time; + END IF; + IF current_reg = '1' THEN + reg1_matrix_time <= matrix_time; + END IF; + END IF; END PROCESS; @@ -78,4 +87,7 @@ BEGIN -- beh reg0_ready_matrix <= ready_matrix WHEN current_reg = '0' ELSE '0'; reg1_ready_matrix <= ready_matrix WHEN current_reg = '1' ELSE '0'; -END beh; \ No newline at end of file + + + +END beh;