@@ -58,7 +58,7 set_io {data[31]} -pinname 214 -fixed y | |||
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58 | 58 | set_io nSRAM_MBE -pinname 9 -fixed yes -DIRECTION Inout |
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59 | 59 | set_io nSRAM_E1 -pinname 20 -fixed yes -DIRECTION Inout |
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60 | 60 | set_io nSRAM_E2 -pinname 15 -fixed yes -DIRECTION Inout |
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61 | set_io nSRAM_SCRUB -pinname 14 -fixed yes -DIRECTION Inout | |
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61 | #set_io nSRAM_SCRUB -pinname 14 -fixed yes -DIRECTION Inout | |
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62 | 62 | set_io nSRAM_W -pinname 8 -fixed yes -DIRECTION Inout |
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63 | 63 | set_io nSRAM_G -pinname 21 -fixed yes -DIRECTION Inout |
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64 | 64 | set_io nSRAM_BUSY -pinname 24 -fixed yes -DIRECTION Inout |
@@ -75,15 +75,15 set_io spw2_sin -pinname 304 -fixed yes | |||
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75 | 75 | set_io spw2_dout -pinname 335 -fixed yes -DIRECTION Inout |
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76 | 76 | set_io spw2_sout -pinname 330 -fixed yes -DIRECTION Inout |
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77 | 77 | |
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78 | set_io TAG1 -pinname 195 -fixed yes -DIRECTION Inout | |
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79 | set_io TAG2 -pinname 190 -fixed yes -DIRECTION Inout | |
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80 | set_io TAG3 -pinname 189 -fixed yes -DIRECTION Inout | |
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81 | set_io TAG4 -pinname 188 -fixed yes -DIRECTION Inout | |
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82 | #set_io TAG5 -pinname 187 -fixed yes -DIRECTION Inout | |
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83 | #set_io TAG6 -pinname 184 -fixed yes -DIRECTION Inout | |
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84 | #set_io TAG7 -pinname 200 -fixed yes -DIRECTION Inout | |
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85 | set_io TAG8 -pinname 199 -fixed yes -DIRECTION Inout | |
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86 | #set_io TAG9 -pinname 196 -fixed yes -DIRECTION Inout | |
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78 | set_io {TAG[1]} -pinname 195 -fixed yes -DIRECTION Inout | |
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79 | #set_io {TAG[2]} -pinname 190 -fixed yes -DIRECTION Inout | |
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80 | set_io {TAG[3]} -pinname 189 -fixed yes -DIRECTION Inout | |
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81 | #set_io {TAG[4]} -pinname 188 -fixed yes -DIRECTION Inout | |
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82 | #set_io {TAG[5]} -pinname 187 -fixed yes -DIRECTION Inout | |
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83 | #set_io {TAG[6]} -pinname 184 -fixed yes -DIRECTION Inout | |
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84 | #set_io {TAG[7]} -pinname 200 -fixed yes -DIRECTION Inout | |
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85 | #set_io {TAG[8]} -pinname 199 -fixed yes -DIRECTION Inout | |
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86 | #set_io {TAG[9]} -pinname 196 -fixed yes -DIRECTION Inout | |
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87 | 87 | |
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88 | 88 | set_io bias_fail_sw -pinname 342 -fixed yes -DIRECTION Inout |
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89 | 89 |
@@ -1,6 +1,6 | |||
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1 | 1 | # Synopsys, Inc. constraint file |
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2 | # E:\opt\tortoiseHG_vhdlib\boards\LFR-EQM\LFR_EQM_altran_syn.sdc | |
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3 |
# Written on Fri Jun |
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2 | # E:/opt/tortoiseHG_vhdlib/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_5/../../../boards/LFR-EQM/LFR_EQM_altran_syn_fanout.sdc | |
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3 | # Written on Fri Jun 26 12:55:35 2015 | |
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4 | 4 | # by Synplify Pro, E-2010.09A-1 Scope Editor |
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5 | 5 | |
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6 | 6 | # |
@@ -10,12 +10,12 | |||
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10 | 10 | # |
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11 | 11 | # Clocks |
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12 | 12 | # |
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13 | define_clock {clk50MHz} -freq 50 -clockgroup default_clkgroup_0 | |
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14 | define_clock {n:clk_25} -freq 25 -clockgroup default_clkgroup_1 | |
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15 | define_clock {n:clk_24} -freq 24.576 -clockgroup default_clkgroup_2 | |
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16 | define_clock {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_3 | |
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17 | define_clock {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_4 | |
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18 | define_clock {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_5 | |
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13 | define_clock {clk50MHz} -name {clk50MHz} -freq 50 -clockgroup default_clkgroup_0 | |
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14 | define_clock {n:clk_25} -name {n:clk_25} -freq 25 -clockgroup default_clkgroup_1 | |
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15 | define_clock {n:clk_24} -name {n:clk_24} -freq 24.576 -clockgroup default_clkgroup_2 | |
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16 | define_clock {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -name {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_3 | |
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17 | define_clock {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -name {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_4 | |
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18 | define_clock {clk49_152MHz} -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_5 | |
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19 | 19 | |
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20 | 20 | # |
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21 | 21 | # Clock to Clock |
@@ -36,24 +36,21 define_clock {clk49_152MHz} -freq 49. | |||
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36 | 36 | # |
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37 | 37 | # Attributes |
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38 | 38 | # |
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39 |
define_global_attribute syn_useioff |
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40 |
define_attribute |
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41 |
define_attribute |
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42 |
define_attribute |
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43 |
define_attribute |
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44 |
define_global_attribute -disable |
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45 | ||
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46 | ||
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39 | define_global_attribute {syn_useioff} {1} | |
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40 | define_attribute {n:leon3_soc_1\.l3\.cpu.0.leon3_radhard_i.cpu.holdn} {syn_maxfan} {10000} | |
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41 | define_attribute {n:spw_inputloop\.0\.spw_phy0.rxclki_1} {syn_maxfan} {10000} | |
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42 | define_attribute {n:spw_inputloop\.1\.spw_phy0.rxclki_1} {syn_maxfan} {10000} | |
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43 | define_attribute {n:leon3_soc_1\.l3\.cpu.0.leon3_radhard_i.cpu} {syn_hier} {flatten} | |
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44 | define_global_attribute -disable {syn_netlist_hierarchy} {1} | |
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47 | 45 | |
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48 | 46 | # |
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49 | 47 | # I/O Standards |
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50 | 48 | # |
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51 | 49 | |
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52 | ||
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53 | 50 | # |
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54 | 51 | # Compile Points |
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55 | 52 | # |
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56 | 53 | |
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57 | 54 | # |
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58 | 55 | # Other |
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59 | # No newline at end of file | |
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56 | # |
@@ -124,6 +124,7 ARCHITECTURE beh OF TB IS | |||
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124 | 124 | --SIGNAL TAG4 : STD_ULOGIC; |
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125 | 125 | SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0); |
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126 | 126 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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127 | SIGNAL data_ram : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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127 | 128 | SIGNAL nSRAM_MBE : STD_LOGIC; |
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128 | 129 | SIGNAL nSRAM_E1 : STD_LOGIC; |
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129 | 130 | SIGNAL nSRAM_E2 : STD_LOGIC; |
@@ -316,8 +316,8 BEGIN -- beh | |||
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316 | 316 | ENABLE_FPU => 1, |
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317 | 317 | FPU_NETLIST => 0, |
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318 | 318 | ENABLE_DSU => 1, |
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319 |
ENABLE_AHB_UART => |
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320 |
ENABLE_APB_UART => |
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319 | ENABLE_AHB_UART => 0, | |
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320 | ENABLE_APB_UART => 0, | |
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321 | 321 | ENABLE_IRQMP => 1, |
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322 | 322 | ENABLE_GPT => 1, |
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323 | 323 | NB_AHB_MASTER => NB_AHB_MASTER, |
@@ -514,7 +514,7 BEGIN -- beh | |||
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514 | 514 | pirq_ms => 6, |
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515 | 515 | pirq_wfp => 14, |
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516 | 516 | hindex => 2, |
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517 |
top_lfr_version => X"00014 |
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517 | top_lfr_version => X"000154") -- aa.bb.cc version | |
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518 | 518 | PORT MAP ( |
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519 | 519 | clk => clk_25, |
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520 | 520 | rstn => LFR_rstn, |
@@ -122,38 +122,26 BEGIN | |||
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122 | 122 | PROCESS (clk, rstn) |
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123 | 123 | BEGIN -- PROCESS |
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124 | 124 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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125 | state <= DESYNC; | |
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125 | state <= DESYNC; | |
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126 | set_TCU <= '0'; | |
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126 | 127 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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127 | --CT_add1 <= '0'; | |
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128 | 128 | set_TCU <= '0'; |
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129 | 129 | CASE state IS |
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130 | 130 | WHEN DESYNC => |
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131 | 131 | IF tick = '1' THEN |
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132 | 132 | state <= SYNC; |
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133 | 133 | set_TCU <= new_coarsetime_reg; |
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134 | --IF new_coarsetime = '0' AND FT_half = '1' THEN | |
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135 | -- CT_add1 <= '1'; | |
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136 | --END IF; | |
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137 | --ELSIF FT_max = '1' THEN | |
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138 | -- CT_add1 <= '1'; | |
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139 | 134 | END IF; |
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140 | 135 | WHEN TRANSITION => |
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141 | 136 | IF tick = '1' THEN |
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142 | 137 | state <= SYNC; |
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143 | 138 | set_TCU <= new_coarsetime_reg; |
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144 | --IF new_coarsetime = '0' THEN | |
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145 | -- CT_add1 <= '1'; | |
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146 | --END IF; | |
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147 | 139 | ELSIF FT_wait = '1' THEN |
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148 | --CT_add1 <= '1'; | |
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149 | 140 | state <= DESYNC; |
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150 | 141 | END IF; |
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151 | 142 | WHEN SYNC => |
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152 | 143 | IF tick = '1' THEN |
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153 | 144 | set_TCU <= new_coarsetime_reg; |
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154 | --IF new_coarsetime = '0' THEN | |
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155 | -- CT_add1 <= '1'; | |
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156 | --END IF; | |
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157 | 145 | ELSIF FT_max = '1' THEN |
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158 | 146 | state <= TRANSITION; |
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159 | 147 | END IF; |
@@ -42,11 +42,13 ENTITY SPI_DAC_DRIVER IS | |||
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42 | 42 | END ENTITY SPI_DAC_DRIVER; |
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43 | 43 | |
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44 | 44 | ARCHITECTURE behav OF SPI_DAC_DRIVER IS |
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45 |
SIGNAL SHIFTREG |
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46 |
SIGNAL INPUTREG |
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47 |
SIGNAL SMP_CLK_R |
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48 |
SIGNAL shiftcnt |
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49 |
SIGNAL shifting |
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45 | SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0'); | |
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46 | SIGNAL INPUTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0'); | |
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47 | SIGNAL SMP_CLK_R : STD_LOGIC := '0'; | |
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48 | SIGNAL shiftcnt : INTEGER := 0; | |
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49 | SIGNAL shifting : STD_LOGIC := '0'; | |
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50 | ||
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51 | SIGNAL SCLK_s : STD_LOGIC; | |
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50 | 52 | BEGIN |
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51 | 53 | |
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52 | 54 | |
@@ -58,7 +60,16 BEGIN | |||
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58 | 60 | INPUTREG(datawidth-1 DOWNTO 0) <= DATA(0 TO datawidth-1); |
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59 | 61 | END GENERATE; |
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60 | 62 | |
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61 | SCLK <= clk; | |
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63 | PROCESS (clk, rstn) | |
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64 | BEGIN -- PROCESS | |
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65 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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66 | SCLK_s <= '0'; | |
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67 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
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68 | SCLK_s <= NOT SCLK_s; | |
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69 | ||
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70 | END IF; | |
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71 | END PROCESS; | |
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72 | SCLK <= SCLK_s; | |
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62 | 73 | |
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63 | 74 | PROCESS(clk, rstn) |
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64 | 75 | BEGIN |
@@ -140,21 +140,6 ARCHITECTURE beh OF lpp_lfr IS | |||
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140 | 140 | ----------------------------------------------------------------------------- |
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141 | 141 | -- |
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142 | 142 | ----------------------------------------------------------------------------- |
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143 | -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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144 | -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC; | |
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145 | -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; | |
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146 | --f1 | |
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147 | -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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148 | -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC; | |
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149 | -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; | |
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150 | --f2 | |
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151 | -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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152 | -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC; | |
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153 | -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; | |
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154 | --f3 | |
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155 | -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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156 | -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC; | |
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157 | -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; | |
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158 | 143 | |
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159 | 144 | SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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160 | 145 | SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
@@ -162,57 +147,8 ARCHITECTURE beh OF lpp_lfr IS | |||
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162 | 147 | SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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163 | 148 | SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
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164 | 149 | SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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165 | ----------------------------------------------------------------------------- | |
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166 | -- DMA RR | |
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167 | ----------------------------------------------------------------------------- | |
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168 | -- SIGNAL dma_sel_valid : STD_LOGIC; | |
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169 | -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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170 | -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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171 | -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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172 | -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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173 | ||
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174 | -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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175 | -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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176 | ||
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177 | ----------------------------------------------------------------------------- | |
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178 | -- DMA_REG | |
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179 | ----------------------------------------------------------------------------- | |
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180 | -- SIGNAL ongoing_reg : STD_LOGIC; | |
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181 | -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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182 | -- SIGNAL dma_send_reg : STD_LOGIC; | |
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183 | -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
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184 | -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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185 | -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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186 | ||
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187 | ||
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188 | ----------------------------------------------------------------------------- | |
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189 | -- DMA | |
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190 | ----------------------------------------------------------------------------- | |
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191 | -- SIGNAL dma_send : STD_LOGIC; | |
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192 | -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
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193 | -- SIGNAL dma_done : STD_LOGIC; | |
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194 | -- SIGNAL dma_ren : STD_LOGIC; | |
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195 | -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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196 | -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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197 | -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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198 | ||
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199 | ----------------------------------------------------------------------------- | |
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200 | -- MS | |
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201 | ----------------------------------------------------------------------------- | |
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202 | ||
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203 | -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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204 | -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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205 | -- SIGNAL data_ms_valid : STD_LOGIC; | |
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206 | -- SIGNAL data_ms_valid_burst : STD_LOGIC; | |
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207 | -- SIGNAL data_ms_ren : STD_LOGIC; | |
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208 | -- SIGNAL data_ms_done : STD_LOGIC; | |
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209 | -- SIGNAL dma_ms_ongoing : STD_LOGIC; | |
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210 | ||
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211 | -- SIGNAL run_ms : STD_LOGIC; | |
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212 | -- SIGNAL ms_softandhard_rstn : STD_LOGIC; | |
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213 | 150 | |
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214 | 151 | SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
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215 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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216 | 152 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
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217 | 153 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
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218 | 154 | |
@@ -220,9 +156,6 ARCHITECTURE beh OF lpp_lfr IS | |||
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220 | 156 | SIGNAL error_buffer_full : STD_LOGIC; |
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221 | 157 | SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); |
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222 | 158 | |
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223 | -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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224 | -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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225 | ||
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226 | 159 | ----------------------------------------------------------------------------- |
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227 | 160 | SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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228 | 161 | SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
@@ -247,17 +180,12 ARCHITECTURE beh OF lpp_lfr IS | |||
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247 | 180 | |
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248 | 181 | BEGIN |
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249 | 182 | |
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250 | --apb_reg_debug_vector; | |
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251 | 183 | ----------------------------------------------------------------------------- |
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252 | 184 | |
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253 | 185 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
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254 | 186 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
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255 | 187 | sample_time <= coarse_time & fine_time; |
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256 | 188 | |
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257 | --all_channel : FOR i IN 7 DOWNTO 0 GENERATE | |
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258 | -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); | |
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259 | --END GENERATE all_channel; | |
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260 | ||
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261 | 189 |
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262 | 190 | lpp_lfr_filter_1 : lpp_lfr_filter |
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263 | 191 | GENERIC MAP ( |
@@ -291,7 +219,6 BEGIN | |||
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291 | 219 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
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292 | 220 | GENERIC MAP ( |
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293 | 221 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
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294 | -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO | |
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295 | 222 | nb_snapshot_param_size => nb_snapshot_param_size, |
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296 | 223 | delta_vector_size => delta_vector_size, |
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297 | 224 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
@@ -312,8 +239,8 BEGIN | |||
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312 | 239 | ready_matrix_f0 => ready_matrix_f0, |
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313 | 240 | ready_matrix_f1 => ready_matrix_f1, |
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314 | 241 | ready_matrix_f2 => ready_matrix_f2, |
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315 |
error_buffer_full => error_buffer_full, |
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316 |
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242 | error_buffer_full => error_buffer_full, | |
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243 | error_input_fifo_write => error_input_fifo_write, | |
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317 | 244 |
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318 | 245 | status_ready_matrix_f1 => status_ready_matrix_f1, |
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319 | 246 | status_ready_matrix_f2 => status_ready_matrix_f2, |
@@ -329,10 +256,6 BEGIN | |||
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329 | 256 | length_matrix_f0 => length_matrix_f0, |
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330 | 257 | length_matrix_f1 => length_matrix_f1, |
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331 | 258 | length_matrix_f2 => length_matrix_f2, |
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332 | ------------------------------------------------------------------------- | |
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333 | --status_full => status_full, -- TODo | |
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334 | --status_full_ack => status_full_ack, -- TODo | |
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335 | --status_full_err => status_full_err, -- TODo | |
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336 | 259 | status_new_err => status_new_err, |
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337 | 260 | data_shaping_BW => data_shaping_BW, |
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338 | 261 | data_shaping_SP0 => data_shaping_SP0, |
@@ -346,7 +269,6 BEGIN | |||
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346 | 269 | delta_f1 => delta_f1, |
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347 | 270 | delta_f2 => delta_f2, |
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348 | 271 | nb_data_by_buffer => nb_data_by_buffer, |
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349 | -- nb_word_by_buffer => nb_word_by_buffer, -- TODO | |
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350 | 272 | nb_snapshot_param => nb_snapshot_param, |
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351 | 273 | enable_f0 => enable_f0, |
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352 | 274 | enable_f1 => enable_f1, |
@@ -355,16 +277,15 BEGIN | |||
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355 | 277 | burst_f0 => burst_f0, |
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356 | 278 | burst_f1 => burst_f1, |
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357 | 279 | burst_f2 => burst_f2, |
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358 |
run => OPEN, |
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280 | run => OPEN, | |
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359 | 281 | start_date => start_date, |
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360 | -- debug_signal => debug_signal, | |
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361 |
wfp_ |
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362 |
wfp_ |
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363 | wfp_length_buffer => wfp_length_buffer,-- TODO | |
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282 | wfp_status_buffer_ready => wfp_status_buffer_ready, | |
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283 | wfp_addr_buffer => wfp_addr_buffer, | |
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284 | wfp_length_buffer => wfp_length_buffer, | |
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364 | 285 | |
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365 |
wfp_ready_buffer => wfp_ready_buffer, |
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366 |
wfp_buffer_time => wfp_buffer_time, |
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367 |
wfp_error_buffer_full => wfp_error_buffer_full, |
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286 | wfp_ready_buffer => wfp_ready_buffer, | |
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287 | wfp_buffer_time => wfp_buffer_time, | |
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288 | wfp_error_buffer_full => wfp_error_buffer_full, | |
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368 | 289 | ------------------------------------------------------------------------- |
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369 | 290 | sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16), |
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370 | 291 | sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16), |
@@ -462,17 +383,12 BEGIN | |||
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462 | 383 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
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463 | 384 | sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16)); |
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464 | 385 | |
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465 | ------------------------------------------------------------------------------- | |
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466 | ||
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467 | --ms_softandhard_rstn <= rstn AND run_ms AND run; | |
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468 | ||
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469 | 386 | ----------------------------------------------------------------------------- |
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470 | 387 | lpp_lfr_ms_1 : lpp_lfr_ms |
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471 | 388 | GENERIC MAP ( |
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472 | 389 | Mem_use => Mem_use) |
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473 | 390 | PORT MAP ( |
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474 | 391 | clk => clk, |
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475 | --rstn => ms_softandhard_rstn, --rstn, | |
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476 | 392 | rstn => rstn, |
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477 | 393 | |
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478 | 394 | run => '1',--run_ms, |
@@ -596,4 +512,4 BEGIN | |||
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596 | 512 | END GENERATE all_channel_sim; |
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597 | 513 | ----------------------------------------------------------------------------- |
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598 | 514 | |
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599 | END beh; No newline at end of file | |
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515 | END beh; |
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