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Mini LFR - 0.1.84
pellion -
r617:7ac14cef3eb0 simu_with_Leon3
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@@ -58,7 +58,7 set_io {data[31]} -pinname 214 -fixed y
58 set_io nSRAM_MBE -pinname 9 -fixed yes -DIRECTION Inout
58 set_io nSRAM_MBE -pinname 9 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E1 -pinname 20 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E1 -pinname 20 -fixed yes -DIRECTION Inout
60 set_io nSRAM_E2 -pinname 15 -fixed yes -DIRECTION Inout
60 set_io nSRAM_E2 -pinname 15 -fixed yes -DIRECTION Inout
61 set_io nSRAM_SCRUB -pinname 14 -fixed yes -DIRECTION Inout
61 #set_io nSRAM_SCRUB -pinname 14 -fixed yes -DIRECTION Inout
62 set_io nSRAM_W -pinname 8 -fixed yes -DIRECTION Inout
62 set_io nSRAM_W -pinname 8 -fixed yes -DIRECTION Inout
63 set_io nSRAM_G -pinname 21 -fixed yes -DIRECTION Inout
63 set_io nSRAM_G -pinname 21 -fixed yes -DIRECTION Inout
64 set_io nSRAM_BUSY -pinname 24 -fixed yes -DIRECTION Inout
64 set_io nSRAM_BUSY -pinname 24 -fixed yes -DIRECTION Inout
@@ -75,15 +75,15 set_io spw2_sin -pinname 304 -fixed yes
75 set_io spw2_dout -pinname 335 -fixed yes -DIRECTION Inout
75 set_io spw2_dout -pinname 335 -fixed yes -DIRECTION Inout
76 set_io spw2_sout -pinname 330 -fixed yes -DIRECTION Inout
76 set_io spw2_sout -pinname 330 -fixed yes -DIRECTION Inout
77
77
78 set_io TAG1 -pinname 195 -fixed yes -DIRECTION Inout
78 set_io {TAG[1]} -pinname 195 -fixed yes -DIRECTION Inout
79 set_io TAG2 -pinname 190 -fixed yes -DIRECTION Inout
79 #set_io {TAG[2]} -pinname 190 -fixed yes -DIRECTION Inout
80 set_io TAG3 -pinname 189 -fixed yes -DIRECTION Inout
80 set_io {TAG[3]} -pinname 189 -fixed yes -DIRECTION Inout
81 set_io TAG4 -pinname 188 -fixed yes -DIRECTION Inout
81 #set_io {TAG[4]} -pinname 188 -fixed yes -DIRECTION Inout
82 #set_io TAG5 -pinname 187 -fixed yes -DIRECTION Inout
82 #set_io {TAG[5]} -pinname 187 -fixed yes -DIRECTION Inout
83 #set_io TAG6 -pinname 184 -fixed yes -DIRECTION Inout
83 #set_io {TAG[6]} -pinname 184 -fixed yes -DIRECTION Inout
84 #set_io TAG7 -pinname 200 -fixed yes -DIRECTION Inout
84 #set_io {TAG[7]} -pinname 200 -fixed yes -DIRECTION Inout
85 set_io TAG8 -pinname 199 -fixed yes -DIRECTION Inout
85 #set_io {TAG[8]} -pinname 199 -fixed yes -DIRECTION Inout
86 #set_io TAG9 -pinname 196 -fixed yes -DIRECTION Inout
86 #set_io {TAG[9]} -pinname 196 -fixed yes -DIRECTION Inout
87
87
88 set_io bias_fail_sw -pinname 342 -fixed yes -DIRECTION Inout
88 set_io bias_fail_sw -pinname 342 -fixed yes -DIRECTION Inout
89
89
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@@ -1,6 +1,6
1 # Synopsys, Inc. constraint file
1 # Synopsys, Inc. constraint file
2 # E:\opt\tortoiseHG_vhdlib\boards\LFR-EQM\LFR_EQM_altran_syn.sdc
2 # E:/opt/tortoiseHG_vhdlib/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_5/../../../boards/LFR-EQM/LFR_EQM_altran_syn_fanout.sdc
3 # Written on Fri Jun 12 10:24:30 2015
3 # Written on Fri Jun 26 12:55:35 2015
4 # by Synplify Pro, E-2010.09A-1 Scope Editor
4 # by Synplify Pro, E-2010.09A-1 Scope Editor
5
5
6 #
6 #
@@ -10,12 +10,12
10 #
10 #
11 # Clocks
11 # Clocks
12 #
12 #
13 define_clock {clk50MHz} -freq 50 -clockgroup default_clkgroup_0
13 define_clock {clk50MHz} -name {clk50MHz} -freq 50 -clockgroup default_clkgroup_0
14 define_clock {n:clk_25} -freq 25 -clockgroup default_clkgroup_1
14 define_clock {n:clk_25} -name {n:clk_25} -freq 25 -clockgroup default_clkgroup_1
15 define_clock {n:clk_24} -freq 24.576 -clockgroup default_clkgroup_2
15 define_clock {n:clk_24} -name {n:clk_24} -freq 24.576 -clockgroup default_clkgroup_2
16 define_clock {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_3
16 define_clock {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -name {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_3
17 define_clock {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_4
17 define_clock {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -name {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_4
18 define_clock {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_5
18 define_clock {clk49_152MHz} -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_5
19
19
20 #
20 #
21 # Clock to Clock
21 # Clock to Clock
@@ -36,24 +36,21 define_clock {clk49_152MHz} -freq 49.
36 #
36 #
37 # Attributes
37 # Attributes
38 #
38 #
39 define_global_attribute syn_useioff {1}
39 define_global_attribute {syn_useioff} {1}
40 define_attribute {n:leon3_soc_1\.l3\.cpu.0.leon3_radhard_i.cpu.holdn} syn_maxfan {10000}
40 define_attribute {n:leon3_soc_1\.l3\.cpu.0.leon3_radhard_i.cpu.holdn} {syn_maxfan} {10000}
41 define_attribute {n:spw_inputloop\.0\.spw_phy0.rxclki_1} syn_maxfan {10000}
41 define_attribute {n:spw_inputloop\.0\.spw_phy0.rxclki_1} {syn_maxfan} {10000}
42 define_attribute {n:spw_inputloop\.1\.spw_phy0.rxclki_1} syn_maxfan {10000}
42 define_attribute {n:spw_inputloop\.1\.spw_phy0.rxclki_1} {syn_maxfan} {10000}
43 define_attribute {n:leon3_soc_1\.l3\.cpu.0.leon3_radhard_i.cpu} syn_hier {flatten}
43 define_attribute {n:leon3_soc_1\.l3\.cpu.0.leon3_radhard_i.cpu} {syn_hier} {flatten}
44 define_global_attribute -disable syn_netlist_hierarchy {1}
44 define_global_attribute -disable {syn_netlist_hierarchy} {1}
45
46
47
45
48 #
46 #
49 # I/O Standards
47 # I/O Standards
50 #
48 #
51
49
52
53 #
50 #
54 # Compile Points
51 # Compile Points
55 #
52 #
56
53
57 #
54 #
58 # Other
55 # Other
59 # No newline at end of file
56 #
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@@ -124,6 +124,7 ARCHITECTURE beh OF TB IS
124 --SIGNAL TAG4 : STD_ULOGIC;
124 --SIGNAL TAG4 : STD_ULOGIC;
125 SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0);
125 SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0);
126 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 SIGNAL data_ram : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 SIGNAL nSRAM_MBE : STD_LOGIC;
128 SIGNAL nSRAM_MBE : STD_LOGIC;
128 SIGNAL nSRAM_E1 : STD_LOGIC;
129 SIGNAL nSRAM_E1 : STD_LOGIC;
129 SIGNAL nSRAM_E2 : STD_LOGIC;
130 SIGNAL nSRAM_E2 : STD_LOGIC;
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@@ -316,8 +316,8 BEGIN -- beh
316 ENABLE_FPU => 1,
316 ENABLE_FPU => 1,
317 FPU_NETLIST => 0,
317 FPU_NETLIST => 0,
318 ENABLE_DSU => 1,
318 ENABLE_DSU => 1,
319 ENABLE_AHB_UART => 1,
319 ENABLE_AHB_UART => 0,
320 ENABLE_APB_UART => 1,
320 ENABLE_APB_UART => 0,
321 ENABLE_IRQMP => 1,
321 ENABLE_IRQMP => 1,
322 ENABLE_GPT => 1,
322 ENABLE_GPT => 1,
323 NB_AHB_MASTER => NB_AHB_MASTER,
323 NB_AHB_MASTER => NB_AHB_MASTER,
@@ -514,7 +514,7 BEGIN -- beh
514 pirq_ms => 6,
514 pirq_ms => 6,
515 pirq_wfp => 14,
515 pirq_wfp => 14,
516 hindex => 2,
516 hindex => 2,
517 top_lfr_version => X"000146") -- aa.bb.cc version
517 top_lfr_version => X"000154") -- aa.bb.cc version
518 PORT MAP (
518 PORT MAP (
519 clk => clk_25,
519 clk => clk_25,
520 rstn => LFR_rstn,
520 rstn => LFR_rstn,
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@@ -122,38 +122,26 BEGIN
122 PROCESS (clk, rstn)
122 PROCESS (clk, rstn)
123 BEGIN -- PROCESS
123 BEGIN -- PROCESS
124 IF rstn = '0' THEN -- asynchronous reset (active low)
124 IF rstn = '0' THEN -- asynchronous reset (active low)
125 state <= DESYNC;
125 state <= DESYNC;
126 set_TCU <= '0';
126 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
127 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
127 --CT_add1 <= '0';
128 set_TCU <= '0';
128 set_TCU <= '0';
129 CASE state IS
129 CASE state IS
130 WHEN DESYNC =>
130 WHEN DESYNC =>
131 IF tick = '1' THEN
131 IF tick = '1' THEN
132 state <= SYNC;
132 state <= SYNC;
133 set_TCU <= new_coarsetime_reg;
133 set_TCU <= new_coarsetime_reg;
134 --IF new_coarsetime = '0' AND FT_half = '1' THEN
135 -- CT_add1 <= '1';
136 --END IF;
137 --ELSIF FT_max = '1' THEN
138 -- CT_add1 <= '1';
139 END IF;
134 END IF;
140 WHEN TRANSITION =>
135 WHEN TRANSITION =>
141 IF tick = '1' THEN
136 IF tick = '1' THEN
142 state <= SYNC;
137 state <= SYNC;
143 set_TCU <= new_coarsetime_reg;
138 set_TCU <= new_coarsetime_reg;
144 --IF new_coarsetime = '0' THEN
145 -- CT_add1 <= '1';
146 --END IF;
147 ELSIF FT_wait = '1' THEN
139 ELSIF FT_wait = '1' THEN
148 --CT_add1 <= '1';
149 state <= DESYNC;
140 state <= DESYNC;
150 END IF;
141 END IF;
151 WHEN SYNC =>
142 WHEN SYNC =>
152 IF tick = '1' THEN
143 IF tick = '1' THEN
153 set_TCU <= new_coarsetime_reg;
144 set_TCU <= new_coarsetime_reg;
154 --IF new_coarsetime = '0' THEN
155 -- CT_add1 <= '1';
156 --END IF;
157 ELSIF FT_max = '1' THEN
145 ELSIF FT_max = '1' THEN
158 state <= TRANSITION;
146 state <= TRANSITION;
159 END IF;
147 END IF;
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@@ -42,11 +42,13 ENTITY SPI_DAC_DRIVER IS
42 END ENTITY SPI_DAC_DRIVER;
42 END ENTITY SPI_DAC_DRIVER;
43
43
44 ARCHITECTURE behav OF SPI_DAC_DRIVER IS
44 ARCHITECTURE behav OF SPI_DAC_DRIVER IS
45 SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
45 SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
46 SIGNAL INPUTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
46 SIGNAL INPUTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
47 SIGNAL SMP_CLK_R : STD_LOGIC := '0';
47 SIGNAL SMP_CLK_R : STD_LOGIC := '0';
48 SIGNAL shiftcnt : INTEGER := 0;
48 SIGNAL shiftcnt : INTEGER := 0;
49 SIGNAL shifting : STD_LOGIC := '0';
49 SIGNAL shifting : STD_LOGIC := '0';
50
51 SIGNAL SCLK_s : STD_LOGIC;
50 BEGIN
52 BEGIN
51
53
52
54
@@ -58,7 +60,16 BEGIN
58 INPUTREG(datawidth-1 DOWNTO 0) <= DATA(0 TO datawidth-1);
60 INPUTREG(datawidth-1 DOWNTO 0) <= DATA(0 TO datawidth-1);
59 END GENERATE;
61 END GENERATE;
60
62
61 SCLK <= clk;
63 PROCESS (clk, rstn)
64 BEGIN -- PROCESS
65 IF rstn = '0' THEN -- asynchronous reset (active low)
66 SCLK_s <= '0';
67 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
68 SCLK_s <= NOT SCLK_s;
69
70 END IF;
71 END PROCESS;
72 SCLK <= SCLK_s;
62
73
63 PROCESS(clk, rstn)
74 PROCESS(clk, rstn)
64 BEGIN
75 BEGIN
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@@ -140,21 +140,6 ARCHITECTURE beh OF lpp_lfr IS
140 -----------------------------------------------------------------------------
140 -----------------------------------------------------------------------------
141 --
141 --
142 -----------------------------------------------------------------------------
142 -----------------------------------------------------------------------------
143 -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
145 -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
146 --f1
147 -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
149 -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
150 --f2
151 -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
153 -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
154 --f3
155 -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
157 -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
158
143
159 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
144 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
145 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
@@ -162,57 +147,8 ARCHITECTURE beh OF lpp_lfr IS
162 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
147 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
148 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
164 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 -----------------------------------------------------------------------------
166 -- DMA RR
167 -----------------------------------------------------------------------------
168 -- SIGNAL dma_sel_valid : STD_LOGIC;
169 -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
170 -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
173
174 -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
175 -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
176
177 -----------------------------------------------------------------------------
178 -- DMA_REG
179 -----------------------------------------------------------------------------
180 -- SIGNAL ongoing_reg : STD_LOGIC;
181 -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
182 -- SIGNAL dma_send_reg : STD_LOGIC;
183 -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
184 -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
186
187
188 -----------------------------------------------------------------------------
189 -- DMA
190 -----------------------------------------------------------------------------
191 -- SIGNAL dma_send : STD_LOGIC;
192 -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
193 -- SIGNAL dma_done : STD_LOGIC;
194 -- SIGNAL dma_ren : STD_LOGIC;
195 -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
198
199 -----------------------------------------------------------------------------
200 -- MS
201 -----------------------------------------------------------------------------
202
203 -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 -- SIGNAL data_ms_valid : STD_LOGIC;
206 -- SIGNAL data_ms_valid_burst : STD_LOGIC;
207 -- SIGNAL data_ms_ren : STD_LOGIC;
208 -- SIGNAL data_ms_done : STD_LOGIC;
209 -- SIGNAL dma_ms_ongoing : STD_LOGIC;
210
211 -- SIGNAL run_ms : STD_LOGIC;
212 -- SIGNAL ms_softandhard_rstn : STD_LOGIC;
213
150
214 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
151 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
215 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
216 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
152 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
217 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
153 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
218
154
@@ -220,9 +156,6 ARCHITECTURE beh OF lpp_lfr IS
220 SIGNAL error_buffer_full : STD_LOGIC;
156 SIGNAL error_buffer_full : STD_LOGIC;
221 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
157 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
222
158
223 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
225
226 -----------------------------------------------------------------------------
159 -----------------------------------------------------------------------------
227 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
160 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
228 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
161 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
@@ -247,17 +180,12 ARCHITECTURE beh OF lpp_lfr IS
247
180
248 BEGIN
181 BEGIN
249
182
250 --apb_reg_debug_vector;
251 -----------------------------------------------------------------------------
183 -----------------------------------------------------------------------------
252
184
253 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
185 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
254 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
186 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
255 sample_time <= coarse_time & fine_time;
187 sample_time <= coarse_time & fine_time;
256
188
257 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
258 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
259 --END GENERATE all_channel;
260
261 -----------------------------------------------------------------------------
189 -----------------------------------------------------------------------------
262 lpp_lfr_filter_1 : lpp_lfr_filter
190 lpp_lfr_filter_1 : lpp_lfr_filter
263 GENERIC MAP (
191 GENERIC MAP (
@@ -291,7 +219,6 BEGIN
291 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
219 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
292 GENERIC MAP (
220 GENERIC MAP (
293 nb_data_by_buffer_size => nb_data_by_buffer_size,
221 nb_data_by_buffer_size => nb_data_by_buffer_size,
294 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
295 nb_snapshot_param_size => nb_snapshot_param_size,
222 nb_snapshot_param_size => nb_snapshot_param_size,
296 delta_vector_size => delta_vector_size,
223 delta_vector_size => delta_vector_size,
297 delta_vector_size_f0_2 => delta_vector_size_f0_2,
224 delta_vector_size_f0_2 => delta_vector_size_f0_2,
@@ -312,8 +239,8 BEGIN
312 ready_matrix_f0 => ready_matrix_f0,
239 ready_matrix_f0 => ready_matrix_f0,
313 ready_matrix_f1 => ready_matrix_f1,
240 ready_matrix_f1 => ready_matrix_f1,
314 ready_matrix_f2 => ready_matrix_f2,
241 ready_matrix_f2 => ready_matrix_f2,
315 error_buffer_full => error_buffer_full, -- TODO
242 error_buffer_full => error_buffer_full,
316 error_input_fifo_write => error_input_fifo_write, -- TODO
243 error_input_fifo_write => error_input_fifo_write,
317 status_ready_matrix_f0 => status_ready_matrix_f0,
244 status_ready_matrix_f0 => status_ready_matrix_f0,
318 status_ready_matrix_f1 => status_ready_matrix_f1,
245 status_ready_matrix_f1 => status_ready_matrix_f1,
319 status_ready_matrix_f2 => status_ready_matrix_f2,
246 status_ready_matrix_f2 => status_ready_matrix_f2,
@@ -329,10 +256,6 BEGIN
329 length_matrix_f0 => length_matrix_f0,
256 length_matrix_f0 => length_matrix_f0,
330 length_matrix_f1 => length_matrix_f1,
257 length_matrix_f1 => length_matrix_f1,
331 length_matrix_f2 => length_matrix_f2,
258 length_matrix_f2 => length_matrix_f2,
332 -------------------------------------------------------------------------
333 --status_full => status_full, -- TODo
334 --status_full_ack => status_full_ack, -- TODo
335 --status_full_err => status_full_err, -- TODo
336 status_new_err => status_new_err,
259 status_new_err => status_new_err,
337 data_shaping_BW => data_shaping_BW,
260 data_shaping_BW => data_shaping_BW,
338 data_shaping_SP0 => data_shaping_SP0,
261 data_shaping_SP0 => data_shaping_SP0,
@@ -346,7 +269,6 BEGIN
346 delta_f1 => delta_f1,
269 delta_f1 => delta_f1,
347 delta_f2 => delta_f2,
270 delta_f2 => delta_f2,
348 nb_data_by_buffer => nb_data_by_buffer,
271 nb_data_by_buffer => nb_data_by_buffer,
349 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
350 nb_snapshot_param => nb_snapshot_param,
272 nb_snapshot_param => nb_snapshot_param,
351 enable_f0 => enable_f0,
273 enable_f0 => enable_f0,
352 enable_f1 => enable_f1,
274 enable_f1 => enable_f1,
@@ -355,16 +277,15 BEGIN
355 burst_f0 => burst_f0,
277 burst_f0 => burst_f0,
356 burst_f1 => burst_f1,
278 burst_f1 => burst_f1,
357 burst_f2 => burst_f2,
279 burst_f2 => burst_f2,
358 run => OPEN, --run,
280 run => OPEN,
359 start_date => start_date,
281 start_date => start_date,
360 -- debug_signal => debug_signal,
282 wfp_status_buffer_ready => wfp_status_buffer_ready,
361 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
283 wfp_addr_buffer => wfp_addr_buffer,
362 wfp_addr_buffer => wfp_addr_buffer,-- TODO
284 wfp_length_buffer => wfp_length_buffer,
363 wfp_length_buffer => wfp_length_buffer,-- TODO
364
285
365 wfp_ready_buffer => wfp_ready_buffer,-- TODO
286 wfp_ready_buffer => wfp_ready_buffer,
366 wfp_buffer_time => wfp_buffer_time,-- TODO
287 wfp_buffer_time => wfp_buffer_time,
367 wfp_error_buffer_full => wfp_error_buffer_full, -- TODO
288 wfp_error_buffer_full => wfp_error_buffer_full,
368 -------------------------------------------------------------------------
289 -------------------------------------------------------------------------
369 sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
290 sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
370 sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
291 sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
@@ -462,17 +383,12 BEGIN
462 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
383 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
463 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
384 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
464
385
465 -------------------------------------------------------------------------------
466
467 --ms_softandhard_rstn <= rstn AND run_ms AND run;
468
469 -----------------------------------------------------------------------------
386 -----------------------------------------------------------------------------
470 lpp_lfr_ms_1 : lpp_lfr_ms
387 lpp_lfr_ms_1 : lpp_lfr_ms
471 GENERIC MAP (
388 GENERIC MAP (
472 Mem_use => Mem_use)
389 Mem_use => Mem_use)
473 PORT MAP (
390 PORT MAP (
474 clk => clk,
391 clk => clk,
475 --rstn => ms_softandhard_rstn, --rstn,
476 rstn => rstn,
392 rstn => rstn,
477
393
478 run => '1',--run_ms,
394 run => '1',--run_ms,
@@ -596,4 +512,4 BEGIN
596 END GENERATE all_channel_sim;
512 END GENERATE all_channel_sim;
597 -----------------------------------------------------------------------------
513 -----------------------------------------------------------------------------
598
514
599 END beh; No newline at end of file
515 END beh;
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