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Mini LFR - 0.1.84
pellion -
r617:7ac14cef3eb0 simu_with_Leon3
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@@ -1,124 +1,124
1 set_io clk49_152MHz -pinname 314 -fixed yes -DIRECTION Inout
1 set_io clk49_152MHz -pinname 314 -fixed yes -DIRECTION Inout
2 set_io clk50MHz -pinname 318 -fixed yes -DIRECTION Inout
2 set_io clk50MHz -pinname 318 -fixed yes -DIRECTION Inout
3 set_io reset -pinname 128 -fixed yes -DIRECTION Inout
3 set_io reset -pinname 128 -fixed yes -DIRECTION Inout
4
4
5 set_io {address[0]} -pinname 124 -fixed yes -DIRECTION Inout
5 set_io {address[0]} -pinname 124 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname 156 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname 156 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname 154 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname 154 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname 160 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname 160 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname 162 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname 162 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname 165 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname 165 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname 155 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname 155 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname 127 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname 127 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname 123 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname 123 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname 137 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname 137 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname 141 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname 141 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname 166 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname 166 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname 182 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname 182 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname 167 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname 167 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname 181 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname 181 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname 171 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname 171 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname 183 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname 183 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname 161 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname 161 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname 159 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname 159 -fixed yes -DIRECTION Inout
24
24
25 set_io {data[0]} -pinname 103 -fixed yes -DIRECTION Inout
25 set_io {data[0]} -pinname 103 -fixed yes -DIRECTION Inout
26 set_io {data[1]} -pinname 100 -fixed yes -DIRECTION Inout
26 set_io {data[1]} -pinname 100 -fixed yes -DIRECTION Inout
27 set_io {data[2]} -pinname 99 -fixed yes -DIRECTION Inout
27 set_io {data[2]} -pinname 99 -fixed yes -DIRECTION Inout
28 set_io {data[3]} -pinname 98 -fixed yes -DIRECTION Inout
28 set_io {data[3]} -pinname 98 -fixed yes -DIRECTION Inout
29 set_io {data[4]} -pinname 97 -fixed yes -DIRECTION Inout
29 set_io {data[4]} -pinname 97 -fixed yes -DIRECTION Inout
30 set_io {data[5]} -pinname 94 -fixed yes -DIRECTION Inout
30 set_io {data[5]} -pinname 94 -fixed yes -DIRECTION Inout
31 set_io {data[6]} -pinname 93 -fixed yes -DIRECTION Inout
31 set_io {data[6]} -pinname 93 -fixed yes -DIRECTION Inout
32 set_io {data[7]} -pinname 92 -fixed yes -DIRECTION Inout
32 set_io {data[7]} -pinname 92 -fixed yes -DIRECTION Inout
33 set_io {data[8]} -pinname 82 -fixed yes -DIRECTION Inout
33 set_io {data[8]} -pinname 82 -fixed yes -DIRECTION Inout
34 set_io {data[9]} -pinname 79 -fixed yes -DIRECTION Inout
34 set_io {data[9]} -pinname 79 -fixed yes -DIRECTION Inout
35 set_io {data[10]} -pinname 78 -fixed yes -DIRECTION Inout
35 set_io {data[10]} -pinname 78 -fixed yes -DIRECTION Inout
36 set_io {data[11]} -pinname 77 -fixed yes -DIRECTION Inout
36 set_io {data[11]} -pinname 77 -fixed yes -DIRECTION Inout
37 set_io {data[12]} -pinname 71 -fixed yes -DIRECTION Inout
37 set_io {data[12]} -pinname 71 -fixed yes -DIRECTION Inout
38 set_io {data[13]} -pinname 70 -fixed yes -DIRECTION Inout
38 set_io {data[13]} -pinname 70 -fixed yes -DIRECTION Inout
39 set_io {data[14]} -pinname 67 -fixed yes -DIRECTION Inout
39 set_io {data[14]} -pinname 67 -fixed yes -DIRECTION Inout
40 set_io {data[15]} -pinname 66 -fixed yes -DIRECTION Inout
40 set_io {data[15]} -pinname 66 -fixed yes -DIRECTION Inout
41 set_io {data[16]} -pinname 246 -fixed yes -DIRECTION Inout
41 set_io {data[16]} -pinname 246 -fixed yes -DIRECTION Inout
42 set_io {data[17]} -pinname 242 -fixed yes -DIRECTION Inout
42 set_io {data[17]} -pinname 242 -fixed yes -DIRECTION Inout
43 set_io {data[18]} -pinname 241 -fixed yes -DIRECTION Inout
43 set_io {data[18]} -pinname 241 -fixed yes -DIRECTION Inout
44 set_io {data[19]} -pinname 229 -fixed yes -DIRECTION Inout
44 set_io {data[19]} -pinname 229 -fixed yes -DIRECTION Inout
45 set_io {data[20]} -pinname 228 -fixed yes -DIRECTION Inout
45 set_io {data[20]} -pinname 228 -fixed yes -DIRECTION Inout
46 set_io {data[21]} -pinname 227 -fixed yes -DIRECTION Inout
46 set_io {data[21]} -pinname 227 -fixed yes -DIRECTION Inout
47 set_io {data[22]} -pinname 224 -fixed yes -DIRECTION Inout
47 set_io {data[22]} -pinname 224 -fixed yes -DIRECTION Inout
48 set_io {data[23]} -pinname 223 -fixed yes -DIRECTION Inout
48 set_io {data[23]} -pinname 223 -fixed yes -DIRECTION Inout
49 set_io {data[24]} -pinname 206 -fixed yes -DIRECTION Inout
49 set_io {data[24]} -pinname 206 -fixed yes -DIRECTION Inout
50 set_io {data[25]} -pinname 212 -fixed yes -DIRECTION Inout
50 set_io {data[25]} -pinname 212 -fixed yes -DIRECTION Inout
51 set_io {data[26]} -pinname 207 -fixed yes -DIRECTION Inout
51 set_io {data[26]} -pinname 207 -fixed yes -DIRECTION Inout
52 set_io {data[27]} -pinname 211 -fixed yes -DIRECTION Inout
52 set_io {data[27]} -pinname 211 -fixed yes -DIRECTION Inout
53 set_io {data[28]} -pinname 205 -fixed yes -DIRECTION Inout
53 set_io {data[28]} -pinname 205 -fixed yes -DIRECTION Inout
54 set_io {data[29]} -pinname 213 -fixed yes -DIRECTION Inout
54 set_io {data[29]} -pinname 213 -fixed yes -DIRECTION Inout
55 set_io {data[30]} -pinname 202 -fixed yes -DIRECTION Inout
55 set_io {data[30]} -pinname 202 -fixed yes -DIRECTION Inout
56 set_io {data[31]} -pinname 214 -fixed yes -DIRECTION Inout
56 set_io {data[31]} -pinname 214 -fixed yes -DIRECTION Inout
57
57
58 set_io nSRAM_MBE -pinname 9 -fixed yes -DIRECTION Inout
58 set_io nSRAM_MBE -pinname 9 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E1 -pinname 20 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E1 -pinname 20 -fixed yes -DIRECTION Inout
60 set_io nSRAM_E2 -pinname 15 -fixed yes -DIRECTION Inout
60 set_io nSRAM_E2 -pinname 15 -fixed yes -DIRECTION Inout
61 set_io nSRAM_SCRUB -pinname 14 -fixed yes -DIRECTION Inout
61 #set_io nSRAM_SCRUB -pinname 14 -fixed yes -DIRECTION Inout
62 set_io nSRAM_W -pinname 8 -fixed yes -DIRECTION Inout
62 set_io nSRAM_W -pinname 8 -fixed yes -DIRECTION Inout
63 set_io nSRAM_G -pinname 21 -fixed yes -DIRECTION Inout
63 set_io nSRAM_G -pinname 21 -fixed yes -DIRECTION Inout
64 set_io nSRAM_BUSY -pinname 24 -fixed yes -DIRECTION Inout
64 set_io nSRAM_BUSY -pinname 24 -fixed yes -DIRECTION Inout
65
65
66 set_io spw1_en -pinname 31 -fixed yes -DIRECTION Inout
66 set_io spw1_en -pinname 31 -fixed yes -DIRECTION Inout
67 set_io spw1_din -pinname 300 -fixed yes -DIRECTION Inout
67 set_io spw1_din -pinname 300 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname 299 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname 299 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname 303 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname 303 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname 317 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname 317 -fixed yes -DIRECTION Inout
71
71
72 set_io spw2_en -pinname 30 -fixed yes -DIRECTION Inout
72 set_io spw2_en -pinname 30 -fixed yes -DIRECTION Inout
73 set_io spw2_din -pinname 313 -fixed yes -DIRECTION Inout
73 set_io spw2_din -pinname 313 -fixed yes -DIRECTION Inout
74 set_io spw2_sin -pinname 304 -fixed yes -DIRECTION Inout
74 set_io spw2_sin -pinname 304 -fixed yes -DIRECTION Inout
75 set_io spw2_dout -pinname 335 -fixed yes -DIRECTION Inout
75 set_io spw2_dout -pinname 335 -fixed yes -DIRECTION Inout
76 set_io spw2_sout -pinname 330 -fixed yes -DIRECTION Inout
76 set_io spw2_sout -pinname 330 -fixed yes -DIRECTION Inout
77
77
78 set_io TAG1 -pinname 195 -fixed yes -DIRECTION Inout
78 set_io {TAG[1]} -pinname 195 -fixed yes -DIRECTION Inout
79 set_io TAG2 -pinname 190 -fixed yes -DIRECTION Inout
79 #set_io {TAG[2]} -pinname 190 -fixed yes -DIRECTION Inout
80 set_io TAG3 -pinname 189 -fixed yes -DIRECTION Inout
80 set_io {TAG[3]} -pinname 189 -fixed yes -DIRECTION Inout
81 set_io TAG4 -pinname 188 -fixed yes -DIRECTION Inout
81 #set_io {TAG[4]} -pinname 188 -fixed yes -DIRECTION Inout
82 #set_io TAG5 -pinname 187 -fixed yes -DIRECTION Inout
82 #set_io {TAG[5]} -pinname 187 -fixed yes -DIRECTION Inout
83 #set_io TAG6 -pinname 184 -fixed yes -DIRECTION Inout
83 #set_io {TAG[6]} -pinname 184 -fixed yes -DIRECTION Inout
84 #set_io TAG7 -pinname 200 -fixed yes -DIRECTION Inout
84 #set_io {TAG[7]} -pinname 200 -fixed yes -DIRECTION Inout
85 set_io TAG8 -pinname 199 -fixed yes -DIRECTION Inout
85 #set_io {TAG[8]} -pinname 199 -fixed yes -DIRECTION Inout
86 #set_io TAG9 -pinname 196 -fixed yes -DIRECTION Inout
86 #set_io {TAG[9]} -pinname 196 -fixed yes -DIRECTION Inout
87
87
88 set_io bias_fail_sw -pinname 342 -fixed yes -DIRECTION Inout
88 set_io bias_fail_sw -pinname 342 -fixed yes -DIRECTION Inout
89
89
90 set_io {ADC_OEB_bar_CH[0]} -pinname 288 -fixed yes -DIRECTION Inout
90 set_io {ADC_OEB_bar_CH[0]} -pinname 288 -fixed yes -DIRECTION Inout
91 set_io {ADC_OEB_bar_CH[1]} -pinname 287 -fixed yes -DIRECTION Inout
91 set_io {ADC_OEB_bar_CH[1]} -pinname 287 -fixed yes -DIRECTION Inout
92 set_io {ADC_OEB_bar_CH[2]} -pinname 285 -fixed yes -DIRECTION Inout
92 set_io {ADC_OEB_bar_CH[2]} -pinname 285 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[3]} -pinname 286 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[3]} -pinname 286 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[4]} -pinname 281 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[4]} -pinname 281 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[5]} -pinname 332 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[5]} -pinname 332 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[6]} -pinname 282 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[6]} -pinname 282 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[7]} -pinname 280 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[7]} -pinname 280 -fixed yes -DIRECTION Inout
98
98
99 set_io ADC_smpclk -pinname 279 -fixed yes -DIRECTION Inout
99 set_io ADC_smpclk -pinname 279 -fixed yes -DIRECTION Inout
100
100
101 set_io HK_smpclk -pinname 172 -fixed yes -DIRECTION Inout
101 set_io HK_smpclk -pinname 172 -fixed yes -DIRECTION Inout
102 set_io ADC_OEB_bar_HK -pinname 331 -fixed yes -DIRECTION Inout
102 set_io ADC_OEB_bar_HK -pinname 331 -fixed yes -DIRECTION Inout
103 set_io {HK_SEL[0]} -pinname 6 -fixed yes -DIRECTION Inout
103 set_io {HK_SEL[0]} -pinname 6 -fixed yes -DIRECTION Inout
104 set_io {HK_SEL[1]} -pinname 343 -fixed yes -DIRECTION Inout
104 set_io {HK_SEL[1]} -pinname 343 -fixed yes -DIRECTION Inout
105
105
106 set_io {ADC_data[0]} -pinname 251 -fixed yes -DIRECTION Inout
106 set_io {ADC_data[0]} -pinname 251 -fixed yes -DIRECTION Inout
107 set_io {ADC_data[1]} -pinname 253 -fixed yes -DIRECTION Inout
107 set_io {ADC_data[1]} -pinname 253 -fixed yes -DIRECTION Inout
108 set_io {ADC_data[2]} -pinname 257 -fixed yes -DIRECTION Inout
108 set_io {ADC_data[2]} -pinname 257 -fixed yes -DIRECTION Inout
109 set_io {ADC_data[3]} -pinname 259 -fixed yes -DIRECTION Inout
109 set_io {ADC_data[3]} -pinname 259 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[4]} -pinname 252 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[4]} -pinname 252 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[5]} -pinname 254 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[5]} -pinname 254 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[6]} -pinname 258 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[6]} -pinname 258 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[7]} -pinname 260 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[7]} -pinname 260 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[8]} -pinname 270 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[8]} -pinname 270 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[9]} -pinname 274 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[9]} -pinname 274 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[10]} -pinname 276 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[10]} -pinname 276 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[11]} -pinname 275 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[11]} -pinname 275 -fixed yes -DIRECTION Inout
118 set_io {ADC_data[12]} -pinname 273 -fixed yes -DIRECTION Inout
118 set_io {ADC_data[12]} -pinname 273 -fixed yes -DIRECTION Inout
119 set_io {ADC_data[13]} -pinname 269 -fixed yes -DIRECTION Inout
119 set_io {ADC_data[13]} -pinname 269 -fixed yes -DIRECTION Inout
120
120
121 set_io DAC_SDO -pinname 341 -fixed yes -DIRECTION Inout
121 set_io DAC_SDO -pinname 341 -fixed yes -DIRECTION Inout
122 set_io DAC_SCK -pinname 338 -fixed yes -DIRECTION Inout
122 set_io DAC_SCK -pinname 338 -fixed yes -DIRECTION Inout
123 set_io DAC_SYNC -pinname 337 -fixed yes -DIRECTION Inout
123 set_io DAC_SYNC -pinname 337 -fixed yes -DIRECTION Inout
124 set_io DAC_CAL_EN -pinname 336 -fixed yes -DIRECTION Inout
124 set_io DAC_CAL_EN -pinname 336 -fixed yes -DIRECTION Inout
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@@ -1,59 +1,56
1 # Synopsys, Inc. constraint file
1 # Synopsys, Inc. constraint file
2 # E:\opt\tortoiseHG_vhdlib\boards\LFR-EQM\LFR_EQM_altran_syn.sdc
2 # E:/opt/tortoiseHG_vhdlib/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_5/../../../boards/LFR-EQM/LFR_EQM_altran_syn_fanout.sdc
3 # Written on Fri Jun 12 10:24:30 2015
3 # Written on Fri Jun 26 12:55:35 2015
4 # by Synplify Pro, E-2010.09A-1 Scope Editor
4 # by Synplify Pro, E-2010.09A-1 Scope Editor
5
5
6 #
6 #
7 # Collections
7 # Collections
8 #
8 #
9
9
10 #
10 #
11 # Clocks
11 # Clocks
12 #
12 #
13 define_clock {clk50MHz} -freq 50 -clockgroup default_clkgroup_0
13 define_clock {clk50MHz} -name {clk50MHz} -freq 50 -clockgroup default_clkgroup_0
14 define_clock {n:clk_25} -freq 25 -clockgroup default_clkgroup_1
14 define_clock {n:clk_25} -name {n:clk_25} -freq 25 -clockgroup default_clkgroup_1
15 define_clock {n:clk_24} -freq 24.576 -clockgroup default_clkgroup_2
15 define_clock {n:clk_24} -name {n:clk_24} -freq 24.576 -clockgroup default_clkgroup_2
16 define_clock {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_3
16 define_clock {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -name {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_3
17 define_clock {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_4
17 define_clock {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -name {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_4
18 define_clock {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_5
18 define_clock {clk49_152MHz} -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_5
19
19
20 #
20 #
21 # Clock to Clock
21 # Clock to Clock
22 #
22 #
23
23
24 #
24 #
25 # Inputs/Outputs
25 # Inputs/Outputs
26 #
26 #
27
27
28 #
28 #
29 # Registers
29 # Registers
30 #
30 #
31
31
32 #
32 #
33 # Delay Paths
33 # Delay Paths
34 #
34 #
35
35
36 #
36 #
37 # Attributes
37 # Attributes
38 #
38 #
39 define_global_attribute syn_useioff {1}
39 define_global_attribute {syn_useioff} {1}
40 define_attribute {n:leon3_soc_1\.l3\.cpu.0.leon3_radhard_i.cpu.holdn} syn_maxfan {10000}
40 define_attribute {n:leon3_soc_1\.l3\.cpu.0.leon3_radhard_i.cpu.holdn} {syn_maxfan} {10000}
41 define_attribute {n:spw_inputloop\.0\.spw_phy0.rxclki_1} syn_maxfan {10000}
41 define_attribute {n:spw_inputloop\.0\.spw_phy0.rxclki_1} {syn_maxfan} {10000}
42 define_attribute {n:spw_inputloop\.1\.spw_phy0.rxclki_1} syn_maxfan {10000}
42 define_attribute {n:spw_inputloop\.1\.spw_phy0.rxclki_1} {syn_maxfan} {10000}
43 define_attribute {n:leon3_soc_1\.l3\.cpu.0.leon3_radhard_i.cpu} syn_hier {flatten}
43 define_attribute {n:leon3_soc_1\.l3\.cpu.0.leon3_radhard_i.cpu} {syn_hier} {flatten}
44 define_global_attribute -disable syn_netlist_hierarchy {1}
44 define_global_attribute -disable {syn_netlist_hierarchy} {1}
45
46
47
45
48 #
46 #
49 # I/O Standards
47 # I/O Standards
50 #
48 #
51
49
52
53 #
50 #
54 # Compile Points
51 # Compile Points
55 #
52 #
56
53
57 #
54 #
58 # Other
55 # Other
59 # No newline at end of file
56 #
Show file before | Show file after | Hide comments
@@ -1,685 +1,686
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
26
26
27 LIBRARY techmap;
27 LIBRARY techmap;
28 USE techmap.gencomp.ALL;
28 USE techmap.gencomp.ALL;
29
29
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_sim_pkg.ALL;
31 USE lpp.lpp_sim_pkg.ALL;
32 USE lpp.lpp_lfr_sim_pkg.ALL;
32 USE lpp.lpp_lfr_sim_pkg.ALL;
33 USE lpp.lpp_lfr_apbreg_pkg.ALL;
33 USE lpp.lpp_lfr_apbreg_pkg.ALL;
34 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
34 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
35 USE lpp.iir_filter.ALL;
35 USE lpp.iir_filter.ALL;
36 USE lpp.FILTERcfg.ALL;
36 USE lpp.FILTERcfg.ALL;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_waveform_pkg.ALL;
38 USE lpp.lpp_waveform_pkg.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_top_lfr_pkg.ALL;
40 USE lpp.lpp_top_lfr_pkg.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.general_purpose.ALL;
42 USE lpp.general_purpose.ALL;
43 --LIBRARY lpp;
43 --LIBRARY lpp;
44 USE lpp.lpp_ad_conv.ALL;
44 USE lpp.lpp_ad_conv.ALL;
45 --USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
45 --USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
46 --USE lpp.lpp_lfr_apbreg_pkg.ALL;
46 --USE lpp.lpp_lfr_apbreg_pkg.ALL;
47
47
48 --USE work.debug.ALL;
48 --USE work.debug.ALL;
49
49
50 LIBRARY gaisler;
50 LIBRARY gaisler;
51 USE gaisler.libdcom.ALL;
51 USE gaisler.libdcom.ALL;
52 USE gaisler.sim.ALL;
52 USE gaisler.sim.ALL;
53 USE gaisler.memctrl.ALL;
53 USE gaisler.memctrl.ALL;
54 USE gaisler.leon3.ALL;
54 USE gaisler.leon3.ALL;
55 USE gaisler.uart.ALL;
55 USE gaisler.uart.ALL;
56 USE gaisler.misc.ALL;
56 USE gaisler.misc.ALL;
57 USE gaisler.spacewire.ALL;
57 USE gaisler.spacewire.ALL;
58
58
59 ENTITY TB IS
59 ENTITY TB IS
60
60
61 END TB;
61 END TB;
62
62
63 ARCHITECTURE beh OF TB IS
63 ARCHITECTURE beh OF TB IS
64 CONSTANT sramfile : STRING := "prom.srec";
64 CONSTANT sramfile : STRING := "prom.srec";
65 -- CONSTANT sramfile : STRING;
65 -- CONSTANT sramfile : STRING;
66
66
67 CONSTANT USE_ESA_MEMCTRL : INTEGER := 0;
67 CONSTANT USE_ESA_MEMCTRL : INTEGER := 0;
68
68
69 COMPONENT LFR_EQM
69 COMPONENT LFR_EQM
70 GENERIC (
70 GENERIC (
71 Mem_use : INTEGER;
71 Mem_use : INTEGER;
72 USE_BOOTLOADER : INTEGER;
72 USE_BOOTLOADER : INTEGER;
73 USE_ADCDRIVER : INTEGER;
73 USE_ADCDRIVER : INTEGER;
74 tech : INTEGER;
74 tech : INTEGER;
75 tech_leon : INTEGER;
75 tech_leon : INTEGER;
76 DEBUG_FORCE_DATA_DMA : INTEGER;
76 DEBUG_FORCE_DATA_DMA : INTEGER;
77 USE_DEBUG_VECTOR : INTEGER );
77 USE_DEBUG_VECTOR : INTEGER );
78 PORT (
78 PORT (
79 clk50MHz : IN STD_ULOGIC;
79 clk50MHz : IN STD_ULOGIC;
80 clk49_152MHz : IN STD_ULOGIC;
80 clk49_152MHz : IN STD_ULOGIC;
81 reset : IN STD_ULOGIC;
81 reset : IN STD_ULOGIC;
82 --TAG1 : IN STD_ULOGIC;
82 --TAG1 : IN STD_ULOGIC;
83 --TAG3 : OUT STD_ULOGIC;
83 --TAG3 : OUT STD_ULOGIC;
84 --TAG2 : IN STD_ULOGIC;
84 --TAG2 : IN STD_ULOGIC;
85 --TAG4 : OUT STD_ULOGIC;
85 --TAG4 : OUT STD_ULOGIC;
86 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
86 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
87 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
87 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
88 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 nSRAM_MBE : INOUT STD_LOGIC;
89 nSRAM_MBE : INOUT STD_LOGIC;
90 nSRAM_E1 : OUT STD_LOGIC;
90 nSRAM_E1 : OUT STD_LOGIC;
91 nSRAM_E2 : OUT STD_LOGIC;
91 nSRAM_E2 : OUT STD_LOGIC;
92 nSRAM_W : OUT STD_LOGIC;
92 nSRAM_W : OUT STD_LOGIC;
93 nSRAM_G : OUT STD_LOGIC;
93 nSRAM_G : OUT STD_LOGIC;
94 nSRAM_BUSY : IN STD_LOGIC;
94 nSRAM_BUSY : IN STD_LOGIC;
95 spw1_en : OUT STD_LOGIC;
95 spw1_en : OUT STD_LOGIC;
96 spw1_din : IN STD_LOGIC;
96 spw1_din : IN STD_LOGIC;
97 spw1_sin : IN STD_LOGIC;
97 spw1_sin : IN STD_LOGIC;
98 spw1_dout : OUT STD_LOGIC;
98 spw1_dout : OUT STD_LOGIC;
99 spw1_sout : OUT STD_LOGIC;
99 spw1_sout : OUT STD_LOGIC;
100 spw2_en : OUT STD_LOGIC;
100 spw2_en : OUT STD_LOGIC;
101 spw2_din : IN STD_LOGIC;
101 spw2_din : IN STD_LOGIC;
102 spw2_sin : IN STD_LOGIC;
102 spw2_sin : IN STD_LOGIC;
103 spw2_dout : OUT STD_LOGIC;
103 spw2_dout : OUT STD_LOGIC;
104 spw2_sout : OUT STD_LOGIC;
104 spw2_sout : OUT STD_LOGIC;
105 bias_fail_sw : OUT STD_LOGIC;
105 bias_fail_sw : OUT STD_LOGIC;
106 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
106 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
107 ADC_smpclk : OUT STD_LOGIC;
107 ADC_smpclk : OUT STD_LOGIC;
108 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
108 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
109 DAC_SDO : OUT STD_LOGIC;
109 DAC_SDO : OUT STD_LOGIC;
110 DAC_SCK : OUT STD_LOGIC;
110 DAC_SCK : OUT STD_LOGIC;
111 DAC_SYNC : OUT STD_LOGIC;
111 DAC_SYNC : OUT STD_LOGIC;
112 DAC_CAL_EN : OUT STD_LOGIC;
112 DAC_CAL_EN : OUT STD_LOGIC;
113 HK_smpclk : OUT STD_LOGIC;
113 HK_smpclk : OUT STD_LOGIC;
114 ADC_OEB_bar_HK : OUT STD_LOGIC;
114 ADC_OEB_bar_HK : OUT STD_LOGIC;
115 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
115 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
116 END COMPONENT;
116 END COMPONENT;
117
117
118 SIGNAL clk50MHz : STD_ULOGIC := '0';
118 SIGNAL clk50MHz : STD_ULOGIC := '0';
119 SIGNAL clk49_152MHz : STD_ULOGIC := '0';
119 SIGNAL clk49_152MHz : STD_ULOGIC := '0';
120 SIGNAL reset : STD_ULOGIC;
120 SIGNAL reset : STD_ULOGIC;
121 SIGNAL TAG : STD_LOGIC_VECTOR(9 DOWNTO 1);
121 SIGNAL TAG : STD_LOGIC_VECTOR(9 DOWNTO 1);
122 --SIGNAL TAG3 : STD_ULOGIC;
122 --SIGNAL TAG3 : STD_ULOGIC;
123 --SIGNAL TAG2 : STD_ULOGIC := '1';
123 --SIGNAL TAG2 : STD_ULOGIC := '1';
124 --SIGNAL TAG4 : STD_ULOGIC;
124 --SIGNAL TAG4 : STD_ULOGIC;
125 SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0);
125 SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0);
126 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 SIGNAL data_ram : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 SIGNAL nSRAM_MBE : STD_LOGIC;
128 SIGNAL nSRAM_MBE : STD_LOGIC;
128 SIGNAL nSRAM_E1 : STD_LOGIC;
129 SIGNAL nSRAM_E1 : STD_LOGIC;
129 SIGNAL nSRAM_E2 : STD_LOGIC;
130 SIGNAL nSRAM_E2 : STD_LOGIC;
130 SIGNAL nSRAM_W : STD_LOGIC;
131 SIGNAL nSRAM_W : STD_LOGIC;
131 SIGNAL nSRAM_G : STD_LOGIC;
132 SIGNAL nSRAM_G : STD_LOGIC;
132 SIGNAL nSRAM_BUSY : STD_LOGIC;
133 SIGNAL nSRAM_BUSY : STD_LOGIC;
133 SIGNAL spw1_en : STD_LOGIC;
134 SIGNAL spw1_en : STD_LOGIC;
134 SIGNAL spw1_din : STD_LOGIC := '1';
135 SIGNAL spw1_din : STD_LOGIC := '1';
135 SIGNAL spw1_sin : STD_LOGIC := '1';
136 SIGNAL spw1_sin : STD_LOGIC := '1';
136 SIGNAL spw1_dout : STD_LOGIC;
137 SIGNAL spw1_dout : STD_LOGIC;
137 SIGNAL spw1_sout : STD_LOGIC;
138 SIGNAL spw1_sout : STD_LOGIC;
138 SIGNAL spw2_en : STD_LOGIC;
139 SIGNAL spw2_en : STD_LOGIC;
139 SIGNAL spw2_din : STD_LOGIC := '1';
140 SIGNAL spw2_din : STD_LOGIC := '1';
140 SIGNAL spw2_sin : STD_LOGIC := '1';
141 SIGNAL spw2_sin : STD_LOGIC := '1';
141 SIGNAL spw2_dout : STD_LOGIC;
142 SIGNAL spw2_dout : STD_LOGIC;
142 SIGNAL spw2_sout : STD_LOGIC;
143 SIGNAL spw2_sout : STD_LOGIC;
143 SIGNAL bias_fail_sw : STD_LOGIC;
144 SIGNAL bias_fail_sw : STD_LOGIC;
144 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
145 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
145 SIGNAL ADC_OEB_bar_CH_r : STD_LOGIC_VECTOR(7 DOWNTO 0);
146 SIGNAL ADC_OEB_bar_CH_r : STD_LOGIC_VECTOR(7 DOWNTO 0);
146 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
147 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
147 SIGNAL ADC_smpclk : STD_LOGIC;
148 SIGNAL ADC_smpclk : STD_LOGIC;
148 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
149 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
149 SIGNAL ADC_data_s : STD_LOGIC_VECTOR(13 DOWNTO 0);
150 SIGNAL ADC_data_s : STD_LOGIC_VECTOR(13 DOWNTO 0);
150 SIGNAL DAC_SDO : STD_LOGIC;
151 SIGNAL DAC_SDO : STD_LOGIC;
151 SIGNAL DAC_SCK : STD_LOGIC;
152 SIGNAL DAC_SCK : STD_LOGIC;
152 SIGNAL DAC_SYNC : STD_LOGIC;
153 SIGNAL DAC_SYNC : STD_LOGIC;
153 SIGNAL DAC_CAL_EN : STD_LOGIC;
154 SIGNAL DAC_CAL_EN : STD_LOGIC;
154 SIGNAL HK_smpclk : STD_LOGIC;
155 SIGNAL HK_smpclk : STD_LOGIC;
155 SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
156 SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
156 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
157 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
157 -- SIGNAL TAG8 : STD_LOGIC;
158 -- SIGNAL TAG8 : STD_LOGIC;
158
159
159 CONSTANT SCRUB_RATE_PERIOD : INTEGER := 1800/20;
160 CONSTANT SCRUB_RATE_PERIOD : INTEGER := 1800/20;
160 CONSTANT SCRUB_PERIOD : INTEGER := 200/20;
161 CONSTANT SCRUB_PERIOD : INTEGER := 200/20;
161 CONSTANT SCRUB_BUSY_TO_SCRUB : INTEGER := 700/20;
162 CONSTANT SCRUB_BUSY_TO_SCRUB : INTEGER := 700/20;
162 CONSTANT SCRUB_SCRUB_TO_BUSY : INTEGER := 60/20;
163 CONSTANT SCRUB_SCRUB_TO_BUSY : INTEGER := 60/20;
163 SIGNAL counter_scrub_period : INTEGER;
164 SIGNAL counter_scrub_period : INTEGER;
164
165
165
166
166 --CONSTANT AHBADDR_APB : STD_LOGIC_VECTOR(11 DOWNTO 0) := X"800";
167 --CONSTANT AHBADDR_APB : STD_LOGIC_VECTOR(11 DOWNTO 0) := X"800";
167 --CONSTANT AHBADDR_LFR_MANAGEMENT : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"006";
168 --CONSTANT AHBADDR_LFR_MANAGEMENT : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"006";
168 --CONSTANT AHBADDR_LFR : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"00F";
169 --CONSTANT AHBADDR_LFR : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"00F";
169
170
170 CONSTANT ADDR_BASE_DSU : STD_LOGIC_VECTOR(31 DOWNTO 24) := X"90";
171 CONSTANT ADDR_BASE_DSU : STD_LOGIC_VECTOR(31 DOWNTO 24) := X"90";
171 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
172 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
172 CONSTANT ADDR_BASE_LFR_2 : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000E";
173 CONSTANT ADDR_BASE_LFR_2 : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000E";
173 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
174 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
174 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
175 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
175 CONSTANT ADDR_BASE_ESA_MEMCTRL : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800000";
176 CONSTANT ADDR_BASE_ESA_MEMCTRL : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800000";
176
177
177 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
178 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
178 SIGNAL data_message : STRING(1 TO 15) := "---------------";
179 SIGNAL data_message : STRING(1 TO 15) := "---------------";
179 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
180 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
180 SIGNAL TXD1 : STD_LOGIC;
181 SIGNAL TXD1 : STD_LOGIC;
181 SIGNAL RXD1 : STD_LOGIC;
182 SIGNAL RXD1 : STD_LOGIC;
182
183
183 -----------------------------------------------------------------------------
184 -----------------------------------------------------------------------------
184 CONSTANT ADDR_BUFFER_WFP_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40100000";
185 CONSTANT ADDR_BUFFER_WFP_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40100000";
185 CONSTANT ADDR_BUFFER_WFP_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40110000";
186 CONSTANT ADDR_BUFFER_WFP_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40110000";
186 CONSTANT ADDR_BUFFER_WFP_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40120000";
187 CONSTANT ADDR_BUFFER_WFP_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40120000";
187 CONSTANT ADDR_BUFFER_WFP_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40130000";
188 CONSTANT ADDR_BUFFER_WFP_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40130000";
188 CONSTANT ADDR_BUFFER_WFP_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40140000";
189 CONSTANT ADDR_BUFFER_WFP_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40140000";
189 CONSTANT ADDR_BUFFER_WFP_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40150000";
190 CONSTANT ADDR_BUFFER_WFP_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40150000";
190 CONSTANT ADDR_BUFFER_WFP_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40160000";
191 CONSTANT ADDR_BUFFER_WFP_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40160000";
191 CONSTANT ADDR_BUFFER_WFP_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40170000";
192 CONSTANT ADDR_BUFFER_WFP_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40170000";
192 CONSTANT ADDR_BUFFER_MS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40180000";
193 CONSTANT ADDR_BUFFER_MS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40180000";
193 CONSTANT ADDR_BUFFER_MS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40190000";
194 CONSTANT ADDR_BUFFER_MS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40190000";
194 CONSTANT ADDR_BUFFER_MS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401A0000";
195 CONSTANT ADDR_BUFFER_MS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401A0000";
195 CONSTANT ADDR_BUFFER_MS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401B0000";
196 CONSTANT ADDR_BUFFER_MS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401B0000";
196 CONSTANT ADDR_BUFFER_MS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401C0000";
197 CONSTANT ADDR_BUFFER_MS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401C0000";
197 CONSTANT ADDR_BUFFER_MS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401D0000";
198 CONSTANT ADDR_BUFFER_MS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401D0000";
198
199
199
200
200 TYPE sample_vector_16b IS ARRAY (NATURAL RANGE <> , NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
201 TYPE sample_vector_16b IS ARRAY (NATURAL RANGE <> , NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
201 SIGNAL sample : sample_vector_16b(2 DOWNTO 0, 5 DOWNTO 0);
202 SIGNAL sample : sample_vector_16b(2 DOWNTO 0, 5 DOWNTO 0);
202
203
203 TYPE counter_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
204 TYPE counter_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
204 SIGNAL sample_counter : counter_vector( 2 DOWNTO 0);
205 SIGNAL sample_counter : counter_vector( 2 DOWNTO 0);
205
206
206 SIGNAL data_pre_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
207 SIGNAL data_pre_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
207 SIGNAL data_pre_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 SIGNAL data_pre_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 SIGNAL data_pre_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 SIGNAL data_pre_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 SIGNAL error_wfp : STD_LOGIC_VECTOR(2 DOWNTO 0);
210 SIGNAL error_wfp : STD_LOGIC_VECTOR(2 DOWNTO 0);
210
211
211 SIGNAL addr_pre_f0 : STD_LOGIC_VECTOR(13 DOWNTO 0);
212 SIGNAL addr_pre_f0 : STD_LOGIC_VECTOR(13 DOWNTO 0);
212 SIGNAL addr_pre_f1 : STD_LOGIC_VECTOR(13 DOWNTO 0);
213 SIGNAL addr_pre_f1 : STD_LOGIC_VECTOR(13 DOWNTO 0);
213 SIGNAL addr_pre_f2 : STD_LOGIC_VECTOR(13 DOWNTO 0);
214 SIGNAL addr_pre_f2 : STD_LOGIC_VECTOR(13 DOWNTO 0);
214
215
215
216
216 SIGNAL error_wfp_addr : STD_LOGIC_VECTOR(2 DOWNTO 0);
217 SIGNAL error_wfp_addr : STD_LOGIC_VECTOR(2 DOWNTO 0);
217 -----------------------------------------------------------------------------
218 -----------------------------------------------------------------------------
218 CONSTANT srambanks : INTEGER := 2;
219 CONSTANT srambanks : INTEGER := 2;
219 CONSTANT sramwidth : INTEGER := 32;
220 CONSTANT sramwidth : INTEGER := 32;
220 CONSTANT sramdepth : INTEGER := 19;
221 CONSTANT sramdepth : INTEGER := 19;
221 SIGNAL ramsn : STD_LOGIC_VECTOR(srambanks-1 DOWNTO 0);
222 SIGNAL ramsn : STD_LOGIC_VECTOR(srambanks-1 DOWNTO 0);
222 -----------------------------------------------------------------------------
223 -----------------------------------------------------------------------------
223
224
224 BEGIN -- beh
225 BEGIN -- beh
225
226
226 LFR_EQM_1 : LFR_EQM
227 LFR_EQM_1 : LFR_EQM
227 GENERIC MAP (
228 GENERIC MAP (
228 Mem_use => use_RAM,
229 Mem_use => use_RAM,
229 USE_BOOTLOADER => 0,
230 USE_BOOTLOADER => 0,
230 USE_ADCDRIVER => 1,
231 USE_ADCDRIVER => 1,
231 tech => apa3e,
232 tech => apa3e,
232 tech_leon => apa3e,
233 tech_leon => apa3e,
233 DEBUG_FORCE_DATA_DMA => 0,
234 DEBUG_FORCE_DATA_DMA => 0,
234 USE_DEBUG_VECTOR => 0)
235 USE_DEBUG_VECTOR => 0)
235 PORT MAP (
236 PORT MAP (
236 clk50MHz => clk50MHz, --IN --ok
237 clk50MHz => clk50MHz, --IN --ok
237 clk49_152MHz => clk49_152MHz, --in --ok
238 clk49_152MHz => clk49_152MHz, --in --ok
238 reset => reset, --IN --ok
239 reset => reset, --IN --ok
239
240
240 TAG => TAG,
241 TAG => TAG,
241 --TAG1 => TAG1, --in
242 --TAG1 => TAG1, --in
242 --TAG3 => TAG3, --out
243 --TAG3 => TAG3, --out
243 --TAG2 => TAG2, --IN --ok
244 --TAG2 => TAG2, --IN --ok
244 --TAG4 => TAG4, --out --ok
245 --TAG4 => TAG4, --out --ok
245
246
246 address => address, --out
247 address => address, --out
247 data => data, --inout
248 data => data, --inout
248 nSRAM_MBE => nSRAM_MBE, --inout
249 nSRAM_MBE => nSRAM_MBE, --inout
249 nSRAM_E1 => nSRAM_E1, --out
250 nSRAM_E1 => nSRAM_E1, --out
250 nSRAM_E2 => nSRAM_E2, --out
251 nSRAM_E2 => nSRAM_E2, --out
251 nSRAM_W => nSRAM_W, --out
252 nSRAM_W => nSRAM_W, --out
252 nSRAM_G => nSRAM_G, --out
253 nSRAM_G => nSRAM_G, --out
253 nSRAM_BUSY => nSRAM_BUSY, --in
254 nSRAM_BUSY => nSRAM_BUSY, --in
254
255
255 spw1_en => spw1_en, --out --ok
256 spw1_en => spw1_en, --out --ok
256 spw1_din => spw1_din, --in --ok
257 spw1_din => spw1_din, --in --ok
257 spw1_sin => spw1_sin, --in --ok
258 spw1_sin => spw1_sin, --in --ok
258 spw1_dout => spw1_dout, --out --ok
259 spw1_dout => spw1_dout, --out --ok
259 spw1_sout => spw1_sout, --out --ok
260 spw1_sout => spw1_sout, --out --ok
260
261
261 spw2_en => spw2_en, --out --ok
262 spw2_en => spw2_en, --out --ok
262 spw2_din => spw2_din, --in --ok
263 spw2_din => spw2_din, --in --ok
263 spw2_sin => spw2_sin, --in --ok
264 spw2_sin => spw2_sin, --in --ok
264 spw2_dout => spw2_dout, --out --ok
265 spw2_dout => spw2_dout, --out --ok
265 spw2_sout => spw2_sout, --out --ok
266 spw2_sout => spw2_sout, --out --ok
266
267
267 bias_fail_sw => bias_fail_sw, --OUT --ok
268 bias_fail_sw => bias_fail_sw, --OUT --ok
268
269
269 ADC_OEB_bar_CH => ADC_OEB_bar_CH, --out --ok
270 ADC_OEB_bar_CH => ADC_OEB_bar_CH, --out --ok
270 ADC_smpclk => ADC_smpclk, --out --ok
271 ADC_smpclk => ADC_smpclk, --out --ok
271 ADC_data => ADC_data, --IN --ok
272 ADC_data => ADC_data, --IN --ok
272
273
273 DAC_SDO => DAC_SDO, --out --ok
274 DAC_SDO => DAC_SDO, --out --ok
274 DAC_SCK => DAC_SCK, --out --ok
275 DAC_SCK => DAC_SCK, --out --ok
275 DAC_SYNC => DAC_SYNC, --out --ok
276 DAC_SYNC => DAC_SYNC, --out --ok
276 DAC_CAL_EN => DAC_CAL_EN, --out --ok
277 DAC_CAL_EN => DAC_CAL_EN, --out --ok
277
278
278 HK_smpclk => HK_smpclk, --out --ok
279 HK_smpclk => HK_smpclk, --out --ok
279 ADC_OEB_bar_HK => ADC_OEB_bar_HK, --out --ok
280 ADC_OEB_bar_HK => ADC_OEB_bar_HK, --out --ok
280 HK_SEL => HK_SEL); --out --ok
281 HK_SEL => HK_SEL); --out --ok
281
282
282
283
283 -----------------------------------------------------------------------------
284 -----------------------------------------------------------------------------
284 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
285 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
285 clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz
286 clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz
286 -----------------------------------------------------------------------------
287 -----------------------------------------------------------------------------
287
288
288 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
289 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
289 TestModule_RHF1401_1 : TestModule_RHF1401
290 TestModule_RHF1401_1 : TestModule_RHF1401
290 GENERIC MAP (
291 GENERIC MAP (
291 freq => 2400,--24*(I*5+1),
292 freq => 2400,--24*(I*5+1),
292 amplitude => 4000,--8000/(I*5+1),
293 amplitude => 4000,--8000/(I*5+1),
293 impulsion => 0)
294 impulsion => 0)
294 PORT MAP (
295 PORT MAP (
295 ADC_smpclk => ADC_smpclk,
296 ADC_smpclk => ADC_smpclk,
296 ADC_OEB_bar => ADC_OEB_bar_CH_s(I),
297 ADC_OEB_bar => ADC_OEB_bar_CH_s(I),
297 ADC_data => ADC_data_s);
298 ADC_data => ADC_data_s);
298 --ADC_data_s <= "00" & X"190";
299 --ADC_data_s <= "00" & X"190";
299 END GENERATE MODULE_RHF1401;
300 END GENERATE MODULE_RHF1401;
300
301
301 ADC_OEB_bar_CH_s <= TRANSPORT ADC_OEB_bar_CH AFTER 10 ns;
302 ADC_OEB_bar_CH_s <= TRANSPORT ADC_OEB_bar_CH AFTER 10 ns;
302 ADC_data <= TRANSPORT ADC_data_s AFTER 35 ns;
303 ADC_data <= TRANSPORT ADC_data_s AFTER 35 ns;
303 -----------------------------------------------------------------------------
304 -----------------------------------------------------------------------------
304 PROCESS (clk50MHz, reset)
305 PROCESS (clk50MHz, reset)
305 BEGIN -- PROCESS
306 BEGIN -- PROCESS
306 IF reset = '0' THEN -- asynchronous reset (active low)
307 IF reset = '0' THEN -- asynchronous reset (active low)
307 nSRAM_BUSY <= '1';
308 nSRAM_BUSY <= '1';
308 counter_scrub_period <= 0;
309 counter_scrub_period <= 0;
309 ELSIF clk50MHz'EVENT AND clk50MHz = '1' THEN -- rising clock edge
310 ELSIF clk50MHz'EVENT AND clk50MHz = '1' THEN -- rising clock edge
310 IF SCRUB_RATE_PERIOD + SCRUB_PERIOD < counter_scrub_period THEN
311 IF SCRUB_RATE_PERIOD + SCRUB_PERIOD < counter_scrub_period THEN
311 counter_scrub_period <= 0;
312 counter_scrub_period <= 0;
312 ELSE
313 ELSE
313 counter_scrub_period <= counter_scrub_period + 1;
314 counter_scrub_period <= counter_scrub_period + 1;
314 END IF;
315 END IF;
315
316
316 IF counter_scrub_period < (SCRUB_RATE_PERIOD + SCRUB_PERIOD) - (SCRUB_PERIOD + SCRUB_BUSY_TO_SCRUB + SCRUB_SCRUB_TO_BUSY) THEN
317 IF counter_scrub_period < (SCRUB_RATE_PERIOD + SCRUB_PERIOD) - (SCRUB_PERIOD + SCRUB_BUSY_TO_SCRUB + SCRUB_SCRUB_TO_BUSY) THEN
317 nSRAM_BUSY <= '1';
318 nSRAM_BUSY <= '1';
318 ELSE
319 ELSE
319 nSRAM_BUSY <= '0';
320 nSRAM_BUSY <= '0';
320 END IF;
321 END IF;
321 END IF;
322 END IF;
322 END PROCESS;
323 END PROCESS;
323
324
324 -----------------------------------------------------------------------------
325 -----------------------------------------------------------------------------
325 -- TB
326 -- TB
326 -----------------------------------------------------------------------------
327 -----------------------------------------------------------------------------
327 TAG(1) <= TXD1;
328 TAG(1) <= TXD1;
328 TAG(2) <= '1';
329 TAG(2) <= '1';
329 RXD1 <= TAG(3);
330 RXD1 <= TAG(3);
330
331
331 PROCESS
332 PROCESS
332 CONSTANT txp : TIME := 320 ns;
333 CONSTANT txp : TIME := 320 ns;
333 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
334 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
334 BEGIN -- PROCESS
335 BEGIN -- PROCESS
335 TXD1 <= '1';
336 TXD1 <= '1';
336 reset <= '0';
337 reset <= '0';
337 WAIT FOR 500 ns;
338 WAIT FOR 500 ns;
338 reset <= '1';
339 reset <= '1';
339 WAIT FOR 100 us;
340 WAIT FOR 100 us;
340 message_simu <= "0 - UART init ";
341 message_simu <= "0 - UART init ";
341 UART_INIT(TXD1, txp);
342 UART_INIT(TXD1, txp);
342
343
343 ---------------------------------------------------------------------------
344 ---------------------------------------------------------------------------
344 -- LAUNCH leon 3 software
345 -- LAUNCH leon 3 software
345 ---------------------------------------------------------------------------
346 ---------------------------------------------------------------------------
346 message_simu <= "2- GO Leon3....";
347 message_simu <= "2- GO Leon3....";
347
348
348 -- bool dsu3plugin::configureTarget() ---------------------------------------------------------------------------------------------------------------------------
349 -- bool dsu3plugin::configureTarget() ---------------------------------------------------------------------------------------------------------------------------
349 --Force a debug break
350 --Force a debug break
350 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS);
351 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS);
351 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000ffff,(unsigned int)DSUBASEADDRESS+0x20);
352 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000ffff,(unsigned int)DSUBASEADDRESS+0x20);
352 --Clear time tag counter
353 --Clear time tag counter
353 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x8);
354 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x8);
354 --Clear ASR registers
355 --Clear ASR registers
355 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400040);
356 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400040);
356 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "01", X"00000000");
357 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "01", X"00000000");
357 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "10", X"00000000");
358 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "10", X"00000000");
358 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<0x2,(unsigned int)DSUBASEADDRESS+0x400024);
359 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<0x2,(unsigned int)DSUBASEADDRESS+0x400024);
359 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
360 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
360 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
361 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
361 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
362 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
362 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
363 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
363 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "00", X"00000000");
364 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "00", X"00000000");
364 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "01", X"00000000");
365 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "01", X"00000000");
365 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "10", X"00000000");
366 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "10", X"00000000");
366 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "11", X"00000000");
367 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "11", X"00000000");
367 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x48);
368 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x48);
368 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "11", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x000004C);
369 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "11", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x000004C);
369 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x400040);
370 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x400040);
370
371
371 IF USE_ESA_MEMCTRL = 1 THEN
372 IF USE_ESA_MEMCTRL = 1 THEN
372 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000000", X"000002FF"); --WriteRegs(uIntlist()<<0x2FF<<0xE60<<0,(unsigned int)MCTRLBASEADDRESS);
373 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000000", X"000002FF"); --WriteRegs(uIntlist()<<0x2FF<<0xE60<<0,(unsigned int)MCTRLBASEADDRESS);
373 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000001", X"00000E60");
374 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000001", X"00000E60");
374 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000010", X"00000000");
375 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000010", X"00000000");
375 END IF;
376 END IF;
376
377
377 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
378 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
378 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
379 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
379 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
380 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
380 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
381 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
381 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "01", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000FFFF,(unsigned int)DSUBASEADDRESS+0x24);
382 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "01", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000FFFF,(unsigned int)DSUBASEADDRESS+0x24);
382
383
383 --memSet(DSUBASEADDRESS+0x300000,0,1567);
384 --memSet(DSUBASEADDRESS+0x300000,0,1567);
384
385
385 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0xF30000E0<<0x00000002<<0x40000000<<0x40000000<<0x40000004<<0x1000000,(unsigned int)DSUBASEADDRESS+0x400000);
386 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0xF30000E0<<0x00000002<<0x40000000<<0x40000000<<0x40000004<<0x1000000,(unsigned int)DSUBASEADDRESS+0x400000);
386 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "01", X"F30000E0");
387 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "01", X"F30000E0");
387 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "10", X"00000002");
388 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "10", X"00000002");
388 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "11", X"40000000");
389 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "11", X"40000000");
389 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "00", X"40000000");
390 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "00", X"40000000");
390 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "01", X"40000004");
391 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "01", X"40000004");
391 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "10", X"10000000");
392 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "10", X"10000000");
392
393
393 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0x403ffff0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x300020);
394 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0x403ffff0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x300020);
394 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "01", X"00000000");
395 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "01", X"00000000");
395 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "10", X"00000000");
396 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "10", X"00000000");
396 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "11", X"00000000");
397 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "11", X"00000000");
397 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "00", X"00000000");
398 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "00", X"00000000");
398 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "01", X"00000000");
399 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "01", X"00000000");
399 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "10", X"403ffff0");
400 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "10", X"403ffff0");
400 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "11", X"00000000");
401 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "11", X"00000000");
401 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "00", X"00000000");
402 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "00", X"00000000");
402 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "01", X"00000000");
403 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "01", X"00000000");
403 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "10", X"00000000");
404 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "10", X"00000000");
404 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "11", X"00000000");
405 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "11", X"00000000");
405 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "00", X"00000000");
406 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "00", X"00000000");
406 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "01", X"00000000");
407 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "01", X"00000000");
407 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "10", X"00000000");
408 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "10", X"00000000");
408 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "11", X"00000000");
409 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "11", X"00000000");
409 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "00", X"00000000");
410 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "00", X"00000000");
410 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "01", X"00000000");
411 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "01", X"00000000");
411 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "10", X"00000000");
412 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "10", X"00000000");
412 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "11", X"00000000");
413 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "11", X"00000000");
413 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "00", X"00000000");
414 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "00", X"00000000");
414 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "01", X"00000000");
415 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "01", X"00000000");
415 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "10", X"00000000");
416 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "10", X"00000000");
416 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "11", X"00000000");
417 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "11", X"00000000");
417
418
418 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"000002EF"); --WriteRegs(uIntlist()<<0x000002EF,(unsigned int)DSUBASEADDRESS);
419 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"000002EF"); --WriteRegs(uIntlist()<<0x000002EF,(unsigned int)DSUBASEADDRESS);
419
420
420 --//Disable interrupts
421 --//Disable interrupts
421 --unsigned int APBIRQCTRLRBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x0d,0);
422 --unsigned int APBIRQCTRLRBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x0d,0);
422 --if(APBIRQCTRLRBASEADD == (unsigned int)-1)
423 --if(APBIRQCTRLRBASEADD == (unsigned int)-1)
423 -- return false;
424 -- return false;
424 --WriteRegs(uIntlist()<<0x00000000,APBIRQCTRLRBASEADD+0x040);
425 --WriteRegs(uIntlist()<<0x00000000,APBIRQCTRLRBASEADD+0x040);
425 --WriteRegs(uIntlist()<<0xFFFE0000,APBIRQCTRLRBASEADD+0x080);
426 --WriteRegs(uIntlist()<<0xFFFE0000,APBIRQCTRLRBASEADD+0x080);
426 --WriteRegs(uIntlist()<<0<<0,APBIRQCTRLRBASEADD);
427 --WriteRegs(uIntlist()<<0<<0,APBIRQCTRLRBASEADD);
427
428
428 -- //Set up timer
429 -- //Set up timer
429 --unsigned int APBTIMERBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x11,0);
430 --unsigned int APBTIMERBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x11,0);
430 --if(APBTIMERBASEADD == (unsigned int)-1)
431 --if(APBTIMERBASEADD == (unsigned int)-1)
431 -- return false;
432 -- return false;
432 --WriteRegs(uIntlist()<<0xffffffff,APBTIMERBASEADD+0x014);
433 --WriteRegs(uIntlist()<<0xffffffff,APBTIMERBASEADD+0x014);
433 --WriteRegs(uIntlist()<<0x00000018,APBTIMERBASEADD+0x04);
434 --WriteRegs(uIntlist()<<0x00000018,APBTIMERBASEADD+0x04);
434 --WriteRegs(uIntlist()<<0x00000007,APBTIMERBASEADD+0x018);
435 --WriteRegs(uIntlist()<<0x00000007,APBTIMERBASEADD+0x018);
435
436
436
437
437 ---------------------------------------------------------------------------
438 ---------------------------------------------------------------------------
438 --bool dsu3plugin::setCacheEnable(bool enabled)
439 --bool dsu3plugin::setCacheEnable(bool enabled)
439 --unsigned int DSUBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,0x01 , 0x004,0);
440 --unsigned int DSUBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,0x01 , 0x004,0);
440 --if(DSUBASEADDRESS == (unsigned int)-1) DSUBASEADDRESS = 0x90000000;
441 --if(DSUBASEADDRESS == (unsigned int)-1) DSUBASEADDRESS = 0x90000000;
441 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024);
442 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024);
442 UART_READ(TXD1, RXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00", data_read_v);--unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000);
443 UART_READ(TXD1, RXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00", data_read_v);--unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000);
443 data_read <= data_read_v;
444 data_read <= data_read_v;
444 --if(enabled){
445 --if(enabled){
445 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0001000F"); --WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000);
446 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0001000F"); --WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000);
446 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0061000F"); --WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000);
447 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0061000F"); --WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000);
447 --}else{
448 --}else{
448 --WriteRegs(uIntlist()<<((!0x0001000F)&reg),DSUBASEADDRESS+0x700000);
449 --WriteRegs(uIntlist()<<((!0x0001000F)&reg),DSUBASEADDRESS+0x700000);
449 --WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000);
450 --WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000);
450 --}
451 --}
451
452
452
453
453 -- void dsu3plugin::run() ---------------------------------------------------------------------------------------------------------------------------------------
454 -- void dsu3plugin::run() ---------------------------------------------------------------------------------------------------------------------------------------
454 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,DSUBASEADDRESS+0x020);
455 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,DSUBASEADDRESS+0x020);
455
456
456 ---------------------------------------------------------------------------
457 ---------------------------------------------------------------------------
457 --message_simu <= "1 - UART test ";
458 --message_simu <= "1 - UART test ";
458 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000010", X"0000FFFF");
459 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000010", X"0000FFFF");
459 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000A0A");
460 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000A0A");
460 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000B0B");
461 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000B0B");
461 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_GPIO & "000001", data_read_v);
462 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_GPIO & "000001", data_read_v);
462 --data_read <= data_read_v;
463 --data_read <= data_read_v;
463 --data_message <= "GPIO_data_write";
464 --data_message <= "GPIO_data_write";
464
465
465 -- UNSET the LFR reset
466 -- UNSET the LFR reset
466 message_simu <= "2 - LFR UNRESET";
467 message_simu <= "2 - LFR UNRESET";
467 UNRESET_LFR(TXD1, txp, ADDR_BASE_TIME_MANAGMENT);
468 UNRESET_LFR(TXD1, txp, ADDR_BASE_TIME_MANAGMENT);
468 --
469 --
469 message_simu <= "3 - LFR CONFIG ";
470 message_simu <= "3 - LFR CONFIG ";
470 LAUNCH_SPECTRAL_MATRIX(TXD1, RXD1, txp, ADDR_BASE_LFR,
471 LAUNCH_SPECTRAL_MATRIX(TXD1, RXD1, txp, ADDR_BASE_LFR,
471 ADDR_BUFFER_MS_F0_0,
472 ADDR_BUFFER_MS_F0_0,
472 ADDR_BUFFER_MS_F0_1,
473 ADDR_BUFFER_MS_F0_1,
473 ADDR_BUFFER_MS_F1_0,
474 ADDR_BUFFER_MS_F1_0,
474 ADDR_BUFFER_MS_F1_1,
475 ADDR_BUFFER_MS_F1_1,
475 ADDR_BUFFER_MS_F2_0,
476 ADDR_BUFFER_MS_F2_0,
476 ADDR_BUFFER_MS_F2_1);
477 ADDR_BUFFER_MS_F2_1);
477
478
478
479
479 LAUNCH_WAVEFORM_PICKER(TXD1, RXD1, txp,
480 LAUNCH_WAVEFORM_PICKER(TXD1, RXD1, txp,
480 LFR_MODE_SBM1,
481 LFR_MODE_SBM1,
481 X"7FFFFFFF", -- START DATE
482 X"7FFFFFFF", -- START DATE
482
483
483 "00000", --DATA_SHAPING ( 4 DOWNTO 0)
484 "00000", --DATA_SHAPING ( 4 DOWNTO 0)
484 X"00012BFF", --DELTA_SNAPSHOT(31 DOWNTO 0)
485 X"00012BFF", --DELTA_SNAPSHOT(31 DOWNTO 0)
485 X"0001280A", --DELTA_F0 (31 DOWNTO 0)
486 X"0001280A", --DELTA_F0 (31 DOWNTO 0)
486 X"00000007", --DELTA_F0_2 (31 DOWNTO 0)
487 X"00000007", --DELTA_F0_2 (31 DOWNTO 0)
487 X"0001283F", --DELTA_F1 (31 DOWNTO 0)
488 X"0001283F", --DELTA_F1 (31 DOWNTO 0)
488 X"000127FF", --DELTA_F2 (31 DOWNTO 0)
489 X"000127FF", --DELTA_F2 (31 DOWNTO 0)
489
490
490 ADDR_BASE_LFR,
491 ADDR_BASE_LFR,
491 ADDR_BUFFER_WFP_F0_0,
492 ADDR_BUFFER_WFP_F0_0,
492 ADDR_BUFFER_WFP_F0_1,
493 ADDR_BUFFER_WFP_F0_1,
493 ADDR_BUFFER_WFP_F1_0,
494 ADDR_BUFFER_WFP_F1_0,
494 ADDR_BUFFER_WFP_F1_1,
495 ADDR_BUFFER_WFP_F1_1,
495 ADDR_BUFFER_WFP_F2_0,
496 ADDR_BUFFER_WFP_F2_0,
496 ADDR_BUFFER_WFP_F2_1,
497 ADDR_BUFFER_WFP_F2_1,
497 ADDR_BUFFER_WFP_F3_0,
498 ADDR_BUFFER_WFP_F3_0,
498 ADDR_BUFFER_WFP_F3_1);
499 ADDR_BUFFER_WFP_F3_1);
499
500
500 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
501 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
501 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
502 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
502
503
503
504
504 ---------------------------------------------------------------------------
505 ---------------------------------------------------------------------------
505 -- CONFIG LFR 2
506 -- CONFIG LFR 2
506 ---------------------------------------------------------------------------
507 ---------------------------------------------------------------------------
507 --message_simu <= "3 - LFR2 CONFIG";
508 --message_simu <= "3 - LFR2 CONFIG";
508 --LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR_2,
509 --LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR_2,
509 -- X"40000000",
510 -- X"40000000",
510 -- X"40001000",
511 -- X"40001000",
511 -- X"40002000",
512 -- X"40002000",
512 -- X"40003000",
513 -- X"40003000",
513 -- X"40004000",
514 -- X"40004000",
514 -- X"40005000");
515 -- X"40005000");
515
516
516
517
517 --LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
518 --LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
518 -- LFR_MODE_SBM1,
519 -- LFR_MODE_SBM1,
519 -- X"7FFFFFFF", -- START DATE
520 -- X"7FFFFFFF", -- START DATE
520
521
521 -- "00000",--DATA_SHAPING ( 4 DOWNTO 0)
522 -- "00000",--DATA_SHAPING ( 4 DOWNTO 0)
522 -- X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
523 -- X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
523 -- X"0001280A",--DELTA_F0 (31 DOWNTO 0)
524 -- X"0001280A",--DELTA_F0 (31 DOWNTO 0)
524 -- X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
525 -- X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
525 -- X"0001283F",--DELTA_F1 (31 DOWNTO 0)
526 -- X"0001283F",--DELTA_F1 (31 DOWNTO 0)
526 -- X"000127FF",--DELTA_F2 (31 DOWNTO 0)
527 -- X"000127FF",--DELTA_F2 (31 DOWNTO 0)
527
528
528 -- ADDR_BASE_LFR_2,
529 -- ADDR_BASE_LFR_2,
529 -- X"40006000",
530 -- X"40006000",
530 -- X"40007000",
531 -- X"40007000",
531 -- X"40008000",
532 -- X"40008000",
532 -- X"40009000",
533 -- X"40009000",
533 -- X"4000A000",
534 -- X"4000A000",
534 -- X"4000B000",
535 -- X"4000B000",
535 -- X"4000C000",
536 -- X"4000C000",
536 -- X"4000D000");
537 -- X"4000D000");
537
538
538 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_LENGTH, X"0000000F");
539 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_LENGTH, X"0000000F");
539 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
540 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
540
541
541 ---------------------------------------------------------------------------
542 ---------------------------------------------------------------------------
542 ---------------------------------------------------------------------------
543 ---------------------------------------------------------------------------
543 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & X"5" & "10", X"FFFFFFFF");
544 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & X"5" & "10", X"FFFFFFFF");
544
545
545
546
546 message_simu <= "4 - GO GO GO !!";
547 message_simu <= "4 - GO GO GO !!";
547 data_message <= "---------------";
548 data_message <= "---------------";
548 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000");
549 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000");
549 -- UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000");
550 -- UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000");
550
551
551
552
552 data_read_v := (OTHERS => '1');
553 data_read_v := (OTHERS => '1');
553 READ_STATUS : LOOP
554 READ_STATUS : LOOP
554 data_message <= "---------------";
555 data_message <= "---------------";
555 WAIT FOR 2 ms;
556 WAIT FOR 2 ms;
556 data_message <= "READ_STATUS_SM_";
557 data_message <= "READ_STATUS_SM_";
557 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
558 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
558 --data_message <= "--------------r";
559 --data_message <= "--------------r";
559 --data_read <= data_read_v;
560 --data_read <= data_read_v;
560 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
561 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
561
562
562 data_message <= "READ_STATUS_WF_";
563 data_message <= "READ_STATUS_WF_";
563 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
564 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
564 --data_message <= "--------------r";
565 --data_message <= "--------------r";
565 --data_read <= data_read_v;
566 --data_read <= data_read_v;
566 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
567 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
567 END LOOP READ_STATUS;
568 END LOOP READ_STATUS;
568
569
569 WAIT;
570 WAIT;
570 END PROCESS;
571 END PROCESS;
571
572
572
573
573 -----------------------------------------------------------------------------
574 -----------------------------------------------------------------------------
574 PROCESS (nSRAM_W, reset)
575 PROCESS (nSRAM_W, reset)
575 BEGIN -- PROCESS
576 BEGIN -- PROCESS
576 IF reset = '0' THEN -- asynchronous reset (active low)
577 IF reset = '0' THEN -- asynchronous reset (active low)
577 data_pre_f0 <= X"00020001";
578 data_pre_f0 <= X"00020001";
578 data_pre_f1 <= X"00020001";
579 data_pre_f1 <= X"00020001";
579 data_pre_f2 <= X"00020001";
580 data_pre_f2 <= X"00020001";
580
581
581 addr_pre_f0 <= (OTHERS => '0');
582 addr_pre_f0 <= (OTHERS => '0');
582 addr_pre_f1 <= (OTHERS => '0');
583 addr_pre_f1 <= (OTHERS => '0');
583 addr_pre_f2 <= (OTHERS => '0');
584 addr_pre_f2 <= (OTHERS => '0');
584
585
585 error_wfp <= "000";
586 error_wfp <= "000";
586 error_wfp_addr <= "000";
587 error_wfp_addr <= "000";
587
588
588 sample_counter <= (0,0,0);
589 sample_counter <= (0,0,0);
589
590
590 ELSIF nSRAM_W'EVENT AND nSRAM_W = '0' THEN -- rising clock edge
591 ELSIF nSRAM_W'EVENT AND nSRAM_W = '0' THEN -- rising clock edge
591 error_wfp <= "000";
592 error_wfp <= "000";
592 error_wfp_addr <= "000";
593 error_wfp_addr <= "000";
593 -------------------------------------------------------------------------
594 -------------------------------------------------------------------------
594 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_0(20 DOWNTO 16) OR
595 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_0(20 DOWNTO 16) OR
595 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_1(20 DOWNTO 16) THEN
596 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_1(20 DOWNTO 16) THEN
596
597
597 addr_pre_f0 <= address(13 DOWNTO 0);
598 addr_pre_f0 <= address(13 DOWNTO 0);
598 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f0))+1) THEN
599 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f0))+1) THEN
599 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
600 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
600 error_wfp_addr(0) <= '1';
601 error_wfp_addr(0) <= '1';
601 END IF;
602 END IF;
602 END IF;
603 END IF;
603
604
604 data_pre_f0 <= data;
605 data_pre_f0 <= data;
605 CASE data_pre_f0 IS
606 CASE data_pre_f0 IS
606 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(0) <= '1'; END IF;
607 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(0) <= '1'; END IF;
607 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(0) <= '1'; END IF;
608 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(0) <= '1'; END IF;
608 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(0) <= '1'; END IF;
609 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(0) <= '1'; END IF;
609 WHEN OTHERS => error_wfp(0) <= '1';
610 WHEN OTHERS => error_wfp(0) <= '1';
610 END CASE;
611 END CASE;
611
612
612
613
613 END IF;
614 END IF;
614 -------------------------------------------------------------------------
615 -------------------------------------------------------------------------
615 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_0(20 DOWNTO 16) OR
616 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_0(20 DOWNTO 16) OR
616 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_1(20 DOWNTO 16) THEN
617 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_1(20 DOWNTO 16) THEN
617
618
618 addr_pre_f1 <= address(13 DOWNTO 0);
619 addr_pre_f1 <= address(13 DOWNTO 0);
619 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f1))+1) THEN
620 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f1))+1) THEN
620 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
621 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
621 error_wfp_addr(1) <= '1';
622 error_wfp_addr(1) <= '1';
622 END IF;
623 END IF;
623 END IF;
624 END IF;
624
625
625 data_pre_f1 <= data;
626 data_pre_f1 <= data;
626 CASE data_pre_f1 IS
627 CASE data_pre_f1 IS
627 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(1) <= '1'; END IF;
628 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(1) <= '1'; END IF;
628 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(1) <= '1'; END IF;
629 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(1) <= '1'; END IF;
629 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(1) <= '1'; END IF;
630 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(1) <= '1'; END IF;
630 WHEN OTHERS => error_wfp(1) <= '1';
631 WHEN OTHERS => error_wfp(1) <= '1';
631 END CASE;
632 END CASE;
632
633
633 sample(1,0 + sample_counter(1)*2) <= data(31 DOWNTO 16);
634 sample(1,0 + sample_counter(1)*2) <= data(31 DOWNTO 16);
634 sample(1,1 + sample_counter(1)*2) <= data(15 DOWNTO 0);
635 sample(1,1 + sample_counter(1)*2) <= data(15 DOWNTO 0);
635 sample_counter(1) <= (sample_counter(1) + 1) MOD 3;
636 sample_counter(1) <= (sample_counter(1) + 1) MOD 3;
636
637
637 END IF;
638 END IF;
638 -------------------------------------------------------------------------
639 -------------------------------------------------------------------------
639 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_0(20 DOWNTO 16) OR
640 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_0(20 DOWNTO 16) OR
640 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_1(20 DOWNTO 16) THEN
641 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_1(20 DOWNTO 16) THEN
641
642
642 addr_pre_f2 <= address(13 DOWNTO 0);
643 addr_pre_f2 <= address(13 DOWNTO 0);
643 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f2))+1) THEN
644 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f2))+1) THEN
644 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
645 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
645 error_wfp_addr(2) <= '1';
646 error_wfp_addr(2) <= '1';
646 END IF;
647 END IF;
647 END IF;
648 END IF;
648
649
649 data_pre_f2 <= data;
650 data_pre_f2 <= data;
650 CASE data_pre_f2 IS
651 CASE data_pre_f2 IS
651 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(2) <= '1'; END IF;
652 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(2) <= '1'; END IF;
652 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(2) <= '1'; END IF;
653 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(2) <= '1'; END IF;
653 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(2) <= '1'; END IF;
654 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(2) <= '1'; END IF;
654 WHEN OTHERS => error_wfp(2) <= '1';
655 WHEN OTHERS => error_wfp(2) <= '1';
655 END CASE;
656 END CASE;
656
657
657 sample(2,0 + sample_counter(2)*2) <= data(31 DOWNTO 16);
658 sample(2,0 + sample_counter(2)*2) <= data(31 DOWNTO 16);
658 sample(2,1 + sample_counter(2)*2) <= data(15 DOWNTO 0);
659 sample(2,1 + sample_counter(2)*2) <= data(15 DOWNTO 0);
659 sample_counter(2) <= (sample_counter(2) + 1) MOD 3;
660 sample_counter(2) <= (sample_counter(2) + 1) MOD 3;
660
661
661 END IF;
662 END IF;
662 END IF;
663 END IF;
663 END PROCESS;
664 END PROCESS;
664 -----------------------------------------------------------------------------
665 -----------------------------------------------------------------------------
665 ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1;
666 ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1;
666
667
667 sbanks : FOR k IN 0 TO srambanks-1 GENERATE
668 sbanks : FOR k IN 0 TO srambanks-1 GENERATE
668 sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE
669 sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE
669 sr0 : sram
670 sr0 : sram
670 GENERIC MAP (
671 GENERIC MAP (
671 index => i,
672 index => i,
672 abits => sramdepth,
673 abits => sramdepth,
673 fname => sramfile)
674 fname => sramfile)
674 PORT MAP (
675 PORT MAP (
675 address,
676 address,
676 data(31-i*8 DOWNTO 24-i*8),
677 data(31-i*8 DOWNTO 24-i*8),
677 ramsn(k),
678 ramsn(k),
678 nSRAM_W,
679 nSRAM_W,
679 nSRAM_G
680 nSRAM_G
680 );
681 );
681 END GENERATE;
682 END GENERATE;
682 END GENERATE;
683 END GENERATE;
683
684
684 END beh;
685 END beh;
685
686
Show file before | Show file after | Hide comments
@@ -1,656 +1,656
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 -----------------------------------------------------------------------------
51 -----------------------------------------------------------------------------
52 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
52 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
53 -- clk_50 frequency is 100 Mhz !
53 -- clk_50 frequency is 100 Mhz !
54 clk_50 : IN STD_LOGIC;
54 clk_50 : IN STD_LOGIC;
55 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
55 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
56 -----------------------------------------------------------------------------
56 -----------------------------------------------------------------------------
57 clk_49 : IN STD_LOGIC;
57 clk_49 : IN STD_LOGIC;
58 reset : IN STD_LOGIC;
58 reset : IN STD_LOGIC;
59 --BPs
59 --BPs
60 BP0 : IN STD_LOGIC;
60 BP0 : IN STD_LOGIC;
61 BP1 : IN STD_LOGIC;
61 BP1 : IN STD_LOGIC;
62 --LEDs
62 --LEDs
63 LED0 : OUT STD_LOGIC;
63 LED0 : OUT STD_LOGIC;
64 LED1 : OUT STD_LOGIC;
64 LED1 : OUT STD_LOGIC;
65 LED2 : OUT STD_LOGIC;
65 LED2 : OUT STD_LOGIC;
66 --UARTs
66 --UARTs
67 TXD1 : IN STD_LOGIC;
67 TXD1 : IN STD_LOGIC;
68 RXD1 : OUT STD_LOGIC;
68 RXD1 : OUT STD_LOGIC;
69 nCTS1 : OUT STD_LOGIC;
69 nCTS1 : OUT STD_LOGIC;
70 nRTS1 : IN STD_LOGIC;
70 nRTS1 : IN STD_LOGIC;
71
71
72 TXD2 : IN STD_LOGIC;
72 TXD2 : IN STD_LOGIC;
73 RXD2 : OUT STD_LOGIC;
73 RXD2 : OUT STD_LOGIC;
74 nCTS2 : OUT STD_LOGIC;
74 nCTS2 : OUT STD_LOGIC;
75 nDTR2 : IN STD_LOGIC;
75 nDTR2 : IN STD_LOGIC;
76 nRTS2 : IN STD_LOGIC;
76 nRTS2 : IN STD_LOGIC;
77 nDCD2 : OUT STD_LOGIC;
77 nDCD2 : OUT STD_LOGIC;
78
78
79 --EXT CONNECTOR
79 --EXT CONNECTOR
80 IO0 : INOUT STD_LOGIC;
80 IO0 : INOUT STD_LOGIC;
81 IO1 : INOUT STD_LOGIC;
81 IO1 : INOUT STD_LOGIC;
82 IO2 : INOUT STD_LOGIC;
82 IO2 : INOUT STD_LOGIC;
83 IO3 : INOUT STD_LOGIC;
83 IO3 : INOUT STD_LOGIC;
84 IO4 : INOUT STD_LOGIC;
84 IO4 : INOUT STD_LOGIC;
85 IO5 : INOUT STD_LOGIC;
85 IO5 : INOUT STD_LOGIC;
86 IO6 : INOUT STD_LOGIC;
86 IO6 : INOUT STD_LOGIC;
87 IO7 : INOUT STD_LOGIC;
87 IO7 : INOUT STD_LOGIC;
88 IO8 : INOUT STD_LOGIC;
88 IO8 : INOUT STD_LOGIC;
89 IO9 : INOUT STD_LOGIC;
89 IO9 : INOUT STD_LOGIC;
90 IO10 : INOUT STD_LOGIC;
90 IO10 : INOUT STD_LOGIC;
91 IO11 : INOUT STD_LOGIC;
91 IO11 : INOUT STD_LOGIC;
92
92
93 --SPACE WIRE
93 --SPACE WIRE
94 SPW_EN : OUT STD_LOGIC; -- 0 => off
94 SPW_EN : OUT STD_LOGIC; -- 0 => off
95 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
95 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
96 SPW_NOM_SIN : IN STD_LOGIC;
96 SPW_NOM_SIN : IN STD_LOGIC;
97 SPW_NOM_DOUT : OUT STD_LOGIC;
97 SPW_NOM_DOUT : OUT STD_LOGIC;
98 SPW_NOM_SOUT : OUT STD_LOGIC;
98 SPW_NOM_SOUT : OUT STD_LOGIC;
99 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
99 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
100 SPW_RED_SIN : IN STD_LOGIC;
100 SPW_RED_SIN : IN STD_LOGIC;
101 SPW_RED_DOUT : OUT STD_LOGIC;
101 SPW_RED_DOUT : OUT STD_LOGIC;
102 SPW_RED_SOUT : OUT STD_LOGIC;
102 SPW_RED_SOUT : OUT STD_LOGIC;
103 -- MINI LFR ADC INPUTS
103 -- MINI LFR ADC INPUTS
104 ADC_nCS : OUT STD_LOGIC;
104 ADC_nCS : OUT STD_LOGIC;
105 ADC_CLK : OUT STD_LOGIC;
105 ADC_CLK : OUT STD_LOGIC;
106 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
106 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
107
107
108 -- SRAM
108 -- SRAM
109 SRAM_nWE : OUT STD_LOGIC;
109 SRAM_nWE : OUT STD_LOGIC;
110 SRAM_CE : OUT STD_LOGIC;
110 SRAM_CE : OUT STD_LOGIC;
111 SRAM_nOE : OUT STD_LOGIC;
111 SRAM_nOE : OUT STD_LOGIC;
112 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
112 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
113 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
113 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
114 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
114 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
115 );
115 );
116
116
117 END MINI_LFR_top;
117 END MINI_LFR_top;
118
118
119
119
120 ARCHITECTURE beh OF MINI_LFR_top IS
120 ARCHITECTURE beh OF MINI_LFR_top IS
121
121
122 --==========================================================================
122 --==========================================================================
123 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
123 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
124 -- when enabled, chip enable polarity should be reversed and bank size also
124 -- when enabled, chip enable polarity should be reversed and bank size also
125 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
125 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
126 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
126 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
127 --==========================================================================
127 --==========================================================================
128 CONSTANT USE_IAP_MEMCTRL : integer := 1;
128 CONSTANT USE_IAP_MEMCTRL : integer := 1;
129 --==========================================================================
129 --==========================================================================
130
130
131 SIGNAL clk_50_s : STD_LOGIC := '0';
131 SIGNAL clk_50_s : STD_LOGIC := '0';
132 SIGNAL clk_25 : STD_LOGIC := '0';
132 SIGNAL clk_25 : STD_LOGIC := '0';
133 SIGNAL clk_24 : STD_LOGIC := '0';
133 SIGNAL clk_24 : STD_LOGIC := '0';
134 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
135 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
135 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
136 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
137 --
137 --
138 SIGNAL errorn : STD_LOGIC;
138 SIGNAL errorn : STD_LOGIC;
139 -- UART AHB ---------------------------------------------------------------
139 -- UART AHB ---------------------------------------------------------------
140 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
140 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
141 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
141 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
142
142
143 -- UART APB ---------------------------------------------------------------
143 -- UART APB ---------------------------------------------------------------
144 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
144 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
145 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
145 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
146 --
146 --
147 SIGNAL I00_s : STD_LOGIC;
147 SIGNAL I00_s : STD_LOGIC;
148
148
149 -- CONSTANTS
149 -- CONSTANTS
150 CONSTANT CFG_PADTECH : INTEGER := inferred;
150 CONSTANT CFG_PADTECH : INTEGER := inferred;
151 --
151 --
152 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
152 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
153 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
153 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
154 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
154 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
155
155
156 SIGNAL apbi_ext : apb_slv_in_type;
156 SIGNAL apbi_ext : apb_slv_in_type;
157 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
157 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
158 SIGNAL ahbi_s_ext : ahb_slv_in_type;
158 SIGNAL ahbi_s_ext : ahb_slv_in_type;
159 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
159 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
160 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
160 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
161 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
161 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
162
162
163 -- Spacewire signals
163 -- Spacewire signals
164 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
164 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
165 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
165 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
166 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
166 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
167 SIGNAL spw_rxtxclk : STD_ULOGIC;
167 SIGNAL spw_rxtxclk : STD_ULOGIC;
168 SIGNAL spw_rxclkn : STD_ULOGIC;
168 SIGNAL spw_rxclkn : STD_ULOGIC;
169 SIGNAL spw_clk : STD_LOGIC;
169 SIGNAL spw_clk : STD_LOGIC;
170 SIGNAL swni : grspw_in_type;
170 SIGNAL swni : grspw_in_type;
171 SIGNAL swno : grspw_out_type;
171 SIGNAL swno : grspw_out_type;
172 -- SIGNAL clkmn : STD_ULOGIC;
172 -- SIGNAL clkmn : STD_ULOGIC;
173 -- SIGNAL txclk : STD_ULOGIC;
173 -- SIGNAL txclk : STD_ULOGIC;
174
174
175 --GPIO
175 --GPIO
176 SIGNAL gpioi : gpio_in_type;
176 SIGNAL gpioi : gpio_in_type;
177 SIGNAL gpioo : gpio_out_type;
177 SIGNAL gpioo : gpio_out_type;
178
178
179 -- AD Converter ADS7886
179 -- AD Converter ADS7886
180 SIGNAL sample : Samples14v(7 DOWNTO 0);
180 SIGNAL sample : Samples14v(7 DOWNTO 0);
181 SIGNAL sample_s : Samples(7 DOWNTO 0);
181 SIGNAL sample_s : Samples(7 DOWNTO 0);
182 SIGNAL sample_val : STD_LOGIC;
182 SIGNAL sample_val : STD_LOGIC;
183 SIGNAL ADC_nCS_sig : STD_LOGIC;
183 SIGNAL ADC_nCS_sig : STD_LOGIC;
184 SIGNAL ADC_CLK_sig : STD_LOGIC;
184 SIGNAL ADC_CLK_sig : STD_LOGIC;
185 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
185 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
186
186
187 SIGNAL bias_fail_sw_sig : STD_LOGIC;
187 SIGNAL bias_fail_sw_sig : STD_LOGIC;
188
188
189 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
190 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
191 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
191 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
192 -----------------------------------------------------------------------------
192 -----------------------------------------------------------------------------
193
193
194 SIGNAL LFR_soft_rstn : STD_LOGIC;
194 SIGNAL LFR_soft_rstn : STD_LOGIC;
195 SIGNAL LFR_rstn : STD_LOGIC;
195 SIGNAL LFR_rstn : STD_LOGIC;
196
196
197
197
198 SIGNAL rstn_25 : STD_LOGIC;
198 SIGNAL rstn_25 : STD_LOGIC;
199 SIGNAL rstn_25_d1 : STD_LOGIC;
199 SIGNAL rstn_25_d1 : STD_LOGIC;
200 SIGNAL rstn_25_d2 : STD_LOGIC;
200 SIGNAL rstn_25_d2 : STD_LOGIC;
201 SIGNAL rstn_25_d3 : STD_LOGIC;
201 SIGNAL rstn_25_d3 : STD_LOGIC;
202
202
203 SIGNAL rstn_24 : STD_LOGIC;
203 SIGNAL rstn_24 : STD_LOGIC;
204 SIGNAL rstn_24_d1 : STD_LOGIC;
204 SIGNAL rstn_24_d1 : STD_LOGIC;
205 SIGNAL rstn_24_d2 : STD_LOGIC;
205 SIGNAL rstn_24_d2 : STD_LOGIC;
206 SIGNAL rstn_24_d3 : STD_LOGIC;
206 SIGNAL rstn_24_d3 : STD_LOGIC;
207
207
208 SIGNAL rstn_50 : STD_LOGIC;
208 SIGNAL rstn_50 : STD_LOGIC;
209 SIGNAL rstn_50_d1 : STD_LOGIC;
209 SIGNAL rstn_50_d1 : STD_LOGIC;
210 SIGNAL rstn_50_d2 : STD_LOGIC;
210 SIGNAL rstn_50_d2 : STD_LOGIC;
211 SIGNAL rstn_50_d3 : STD_LOGIC;
211 SIGNAL rstn_50_d3 : STD_LOGIC;
212
212
213 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
213 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
214 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
214 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
215
215
216 --
216 --
217 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
217 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
218
218
219 --
219 --
220 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
220 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
221 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
221 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
222
222
223 SIGNAL nSRAM_READY : STD_LOGIC;
223 SIGNAL nSRAM_READY : STD_LOGIC;
224
224
225 BEGIN -- beh
225 BEGIN -- beh
226
226
227 -----------------------------------------------------------------------------
227 -----------------------------------------------------------------------------
228 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
228 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
229 -- clk_50 frequency is 100 Mhz !
229 -- clk_50 frequency is 100 Mhz !
230 PROCESS (clk_50, reset)
230 PROCESS (clk_50, reset)
231 BEGIN -- PROCESS
231 BEGIN -- PROCESS
232 IF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
232 IF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
233 clk_50_s <= NOT clk_50_s;
233 clk_50_s <= NOT clk_50_s;
234 END IF;
234 END IF;
235 END PROCESS;
235 END PROCESS;
236 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
236 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
237 -----------------------------------------------------------------------------
237 -----------------------------------------------------------------------------
238
238
239 PROCESS (clk_50_s, reset)
239 PROCESS (clk_50_s, reset)
240 BEGIN -- PROCESS
240 BEGIN -- PROCESS
241 IF reset = '0' THEN -- asynchronous reset (active low)
241 IF reset = '0' THEN -- asynchronous reset (active low)
242 clk_25 <= '0';
242 clk_25 <= '0';
243 rstn_25 <= '0';
243 rstn_25 <= '0';
244 rstn_25_d1 <= '0';
244 rstn_25_d1 <= '0';
245 rstn_25_d2 <= '0';
245 rstn_25_d2 <= '0';
246 rstn_25_d3 <= '0';
246 rstn_25_d3 <= '0';
247 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
247 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
248 clk_25 <= NOT clk_25;
248 clk_25 <= NOT clk_25;
249 rstn_25_d1 <= '1';
249 rstn_25_d1 <= '1';
250 rstn_25_d2 <= rstn_25_d1;
250 rstn_25_d2 <= rstn_25_d1;
251 rstn_25_d3 <= rstn_25_d2;
251 rstn_25_d3 <= rstn_25_d2;
252 rstn_25 <= rstn_25_d3;
252 rstn_25 <= rstn_25_d3;
253 END IF;
253 END IF;
254 END PROCESS;
254 END PROCESS;
255
255
256 PROCESS (clk_49, reset)
256 PROCESS (clk_49, reset)
257 BEGIN -- PROCESS
257 BEGIN -- PROCESS
258 IF reset = '0' THEN -- asynchronous reset (active low)
258 IF reset = '0' THEN -- asynchronous reset (active low)
259 clk_24 <= '0';
259 clk_24 <= '0';
260 rstn_24_d1 <= '0';
260 rstn_24_d1 <= '0';
261 rstn_24_d2 <= '0';
261 rstn_24_d2 <= '0';
262 rstn_24_d3 <= '0';
262 rstn_24_d3 <= '0';
263 rstn_24 <= '0';
263 rstn_24 <= '0';
264 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
264 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
265 clk_24 <= NOT clk_24;
265 clk_24 <= NOT clk_24;
266 rstn_24_d1 <= '1';
266 rstn_24_d1 <= '1';
267 rstn_24_d2 <= rstn_24_d1;
267 rstn_24_d2 <= rstn_24_d1;
268 rstn_24_d3 <= rstn_24_d2;
268 rstn_24_d3 <= rstn_24_d2;
269 rstn_24 <= rstn_24_d3;
269 rstn_24 <= rstn_24_d3;
270 END IF;
270 END IF;
271 END PROCESS;
271 END PROCESS;
272
272
273 -----------------------------------------------------------------------------
273 -----------------------------------------------------------------------------
274
274
275 PROCESS (clk_25, rstn_25)
275 PROCESS (clk_25, rstn_25)
276 BEGIN -- PROCESS
276 BEGIN -- PROCESS
277 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
277 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
278 LED0 <= '0';
278 LED0 <= '0';
279 LED1 <= '0';
279 LED1 <= '0';
280 LED2 <= '0';
280 LED2 <= '0';
281 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
281 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
282 LED0 <= '0';
282 LED0 <= '0';
283 LED1 <= '1';
283 LED1 <= '1';
284 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
284 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
285 END IF;
285 END IF;
286 END PROCESS;
286 END PROCESS;
287
287
288 PROCESS (clk_24, rstn_24)
288 PROCESS (clk_24, rstn_24)
289 BEGIN -- PROCESS
289 BEGIN -- PROCESS
290 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
290 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
291 I00_s <= '0';
291 I00_s <= '0';
292 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
292 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
293 I00_s <= NOT I00_s;
293 I00_s <= NOT I00_s;
294 END IF;
294 END IF;
295 END PROCESS;
295 END PROCESS;
296
296
297 --UARTs
297 --UARTs
298 nCTS1 <= '1';
298 nCTS1 <= '1';
299 nCTS2 <= '1';
299 nCTS2 <= '1';
300 nDCD2 <= '1';
300 nDCD2 <= '1';
301
301
302 --
302 --
303
303
304 leon3_soc_1 : leon3_soc
304 leon3_soc_1 : leon3_soc
305 GENERIC MAP (
305 GENERIC MAP (
306 fabtech => apa3e,
306 fabtech => apa3e,
307 memtech => apa3e,
307 memtech => apa3e,
308 padtech => inferred,
308 padtech => inferred,
309 clktech => inferred,
309 clktech => inferred,
310 disas => 0,
310 disas => 0,
311 dbguart => 0,
311 dbguart => 0,
312 pclow => 2,
312 pclow => 2,
313 clk_freq => 25000,
313 clk_freq => 25000,
314 IS_RADHARD => 0,
314 IS_RADHARD => 0,
315 NB_CPU => 1,
315 NB_CPU => 1,
316 ENABLE_FPU => 1,
316 ENABLE_FPU => 1,
317 FPU_NETLIST => 0,
317 FPU_NETLIST => 0,
318 ENABLE_DSU => 1,
318 ENABLE_DSU => 1,
319 ENABLE_AHB_UART => 1,
319 ENABLE_AHB_UART => 0,
320 ENABLE_APB_UART => 1,
320 ENABLE_APB_UART => 0,
321 ENABLE_IRQMP => 1,
321 ENABLE_IRQMP => 1,
322 ENABLE_GPT => 1,
322 ENABLE_GPT => 1,
323 NB_AHB_MASTER => NB_AHB_MASTER,
323 NB_AHB_MASTER => NB_AHB_MASTER,
324 NB_AHB_SLAVE => NB_AHB_SLAVE,
324 NB_AHB_SLAVE => NB_AHB_SLAVE,
325 NB_APB_SLAVE => NB_APB_SLAVE,
325 NB_APB_SLAVE => NB_APB_SLAVE,
326 ADDRESS_SIZE => 20,
326 ADDRESS_SIZE => 20,
327 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
327 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
328 BYPASS_EDAC_MEMCTRLR => '0',
328 BYPASS_EDAC_MEMCTRLR => '0',
329 SRBANKSZ => 9)
329 SRBANKSZ => 9)
330 PORT MAP (
330 PORT MAP (
331 clk => clk_25,
331 clk => clk_25,
332 reset => rstn_25,
332 reset => rstn_25,
333 errorn => errorn,
333 errorn => errorn,
334 ahbrxd => TXD1,
334 ahbrxd => TXD1,
335 ahbtxd => RXD1,
335 ahbtxd => RXD1,
336 urxd1 => TXD2,
336 urxd1 => TXD2,
337 utxd1 => RXD2,
337 utxd1 => RXD2,
338 address => SRAM_A,
338 address => SRAM_A,
339 data => SRAM_DQ,
339 data => SRAM_DQ,
340 nSRAM_BE0 => SRAM_nBE(0),
340 nSRAM_BE0 => SRAM_nBE(0),
341 nSRAM_BE1 => SRAM_nBE(1),
341 nSRAM_BE1 => SRAM_nBE(1),
342 nSRAM_BE2 => SRAM_nBE(2),
342 nSRAM_BE2 => SRAM_nBE(2),
343 nSRAM_BE3 => SRAM_nBE(3),
343 nSRAM_BE3 => SRAM_nBE(3),
344 nSRAM_WE => SRAM_nWE,
344 nSRAM_WE => SRAM_nWE,
345 nSRAM_CE => SRAM_CE_s,
345 nSRAM_CE => SRAM_CE_s,
346 nSRAM_OE => SRAM_nOE,
346 nSRAM_OE => SRAM_nOE,
347 nSRAM_READY => nSRAM_READY,
347 nSRAM_READY => nSRAM_READY,
348 SRAM_MBE => OPEN,
348 SRAM_MBE => OPEN,
349 apbi_ext => apbi_ext,
349 apbi_ext => apbi_ext,
350 apbo_ext => apbo_ext,
350 apbo_ext => apbo_ext,
351 ahbi_s_ext => ahbi_s_ext,
351 ahbi_s_ext => ahbi_s_ext,
352 ahbo_s_ext => ahbo_s_ext,
352 ahbo_s_ext => ahbo_s_ext,
353 ahbi_m_ext => ahbi_m_ext,
353 ahbi_m_ext => ahbi_m_ext,
354 ahbo_m_ext => ahbo_m_ext);
354 ahbo_m_ext => ahbo_m_ext);
355
355
356 PROCESS (clk_25, rstn_25)
356 PROCESS (clk_25, rstn_25)
357 BEGIN -- PROCESS
357 BEGIN -- PROCESS
358 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
358 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
359 nSRAM_READY <= '1';
359 nSRAM_READY <= '1';
360 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
360 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
361 nSRAM_READY <= '1';
361 nSRAM_READY <= '1';
362 IF IO0 = '1' THEN
362 IF IO0 = '1' THEN
363 nSRAM_READY <= '0';
363 nSRAM_READY <= '0';
364 END IF;
364 END IF;
365 END IF;
365 END IF;
366 END PROCESS;
366 END PROCESS;
367
367
368
368
369
369
370 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
370 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
371 SRAM_CE <= not SRAM_CE_s(0);
371 SRAM_CE <= not SRAM_CE_s(0);
372 END GENERATE;
372 END GENERATE;
373
373
374 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
374 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
375 SRAM_CE <= SRAM_CE_s(0);
375 SRAM_CE <= SRAM_CE_s(0);
376 END GENERATE;
376 END GENERATE;
377 -------------------------------------------------------------------------------
377 -------------------------------------------------------------------------------
378 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
378 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
379 -------------------------------------------------------------------------------
379 -------------------------------------------------------------------------------
380 apb_lfr_management_1 : apb_lfr_management
380 apb_lfr_management_1 : apb_lfr_management
381 GENERIC MAP (
381 GENERIC MAP (
382 tech => apa3e,
382 tech => apa3e,
383 pindex => 6,
383 pindex => 6,
384 paddr => 6,
384 paddr => 6,
385 pmask => 16#fff#,
385 pmask => 16#fff#,
386 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
386 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
387 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
387 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
388 PORT MAP (
388 PORT MAP (
389 clk25MHz => clk_25,
389 clk25MHz => clk_25,
390 resetn_25MHz => rstn_25, -- TODO
390 resetn_25MHz => rstn_25, -- TODO
391 -- clk24_576MHz => clk_24, -- 49.152MHz/2
391 -- clk24_576MHz => clk_24, -- 49.152MHz/2
392 -- resetn_24_576MHz => rstn_24, -- TODO
392 -- resetn_24_576MHz => rstn_24, -- TODO
393 grspw_tick => swno.tickout,
393 grspw_tick => swno.tickout,
394 apbi => apbi_ext,
394 apbi => apbi_ext,
395 apbo => apbo_ext(6),
395 apbo => apbo_ext(6),
396 HK_sample => sample_hk,
396 HK_sample => sample_hk,
397 HK_val => sample_val,
397 HK_val => sample_val,
398 HK_sel => HK_SEL,
398 HK_sel => HK_SEL,
399 DAC_SDO => OPEN,
399 DAC_SDO => OPEN,
400 DAC_SCK => OPEN,
400 DAC_SCK => OPEN,
401 DAC_SYNC => OPEN,
401 DAC_SYNC => OPEN,
402 DAC_CAL_EN => OPEN,
402 DAC_CAL_EN => OPEN,
403 coarse_time => coarse_time,
403 coarse_time => coarse_time,
404 fine_time => fine_time,
404 fine_time => fine_time,
405 LFR_soft_rstn => LFR_soft_rstn
405 LFR_soft_rstn => LFR_soft_rstn
406 );
406 );
407
407
408 -----------------------------------------------------------------------
408 -----------------------------------------------------------------------
409 --- SpaceWire --------------------------------------------------------
409 --- SpaceWire --------------------------------------------------------
410 -----------------------------------------------------------------------
410 -----------------------------------------------------------------------
411
411
412 SPW_EN <= '1';
412 SPW_EN <= '1';
413
413
414 spw_clk <= clk_50_s;
414 spw_clk <= clk_50_s;
415 spw_rxtxclk <= spw_clk;
415 spw_rxtxclk <= spw_clk;
416 spw_rxclkn <= NOT spw_rxtxclk;
416 spw_rxclkn <= NOT spw_rxtxclk;
417
417
418 -- PADS for SPW1
418 -- PADS for SPW1
419 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
419 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
420 PORT MAP (SPW_NOM_DIN, dtmp(0));
420 PORT MAP (SPW_NOM_DIN, dtmp(0));
421 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
421 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
422 PORT MAP (SPW_NOM_SIN, stmp(0));
422 PORT MAP (SPW_NOM_SIN, stmp(0));
423 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
423 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
424 PORT MAP (SPW_NOM_DOUT, swno.d(0));
424 PORT MAP (SPW_NOM_DOUT, swno.d(0));
425 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
425 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
426 PORT MAP (SPW_NOM_SOUT, swno.s(0));
426 PORT MAP (SPW_NOM_SOUT, swno.s(0));
427 -- PADS FOR SPW2
427 -- PADS FOR SPW2
428 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
428 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
429 PORT MAP (SPW_RED_SIN, dtmp(1));
429 PORT MAP (SPW_RED_SIN, dtmp(1));
430 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
430 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
431 PORT MAP (SPW_RED_DIN, stmp(1));
431 PORT MAP (SPW_RED_DIN, stmp(1));
432 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
432 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
433 PORT MAP (SPW_RED_DOUT, swno.d(1));
433 PORT MAP (SPW_RED_DOUT, swno.d(1));
434 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
434 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
435 PORT MAP (SPW_RED_SOUT, swno.s(1));
435 PORT MAP (SPW_RED_SOUT, swno.s(1));
436
436
437 -- GRSPW PHY
437 -- GRSPW PHY
438 --spw1_input: if CFG_SPW_GRSPW = 1 generate
438 --spw1_input: if CFG_SPW_GRSPW = 1 generate
439 spw_inputloop : FOR j IN 0 TO 1 GENERATE
439 spw_inputloop : FOR j IN 0 TO 1 GENERATE
440 spw_phy0 : grspw_phy
440 spw_phy0 : grspw_phy
441 GENERIC MAP(
441 GENERIC MAP(
442 tech => apa3e,
442 tech => apa3e,
443 rxclkbuftype => 1,
443 rxclkbuftype => 1,
444 scantest => 0)
444 scantest => 0)
445 PORT MAP(
445 PORT MAP(
446 rxrst => swno.rxrst,
446 rxrst => swno.rxrst,
447 di => dtmp(j),
447 di => dtmp(j),
448 si => stmp(j),
448 si => stmp(j),
449 rxclko => spw_rxclk(j),
449 rxclko => spw_rxclk(j),
450 do => swni.d(j),
450 do => swni.d(j),
451 ndo => swni.nd(j*5+4 DOWNTO j*5),
451 ndo => swni.nd(j*5+4 DOWNTO j*5),
452 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
452 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
453 END GENERATE spw_inputloop;
453 END GENERATE spw_inputloop;
454
454
455 swni.rmapnodeaddr <= (OTHERS => '0');
455 swni.rmapnodeaddr <= (OTHERS => '0');
456
456
457 -- SPW core
457 -- SPW core
458 sw0 : grspwm GENERIC MAP(
458 sw0 : grspwm GENERIC MAP(
459 tech => apa3e,
459 tech => apa3e,
460 hindex => 1,
460 hindex => 1,
461 pindex => 5,
461 pindex => 5,
462 paddr => 5,
462 paddr => 5,
463 pirq => 11,
463 pirq => 11,
464 sysfreq => 25000, -- CPU_FREQ
464 sysfreq => 25000, -- CPU_FREQ
465 rmap => 1,
465 rmap => 1,
466 rmapcrc => 1,
466 rmapcrc => 1,
467 fifosize1 => 16,
467 fifosize1 => 16,
468 fifosize2 => 16,
468 fifosize2 => 16,
469 rxclkbuftype => 1,
469 rxclkbuftype => 1,
470 rxunaligned => 0,
470 rxunaligned => 0,
471 rmapbufs => 4,
471 rmapbufs => 4,
472 ft => 0,
472 ft => 0,
473 netlist => 0,
473 netlist => 0,
474 ports => 2,
474 ports => 2,
475 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
475 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
476 memtech => apa3e,
476 memtech => apa3e,
477 destkey => 2,
477 destkey => 2,
478 spwcore => 1
478 spwcore => 1
479 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
479 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
480 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
480 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
481 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
481 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
482 )
482 )
483 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
483 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
484 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
484 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
485 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
485 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
486 swni, swno);
486 swni, swno);
487
487
488 swni.tickin <= '0';
488 swni.tickin <= '0';
489 swni.rmapen <= '1';
489 swni.rmapen <= '1';
490 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
490 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
491 swni.tickinraw <= '0';
491 swni.tickinraw <= '0';
492 swni.timein <= (OTHERS => '0');
492 swni.timein <= (OTHERS => '0');
493 swni.dcrstval <= (OTHERS => '0');
493 swni.dcrstval <= (OTHERS => '0');
494 swni.timerrstval <= (OTHERS => '0');
494 swni.timerrstval <= (OTHERS => '0');
495
495
496 -------------------------------------------------------------------------------
496 -------------------------------------------------------------------------------
497 -- LFR ------------------------------------------------------------------------
497 -- LFR ------------------------------------------------------------------------
498 -------------------------------------------------------------------------------
498 -------------------------------------------------------------------------------
499
499
500
500
501 LFR_rstn <= LFR_soft_rstn AND rstn_25;
501 LFR_rstn <= LFR_soft_rstn AND rstn_25;
502 --LFR_rstn <= rstn_25;
502 --LFR_rstn <= rstn_25;
503
503
504 lpp_lfr_1 : lpp_lfr
504 lpp_lfr_1 : lpp_lfr
505 GENERIC MAP (
505 GENERIC MAP (
506 Mem_use => use_RAM,
506 Mem_use => use_RAM,
507 nb_data_by_buffer_size => 32,
507 nb_data_by_buffer_size => 32,
508 nb_snapshot_param_size => 32,
508 nb_snapshot_param_size => 32,
509 delta_vector_size => 32,
509 delta_vector_size => 32,
510 delta_vector_size_f0_2 => 7, -- log2(96)
510 delta_vector_size_f0_2 => 7, -- log2(96)
511 pindex => 15,
511 pindex => 15,
512 paddr => 15,
512 paddr => 15,
513 pmask => 16#fff#,
513 pmask => 16#fff#,
514 pirq_ms => 6,
514 pirq_ms => 6,
515 pirq_wfp => 14,
515 pirq_wfp => 14,
516 hindex => 2,
516 hindex => 2,
517 top_lfr_version => X"000146") -- aa.bb.cc version
517 top_lfr_version => X"000154") -- aa.bb.cc version
518 PORT MAP (
518 PORT MAP (
519 clk => clk_25,
519 clk => clk_25,
520 rstn => LFR_rstn,
520 rstn => LFR_rstn,
521 sample_B => sample_s(2 DOWNTO 0),
521 sample_B => sample_s(2 DOWNTO 0),
522 sample_E => sample_s(7 DOWNTO 3),
522 sample_E => sample_s(7 DOWNTO 3),
523 sample_val => sample_val,
523 sample_val => sample_val,
524 apbi => apbi_ext,
524 apbi => apbi_ext,
525 apbo => apbo_ext(15),
525 apbo => apbo_ext(15),
526 ahbi => ahbi_m_ext,
526 ahbi => ahbi_m_ext,
527 ahbo => ahbo_m_ext(2),
527 ahbo => ahbo_m_ext(2),
528 coarse_time => coarse_time,
528 coarse_time => coarse_time,
529 fine_time => fine_time,
529 fine_time => fine_time,
530 data_shaping_BW => bias_fail_sw_sig,
530 data_shaping_BW => bias_fail_sw_sig,
531 debug_vector => lfr_debug_vector,
531 debug_vector => lfr_debug_vector,
532 debug_vector_ms => lfr_debug_vector_ms
532 debug_vector_ms => lfr_debug_vector_ms
533 );
533 );
534
534
535 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
535 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
536 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
536 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
537 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
537 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
538 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
538 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
539 -- IO0 <= rstn_25;
539 -- IO0 <= rstn_25;
540 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
540 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
541 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
541 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
542 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
542 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
543 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
543 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
544 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
544 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
545 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
545 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
546 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
546 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
547
547
548 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
548 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
549 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
549 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
550 END GENERATE all_sample;
550 END GENERATE all_sample;
551
551
552 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
552 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
553 GENERIC MAP(
553 GENERIC MAP(
554 ChannelCount => 8,
554 ChannelCount => 8,
555 SampleNbBits => 14,
555 SampleNbBits => 14,
556 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
556 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
557 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
557 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
558 PORT MAP (
558 PORT MAP (
559 -- CONV
559 -- CONV
560 cnv_clk => clk_24,
560 cnv_clk => clk_24,
561 cnv_rstn => rstn_24,
561 cnv_rstn => rstn_24,
562 cnv => ADC_nCS_sig,
562 cnv => ADC_nCS_sig,
563 -- DATA
563 -- DATA
564 clk => clk_25,
564 clk => clk_25,
565 rstn => rstn_25,
565 rstn => rstn_25,
566 sck => ADC_CLK_sig,
566 sck => ADC_CLK_sig,
567 sdo => ADC_SDO_sig,
567 sdo => ADC_SDO_sig,
568 -- SAMPLE
568 -- SAMPLE
569 sample => sample,
569 sample => sample,
570 sample_val => sample_val);
570 sample_val => sample_val);
571
571
572 --IO10 <= ADC_SDO_sig(5);
572 --IO10 <= ADC_SDO_sig(5);
573 --IO9 <= ADC_SDO_sig(4);
573 --IO9 <= ADC_SDO_sig(4);
574 --IO8 <= ADC_SDO_sig(3);
574 --IO8 <= ADC_SDO_sig(3);
575
575
576 ADC_nCS <= ADC_nCS_sig;
576 ADC_nCS <= ADC_nCS_sig;
577 ADC_CLK <= ADC_CLK_sig;
577 ADC_CLK <= ADC_CLK_sig;
578 ADC_SDO_sig <= ADC_SDO;
578 ADC_SDO_sig <= ADC_SDO;
579
579
580 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
580 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
581 "0010001000100010" WHEN HK_SEL = "01" ELSE
581 "0010001000100010" WHEN HK_SEL = "01" ELSE
582 "0100010001000100" WHEN HK_SEL = "10" ELSE
582 "0100010001000100" WHEN HK_SEL = "10" ELSE
583 (OTHERS => '0');
583 (OTHERS => '0');
584
584
585
585
586 ----------------------------------------------------------------------
586 ----------------------------------------------------------------------
587 --- GPIO -----------------------------------------------------------
587 --- GPIO -----------------------------------------------------------
588 ----------------------------------------------------------------------
588 ----------------------------------------------------------------------
589
589
590 grgpio0 : grgpio
590 grgpio0 : grgpio
591 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
591 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
592 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
592 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
593
593
594 gpioi.sig_en <= (OTHERS => '0');
594 gpioi.sig_en <= (OTHERS => '0');
595 gpioi.sig_in <= (OTHERS => '0');
595 gpioi.sig_in <= (OTHERS => '0');
596 gpioi.din <= (OTHERS => '0');
596 gpioi.din <= (OTHERS => '0');
597 PROCESS (clk_25, rstn_25)
597 PROCESS (clk_25, rstn_25)
598 BEGIN -- PROCESS
598 BEGIN -- PROCESS
599 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
599 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
600 IO8 <= '0';
600 IO8 <= '0';
601 IO9 <= '0';
601 IO9 <= '0';
602 IO10 <= '0';
602 IO10 <= '0';
603 IO11 <= '0';
603 IO11 <= '0';
604 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
604 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
605 CASE gpioo.dout(2 DOWNTO 0) IS
605 CASE gpioo.dout(2 DOWNTO 0) IS
606 WHEN "011" =>
606 WHEN "011" =>
607 IO8 <= observation_reg(8);
607 IO8 <= observation_reg(8);
608 IO9 <= observation_reg(9);
608 IO9 <= observation_reg(9);
609 IO10 <= observation_reg(10);
609 IO10 <= observation_reg(10);
610 IO11 <= observation_reg(11);
610 IO11 <= observation_reg(11);
611 WHEN "001" =>
611 WHEN "001" =>
612 IO8 <= observation_reg(8 + 12);
612 IO8 <= observation_reg(8 + 12);
613 IO9 <= observation_reg(9 + 12);
613 IO9 <= observation_reg(9 + 12);
614 IO10 <= observation_reg(10 + 12);
614 IO10 <= observation_reg(10 + 12);
615 IO11 <= observation_reg(11 + 12);
615 IO11 <= observation_reg(11 + 12);
616 WHEN "010" =>
616 WHEN "010" =>
617 IO8 <= '0';
617 IO8 <= '0';
618 IO9 <= '0';
618 IO9 <= '0';
619 IO10 <= '0';
619 IO10 <= '0';
620 IO11 <= '0';
620 IO11 <= '0';
621 WHEN "000" =>
621 WHEN "000" =>
622 IO8 <= observation_vector_0(8);
622 IO8 <= observation_vector_0(8);
623 IO9 <= observation_vector_0(9);
623 IO9 <= observation_vector_0(9);
624 IO10 <= observation_vector_0(10);
624 IO10 <= observation_vector_0(10);
625 IO11 <= observation_vector_0(11);
625 IO11 <= observation_vector_0(11);
626 WHEN "100" =>
626 WHEN "100" =>
627 IO8 <= observation_vector_1(8);
627 IO8 <= observation_vector_1(8);
628 IO9 <= observation_vector_1(9);
628 IO9 <= observation_vector_1(9);
629 IO10 <= observation_vector_1(10);
629 IO10 <= observation_vector_1(10);
630 IO11 <= observation_vector_1(11);
630 IO11 <= observation_vector_1(11);
631 WHEN OTHERS => NULL;
631 WHEN OTHERS => NULL;
632 END CASE;
632 END CASE;
633
633
634 END IF;
634 END IF;
635 END PROCESS;
635 END PROCESS;
636 -----------------------------------------------------------------------------
636 -----------------------------------------------------------------------------
637 --
637 --
638 -----------------------------------------------------------------------------
638 -----------------------------------------------------------------------------
639 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
639 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
640 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
640 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
641 apbo_ext(I) <= apb_none;
641 apbo_ext(I) <= apb_none;
642 END GENERATE apbo_ext_not_used;
642 END GENERATE apbo_ext_not_used;
643 END GENERATE all_apbo_ext;
643 END GENERATE all_apbo_ext;
644
644
645
645
646 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
646 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
647 ahbo_s_ext(I) <= ahbs_none;
647 ahbo_s_ext(I) <= ahbs_none;
648 END GENERATE all_ahbo_ext;
648 END GENERATE all_ahbo_ext;
649
649
650 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
650 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
651 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
651 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
652 ahbo_m_ext(I) <= ahbm_none;
652 ahbo_m_ext(I) <= ahbm_none;
653 END GENERATE ahbo_m_ext_not_used;
653 END GENERATE ahbo_m_ext_not_used;
654 END GENERATE all_ahbo_m_ext;
654 END GENERATE all_ahbo_m_ext;
655
655
656 END beh;
656 END beh;
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@@ -1,172 +1,160
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 11:14:05 07/02/2012
5 -- Create Date: 11:14:05 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: lfr_time_management - Behavioral
7 -- Module Name: lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY lpp;
23 LIBRARY lpp;
24 USE lpp.lpp_lfr_management.ALL;
24 USE lpp.lpp_lfr_management.ALL;
25
25
26 ENTITY lfr_time_management IS
26 ENTITY lfr_time_management IS
27 GENERIC (
27 GENERIC (
28 NB_SECOND_DESYNC : INTEGER := 60);
28 NB_SECOND_DESYNC : INTEGER := 60);
29 PORT (
29 PORT (
30 clk : IN STD_LOGIC;
30 clk : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
32
32
33 tick : IN STD_LOGIC; -- transition signal information
33 tick : IN STD_LOGIC; -- transition signal information
34
34
35 new_coarsetime : IN STD_LOGIC; -- transition signal information
35 new_coarsetime : IN STD_LOGIC; -- transition signal information
36 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
36 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
37
37
38 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
38 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
39 fine_time_new : OUT STD_LOGIC;
39 fine_time_new : OUT STD_LOGIC;
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
41 coarse_time_new : OUT STD_LOGIC
41 coarse_time_new : OUT STD_LOGIC
42 );
42 );
43 END lfr_time_management;
43 END lfr_time_management;
44
44
45 ARCHITECTURE Behavioral OF lfr_time_management IS
45 ARCHITECTURE Behavioral OF lfr_time_management IS
46
46
47 SIGNAL FT_max : STD_LOGIC;
47 SIGNAL FT_max : STD_LOGIC;
48 SIGNAL FT_half : STD_LOGIC;
48 SIGNAL FT_half : STD_LOGIC;
49 SIGNAL FT_wait : STD_LOGIC;
49 SIGNAL FT_wait : STD_LOGIC;
50
50
51 TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC);
51 TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC);
52 SIGNAL state : state_fsm_time_management;
52 SIGNAL state : state_fsm_time_management;
53
53
54 SIGNAL fsm_desync : STD_LOGIC;
54 SIGNAL fsm_desync : STD_LOGIC;
55 SIGNAL fsm_transition : STD_LOGIC;
55 SIGNAL fsm_transition : STD_LOGIC;
56
56
57 SIGNAL set_TCU : STD_LOGIC;
57 SIGNAL set_TCU : STD_LOGIC;
58 SIGNAL CT_add1 : STD_LOGIC;
58 SIGNAL CT_add1 : STD_LOGIC;
59
59
60 SIGNAL new_coarsetime_reg : STD_LOGIC;
60 SIGNAL new_coarsetime_reg : STD_LOGIC;
61
61
62 BEGIN
62 BEGIN
63
63
64 -----------------------------------------------------------------------------
64 -----------------------------------------------------------------------------
65 --
65 --
66 -----------------------------------------------------------------------------
66 -----------------------------------------------------------------------------
67 PROCESS (clk, rstn)
67 PROCESS (clk, rstn)
68 BEGIN -- PROCESS
68 BEGIN -- PROCESS
69 IF rstn = '0' THEN -- asynchronous reset (active low)
69 IF rstn = '0' THEN -- asynchronous reset (active low)
70 new_coarsetime_reg <= '0';
70 new_coarsetime_reg <= '0';
71 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
71 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
72 IF new_coarsetime = '1' THEN
72 IF new_coarsetime = '1' THEN
73 new_coarsetime_reg <= '1';
73 new_coarsetime_reg <= '1';
74 ELSIF tick = '1' THEN
74 ELSIF tick = '1' THEN
75 new_coarsetime_reg <= '0';
75 new_coarsetime_reg <= '0';
76 END IF;
76 END IF;
77 END IF;
77 END IF;
78 END PROCESS;
78 END PROCESS;
79
79
80 -----------------------------------------------------------------------------
80 -----------------------------------------------------------------------------
81 -- FINE_TIME
81 -- FINE_TIME
82 -----------------------------------------------------------------------------
82 -----------------------------------------------------------------------------
83 fine_time_counter_1: fine_time_counter
83 fine_time_counter_1: fine_time_counter
84 GENERIC MAP (
84 GENERIC MAP (
85 WAITING_TIME => X"0040")
85 WAITING_TIME => X"0040")
86 PORT MAP (
86 PORT MAP (
87 clk => clk,
87 clk => clk,
88 rstn => rstn,
88 rstn => rstn,
89 tick => tick,
89 tick => tick,
90 fsm_transition => fsm_transition, -- todo
90 fsm_transition => fsm_transition, -- todo
91 FT_max => FT_max,
91 FT_max => FT_max,
92 FT_half => FT_half,
92 FT_half => FT_half,
93 FT_wait => FT_wait,
93 FT_wait => FT_wait,
94 fine_time => fine_time,
94 fine_time => fine_time,
95 fine_time_new => fine_time_new);
95 fine_time_new => fine_time_new);
96
96
97 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
98 -- COARSE_TIME
98 -- COARSE_TIME
99 -----------------------------------------------------------------------------
99 -----------------------------------------------------------------------------
100 coarse_time_counter_1: coarse_time_counter
100 coarse_time_counter_1: coarse_time_counter
101 GENERIC MAP(
101 GENERIC MAP(
102 NB_SECOND_DESYNC => NB_SECOND_DESYNC )
102 NB_SECOND_DESYNC => NB_SECOND_DESYNC )
103 PORT MAP (
103 PORT MAP (
104 clk => clk,
104 clk => clk,
105 rstn => rstn,
105 rstn => rstn,
106 tick => tick,
106 tick => tick,
107 set_TCU => set_TCU, -- todo
107 set_TCU => set_TCU, -- todo
108 new_TCU => new_coarsetime_reg,
108 new_TCU => new_coarsetime_reg,
109 set_TCU_value => coarsetime_reg, -- todo
109 set_TCU_value => coarsetime_reg, -- todo
110 CT_add1 => CT_add1, -- todo
110 CT_add1 => CT_add1, -- todo
111 fsm_desync => fsm_desync, -- todo
111 fsm_desync => fsm_desync, -- todo
112 FT_max => FT_max,
112 FT_max => FT_max,
113 coarse_time => coarse_time,
113 coarse_time => coarse_time,
114 coarse_time_new => coarse_time_new);
114 coarse_time_new => coarse_time_new);
115
115
116 -----------------------------------------------------------------------------
116 -----------------------------------------------------------------------------
117 -- FSM
117 -- FSM
118 -----------------------------------------------------------------------------
118 -----------------------------------------------------------------------------
119 fsm_desync <= '1' WHEN state = DESYNC ELSE '0';
119 fsm_desync <= '1' WHEN state = DESYNC ELSE '0';
120 fsm_transition <= '1' WHEN state = TRANSITION ELSE '0';
120 fsm_transition <= '1' WHEN state = TRANSITION ELSE '0';
121
121
122 PROCESS (clk, rstn)
122 PROCESS (clk, rstn)
123 BEGIN -- PROCESS
123 BEGIN -- PROCESS
124 IF rstn = '0' THEN -- asynchronous reset (active low)
124 IF rstn = '0' THEN -- asynchronous reset (active low)
125 state <= DESYNC;
125 state <= DESYNC;
126 set_TCU <= '0';
126 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
127 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
127 --CT_add1 <= '0';
128 set_TCU <= '0';
128 set_TCU <= '0';
129 CASE state IS
129 CASE state IS
130 WHEN DESYNC =>
130 WHEN DESYNC =>
131 IF tick = '1' THEN
131 IF tick = '1' THEN
132 state <= SYNC;
132 state <= SYNC;
133 set_TCU <= new_coarsetime_reg;
133 set_TCU <= new_coarsetime_reg;
134 --IF new_coarsetime = '0' AND FT_half = '1' THEN
135 -- CT_add1 <= '1';
136 --END IF;
137 --ELSIF FT_max = '1' THEN
138 -- CT_add1 <= '1';
139 END IF;
134 END IF;
140 WHEN TRANSITION =>
135 WHEN TRANSITION =>
141 IF tick = '1' THEN
136 IF tick = '1' THEN
142 state <= SYNC;
137 state <= SYNC;
143 set_TCU <= new_coarsetime_reg;
138 set_TCU <= new_coarsetime_reg;
144 --IF new_coarsetime = '0' THEN
145 -- CT_add1 <= '1';
146 --END IF;
147 ELSIF FT_wait = '1' THEN
139 ELSIF FT_wait = '1' THEN
148 --CT_add1 <= '1';
149 state <= DESYNC;
140 state <= DESYNC;
150 END IF;
141 END IF;
151 WHEN SYNC =>
142 WHEN SYNC =>
152 IF tick = '1' THEN
143 IF tick = '1' THEN
153 set_TCU <= new_coarsetime_reg;
144 set_TCU <= new_coarsetime_reg;
154 --IF new_coarsetime = '0' THEN
155 -- CT_add1 <= '1';
156 --END IF;
157 ELSIF FT_max = '1' THEN
145 ELSIF FT_max = '1' THEN
158 state <= TRANSITION;
146 state <= TRANSITION;
159 END IF;
147 END IF;
160 WHEN OTHERS => NULL;
148 WHEN OTHERS => NULL;
161 END CASE;
149 END CASE;
162 END IF;
150 END IF;
163 END PROCESS;
151 END PROCESS;
164
152
165
153
166 CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE
154 CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE
167 '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE
155 '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE
168 '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE
156 '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE
169 '1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE
157 '1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE
170 '1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE
158 '1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE
171 '0';
159 '0';
172 END Behavioral;
160 END Behavioral;
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@@ -1,103 +1,114
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
20 -- Mail : alexis.jeandet@member.fsf.org
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22
22
23
23
24 LIBRARY IEEE;
24 LIBRARY IEEE;
25 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.STD_LOGIC_1164.ALL;
26 USE IEEE.NUMERIC_STD.ALL;
26 USE IEEE.NUMERIC_STD.ALL;
27
27
28 ENTITY SPI_DAC_DRIVER IS
28 ENTITY SPI_DAC_DRIVER IS
29 GENERIC(
29 GENERIC(
30 datawidth : INTEGER := 16;
30 datawidth : INTEGER := 16;
31 MSBFIRST : INTEGER := 1
31 MSBFIRST : INTEGER := 1
32 );
32 );
33 PORT (
33 PORT (
34 clk : IN STD_LOGIC;
34 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36 DATA : IN STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
36 DATA : IN STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
37 SMP_CLK : IN STD_LOGIC;
37 SMP_CLK : IN STD_LOGIC;
38 SYNC : OUT STD_LOGIC;
38 SYNC : OUT STD_LOGIC;
39 DOUT : OUT STD_LOGIC;
39 DOUT : OUT STD_LOGIC;
40 SCLK : OUT STD_LOGIC
40 SCLK : OUT STD_LOGIC
41 );
41 );
42 END ENTITY SPI_DAC_DRIVER;
42 END ENTITY SPI_DAC_DRIVER;
43
43
44 ARCHITECTURE behav OF SPI_DAC_DRIVER IS
44 ARCHITECTURE behav OF SPI_DAC_DRIVER IS
45 SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
45 SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
46 SIGNAL INPUTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
46 SIGNAL INPUTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
47 SIGNAL SMP_CLK_R : STD_LOGIC := '0';
47 SIGNAL SMP_CLK_R : STD_LOGIC := '0';
48 SIGNAL shiftcnt : INTEGER := 0;
48 SIGNAL shiftcnt : INTEGER := 0;
49 SIGNAL shifting : STD_LOGIC := '0';
49 SIGNAL shifting : STD_LOGIC := '0';
50
51 SIGNAL SCLK_s : STD_LOGIC;
50 BEGIN
52 BEGIN
51
53
52
54
53 MSB : IF MSBFIRST = 1 GENERATE
55 MSB : IF MSBFIRST = 1 GENERATE
54 INPUTREG <= DATA;
56 INPUTREG <= DATA;
55 END GENERATE;
57 END GENERATE;
56
58
57 LSB : IF MSBFIRST = 0 GENERATE
59 LSB : IF MSBFIRST = 0 GENERATE
58 INPUTREG(datawidth-1 DOWNTO 0) <= DATA(0 TO datawidth-1);
60 INPUTREG(datawidth-1 DOWNTO 0) <= DATA(0 TO datawidth-1);
59 END GENERATE;
61 END GENERATE;
60
62
61 SCLK <= clk;
63 PROCESS (clk, rstn)
64 BEGIN -- PROCESS
65 IF rstn = '0' THEN -- asynchronous reset (active low)
66 SCLK_s <= '0';
67 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
68 SCLK_s <= NOT SCLK_s;
69
70 END IF;
71 END PROCESS;
72 SCLK <= SCLK_s;
62
73
63 PROCESS(clk, rstn)
74 PROCESS(clk, rstn)
64 BEGIN
75 BEGIN
65 IF rstn = '0' THEN
76 IF rstn = '0' THEN
66 SMP_CLK_R <= '0';
77 SMP_CLK_R <= '0';
67 ELSIF clk'EVENT AND clk = '1' THEN
78 ELSIF clk'EVENT AND clk = '1' THEN
68 SMP_CLK_R <= SMP_CLK;
79 SMP_CLK_R <= SMP_CLK;
69 END IF;
80 END IF;
70 END PROCESS;
81 END PROCESS;
71
82
72 PROCESS(clk, rstn)
83 PROCESS(clk, rstn)
73 BEGIN
84 BEGIN
74 IF rstn = '0' THEN
85 IF rstn = '0' THEN
75 shifting <= '0';
86 shifting <= '0';
76 SHIFTREG <= (OTHERS => '0');
87 SHIFTREG <= (OTHERS => '0');
77 SYNC <= '0';
88 SYNC <= '0';
78 shiftcnt <= 0;
89 shiftcnt <= 0;
79 DOUT <= '0';
90 DOUT <= '0';
80 ELSIF clk'EVENT AND clk = '1' THEN
91 ELSIF clk'EVENT AND clk = '1' THEN
81 DOUT <= SHIFTREG(datawidth-1);
92 DOUT <= SHIFTREG(datawidth-1);
82 IF(SMP_CLK = '1' AND SMP_CLK_R = '0') THEN
93 IF(SMP_CLK = '1' AND SMP_CLK_R = '0') THEN
83 SYNC <= '1';
94 SYNC <= '1';
84 shifting <= '1';
95 shifting <= '1';
85 ELSE
96 ELSE
86 SYNC <= '0';
97 SYNC <= '0';
87 IF shiftcnt = datawidth-1 THEN
98 IF shiftcnt = datawidth-1 THEN
88 shifting <= '0';
99 shifting <= '0';
89 END IF;
100 END IF;
90 END IF;
101 END IF;
91 IF shifting = '1' THEN
102 IF shifting = '1' THEN
92 shiftcnt <= shiftcnt + 1;
103 shiftcnt <= shiftcnt + 1;
93 SHIFTREG <= SHIFTREG (datawidth-2 DOWNTO 0) & '0';
104 SHIFTREG <= SHIFTREG (datawidth-2 DOWNTO 0) & '0';
94
105
95 ELSE
106 ELSE
96 SHIFTREG <= INPUTREG;
107 SHIFTREG <= INPUTREG;
97 shiftcnt <= 0;
108 shiftcnt <= 0;
98 END IF;
109 END IF;
99 END IF;
110 END IF;
100 END PROCESS;
111 END PROCESS;
101
112
102 END ARCHITECTURE behav;
113 END ARCHITECTURE behav;
103
114
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@@ -1,599 +1,515
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 tech : INTEGER := inferred;
28 tech : INTEGER := inferred;
29 nb_data_by_buffer_size : INTEGER := 32;
29 nb_data_by_buffer_size : INTEGER := 32;
30 nb_snapshot_param_size : INTEGER := 32;
30 nb_snapshot_param_size : INTEGER := 32;
31 delta_vector_size : INTEGER := 32;
31 delta_vector_size : INTEGER := 32;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 15;
34 pindex : INTEGER := 15;
35 paddr : INTEGER := 15;
35 paddr : INTEGER := 15;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 6;
37 pirq_ms : INTEGER := 6;
38 pirq_wfp : INTEGER := 14;
38 pirq_wfp : INTEGER := 14;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153";
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153";
43
43
44 DEBUG_FORCE_DATA_DMA : INTEGER := 0
44 DEBUG_FORCE_DATA_DMA : INTEGER := 0
45
45
46 );
46 );
47 PORT (
47 PORT (
48 clk : IN STD_LOGIC;
48 clk : IN STD_LOGIC;
49 rstn : IN STD_LOGIC;
49 rstn : IN STD_LOGIC;
50 -- SAMPLE
50 -- SAMPLE
51 sample_B : IN Samples(2 DOWNTO 0);
51 sample_B : IN Samples(2 DOWNTO 0);
52 sample_E : IN Samples(4 DOWNTO 0);
52 sample_E : IN Samples(4 DOWNTO 0);
53 sample_val : IN STD_LOGIC;
53 sample_val : IN STD_LOGIC;
54 -- APB
54 -- APB
55 apbi : IN apb_slv_in_type;
55 apbi : IN apb_slv_in_type;
56 apbo : OUT apb_slv_out_type;
56 apbo : OUT apb_slv_out_type;
57 -- AHB
57 -- AHB
58 ahbi : IN AHB_Mst_In_Type;
58 ahbi : IN AHB_Mst_In_Type;
59 ahbo : OUT AHB_Mst_Out_Type;
59 ahbo : OUT AHB_Mst_Out_Type;
60 -- TIME
60 -- TIME
61 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
61 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
62 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
62 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
63 --
63 --
64 data_shaping_BW : OUT STD_LOGIC;
64 data_shaping_BW : OUT STD_LOGIC;
65 --
65 --
66 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
67 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
68 );
68 );
69 END lpp_lfr;
69 END lpp_lfr;
70
70
71 ARCHITECTURE beh OF lpp_lfr IS
71 ARCHITECTURE beh OF lpp_lfr IS
72 SIGNAL sample_s : Samples(7 DOWNTO 0);
72 SIGNAL sample_s : Samples(7 DOWNTO 0);
73 --
73 --
74 SIGNAL data_shaping_SP0 : STD_LOGIC;
74 SIGNAL data_shaping_SP0 : STD_LOGIC;
75 SIGNAL data_shaping_SP1 : STD_LOGIC;
75 SIGNAL data_shaping_SP1 : STD_LOGIC;
76 SIGNAL data_shaping_R0 : STD_LOGIC;
76 SIGNAL data_shaping_R0 : STD_LOGIC;
77 SIGNAL data_shaping_R1 : STD_LOGIC;
77 SIGNAL data_shaping_R1 : STD_LOGIC;
78 SIGNAL data_shaping_R2 : STD_LOGIC;
78 SIGNAL data_shaping_R2 : STD_LOGIC;
79 --
79 --
80 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
80 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
81 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
81 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
83 --
83 --
84 SIGNAL sample_f0_val : STD_LOGIC;
84 SIGNAL sample_f0_val : STD_LOGIC;
85 SIGNAL sample_f1_val : STD_LOGIC;
85 SIGNAL sample_f1_val : STD_LOGIC;
86 SIGNAL sample_f2_val : STD_LOGIC;
86 SIGNAL sample_f2_val : STD_LOGIC;
87 SIGNAL sample_f3_val : STD_LOGIC;
87 SIGNAL sample_f3_val : STD_LOGIC;
88 --
88 --
89 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
89 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
90 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
90 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
91 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
91 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
92 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
92 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
93 --
93 --
94 SIGNAL sample_f0_data_sim : Samples(5 DOWNTO 0);
94 SIGNAL sample_f0_data_sim : Samples(5 DOWNTO 0);
95 SIGNAL sample_f1_data_sim : Samples(5 DOWNTO 0);
95 SIGNAL sample_f1_data_sim : Samples(5 DOWNTO 0);
96 SIGNAL sample_f2_data_sim : Samples(5 DOWNTO 0);
96 SIGNAL sample_f2_data_sim : Samples(5 DOWNTO 0);
97 SIGNAL sample_f3_data_sim : Samples(5 DOWNTO 0);
97 SIGNAL sample_f3_data_sim : Samples(5 DOWNTO 0);
98 --
98 --
99 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
99 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
100 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
100 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
102
102
103 -- SM
103 -- SM
104 SIGNAL ready_matrix_f0 : STD_LOGIC;
104 SIGNAL ready_matrix_f0 : STD_LOGIC;
105 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
105 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
106 SIGNAL ready_matrix_f1 : STD_LOGIC;
106 SIGNAL ready_matrix_f1 : STD_LOGIC;
107 SIGNAL ready_matrix_f2 : STD_LOGIC;
107 SIGNAL ready_matrix_f2 : STD_LOGIC;
108 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
108 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
109 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
109 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
110 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
110 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
111 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
111 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
112 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
112 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
113 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
113 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
114 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
114 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
115 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
116 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
116 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
117 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
117 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
118
118
119 -- WFP
119 -- WFP
120 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
120 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
121 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
122 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
122 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
123 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
123 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
124 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
124 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
125 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
125 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
126
126
127 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
127 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
128 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
128 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
129 SIGNAL enable_f0 : STD_LOGIC;
129 SIGNAL enable_f0 : STD_LOGIC;
130 SIGNAL enable_f1 : STD_LOGIC;
130 SIGNAL enable_f1 : STD_LOGIC;
131 SIGNAL enable_f2 : STD_LOGIC;
131 SIGNAL enable_f2 : STD_LOGIC;
132 SIGNAL enable_f3 : STD_LOGIC;
132 SIGNAL enable_f3 : STD_LOGIC;
133 SIGNAL burst_f0 : STD_LOGIC;
133 SIGNAL burst_f0 : STD_LOGIC;
134 SIGNAL burst_f1 : STD_LOGIC;
134 SIGNAL burst_f1 : STD_LOGIC;
135 SIGNAL burst_f2 : STD_LOGIC;
135 SIGNAL burst_f2 : STD_LOGIC;
136
136
137 --SIGNAL run : STD_LOGIC;
137 --SIGNAL run : STD_LOGIC;
138 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
138 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
139
139
140 -----------------------------------------------------------------------------
140 -----------------------------------------------------------------------------
141 --
141 --
142 -----------------------------------------------------------------------------
142 -----------------------------------------------------------------------------
143 -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
145 -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
146 --f1
147 -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
149 -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
150 --f2
151 -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
153 -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
154 --f3
155 -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
157 -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
158
143
159 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
144 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
145 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
161 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
146 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
162 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
147 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
148 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
164 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 -----------------------------------------------------------------------------
166 -- DMA RR
167 -----------------------------------------------------------------------------
168 -- SIGNAL dma_sel_valid : STD_LOGIC;
169 -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
170 -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
173
174 -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
175 -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
176
177 -----------------------------------------------------------------------------
178 -- DMA_REG
179 -----------------------------------------------------------------------------
180 -- SIGNAL ongoing_reg : STD_LOGIC;
181 -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
182 -- SIGNAL dma_send_reg : STD_LOGIC;
183 -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
184 -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
186
187
188 -----------------------------------------------------------------------------
189 -- DMA
190 -----------------------------------------------------------------------------
191 -- SIGNAL dma_send : STD_LOGIC;
192 -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
193 -- SIGNAL dma_done : STD_LOGIC;
194 -- SIGNAL dma_ren : STD_LOGIC;
195 -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
198
199 -----------------------------------------------------------------------------
200 -- MS
201 -----------------------------------------------------------------------------
202
203 -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 -- SIGNAL data_ms_valid : STD_LOGIC;
206 -- SIGNAL data_ms_valid_burst : STD_LOGIC;
207 -- SIGNAL data_ms_ren : STD_LOGIC;
208 -- SIGNAL data_ms_done : STD_LOGIC;
209 -- SIGNAL dma_ms_ongoing : STD_LOGIC;
210
211 -- SIGNAL run_ms : STD_LOGIC;
212 -- SIGNAL ms_softandhard_rstn : STD_LOGIC;
213
150
214 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
151 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
215 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
216 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
152 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
217 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
153 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
218
154
219
155
220 SIGNAL error_buffer_full : STD_LOGIC;
156 SIGNAL error_buffer_full : STD_LOGIC;
221 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
157 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
222
158
223 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
225
226 -----------------------------------------------------------------------------
159 -----------------------------------------------------------------------------
227 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
160 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
228 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
161 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
229 SIGNAL dma_fifo_data_forced_gen : STD_LOGIC_VECTOR(32-1 DOWNTO 0); --21-04-2015
162 SIGNAL dma_fifo_data_forced_gen : STD_LOGIC_VECTOR(32-1 DOWNTO 0); --21-04-2015
230 SIGNAL dma_fifo_data_forced : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
163 SIGNAL dma_fifo_data_forced : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
231 SIGNAL dma_fifo_data_debug : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
164 SIGNAL dma_fifo_data_debug : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
232 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
233 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
234 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
167 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
235 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
168 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
236 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
169 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
237 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
170 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 SIGNAL dma_grant_error : STD_LOGIC;
171 SIGNAL dma_grant_error : STD_LOGIC;
239
172
240 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
173 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
241 -----------------------------------------------------------------------------
174 -----------------------------------------------------------------------------
242 SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
175 SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
243 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
244 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
245 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
178 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
246 SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
247
180
248 BEGIN
181 BEGIN
249
182
250 --apb_reg_debug_vector;
251 -----------------------------------------------------------------------------
183 -----------------------------------------------------------------------------
252
184
253 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
185 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
254 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
186 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
255 sample_time <= coarse_time & fine_time;
187 sample_time <= coarse_time & fine_time;
256
188
257 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
258 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
259 --END GENERATE all_channel;
260
261 -----------------------------------------------------------------------------
189 -----------------------------------------------------------------------------
262 lpp_lfr_filter_1 : lpp_lfr_filter
190 lpp_lfr_filter_1 : lpp_lfr_filter
263 GENERIC MAP (
191 GENERIC MAP (
264 Mem_use => Mem_use)
192 Mem_use => Mem_use)
265 PORT MAP (
193 PORT MAP (
266 sample => sample_s,
194 sample => sample_s,
267 sample_val => sample_val,
195 sample_val => sample_val,
268 sample_time => sample_time,
196 sample_time => sample_time,
269 clk => clk,
197 clk => clk,
270 rstn => rstn,
198 rstn => rstn,
271 data_shaping_SP0 => data_shaping_SP0,
199 data_shaping_SP0 => data_shaping_SP0,
272 data_shaping_SP1 => data_shaping_SP1,
200 data_shaping_SP1 => data_shaping_SP1,
273 data_shaping_R0 => data_shaping_R0,
201 data_shaping_R0 => data_shaping_R0,
274 data_shaping_R1 => data_shaping_R1,
202 data_shaping_R1 => data_shaping_R1,
275 data_shaping_R2 => data_shaping_R2,
203 data_shaping_R2 => data_shaping_R2,
276 sample_f0_val => sample_f0_val,
204 sample_f0_val => sample_f0_val,
277 sample_f1_val => sample_f1_val,
205 sample_f1_val => sample_f1_val,
278 sample_f2_val => sample_f2_val,
206 sample_f2_val => sample_f2_val,
279 sample_f3_val => sample_f3_val,
207 sample_f3_val => sample_f3_val,
280 sample_f0_wdata => sample_f0_data,
208 sample_f0_wdata => sample_f0_data,
281 sample_f1_wdata => sample_f1_data,
209 sample_f1_wdata => sample_f1_data,
282 sample_f2_wdata => sample_f2_data,
210 sample_f2_wdata => sample_f2_data,
283 sample_f3_wdata => sample_f3_data,
211 sample_f3_wdata => sample_f3_data,
284 sample_f0_time => sample_f0_time,
212 sample_f0_time => sample_f0_time,
285 sample_f1_time => sample_f1_time,
213 sample_f1_time => sample_f1_time,
286 sample_f2_time => sample_f2_time,
214 sample_f2_time => sample_f2_time,
287 sample_f3_time => sample_f3_time
215 sample_f3_time => sample_f3_time
288 );
216 );
289
217
290 -----------------------------------------------------------------------------
218 -----------------------------------------------------------------------------
291 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
219 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
292 GENERIC MAP (
220 GENERIC MAP (
293 nb_data_by_buffer_size => nb_data_by_buffer_size,
221 nb_data_by_buffer_size => nb_data_by_buffer_size,
294 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
295 nb_snapshot_param_size => nb_snapshot_param_size,
222 nb_snapshot_param_size => nb_snapshot_param_size,
296 delta_vector_size => delta_vector_size,
223 delta_vector_size => delta_vector_size,
297 delta_vector_size_f0_2 => delta_vector_size_f0_2,
224 delta_vector_size_f0_2 => delta_vector_size_f0_2,
298 pindex => pindex,
225 pindex => pindex,
299 paddr => paddr,
226 paddr => paddr,
300 pmask => pmask,
227 pmask => pmask,
301 pirq_ms => pirq_ms,
228 pirq_ms => pirq_ms,
302 pirq_wfp => pirq_wfp,
229 pirq_wfp => pirq_wfp,
303 top_lfr_version => top_lfr_version)
230 top_lfr_version => top_lfr_version)
304 PORT MAP (
231 PORT MAP (
305 HCLK => clk,
232 HCLK => clk,
306 HRESETn => rstn,
233 HRESETn => rstn,
307 apbi => apbi,
234 apbi => apbi,
308 apbo => apbo,
235 apbo => apbo,
309
236
310 run_ms => OPEN,--run_ms,
237 run_ms => OPEN,--run_ms,
311
238
312 ready_matrix_f0 => ready_matrix_f0,
239 ready_matrix_f0 => ready_matrix_f0,
313 ready_matrix_f1 => ready_matrix_f1,
240 ready_matrix_f1 => ready_matrix_f1,
314 ready_matrix_f2 => ready_matrix_f2,
241 ready_matrix_f2 => ready_matrix_f2,
315 error_buffer_full => error_buffer_full, -- TODO
242 error_buffer_full => error_buffer_full,
316 error_input_fifo_write => error_input_fifo_write, -- TODO
243 error_input_fifo_write => error_input_fifo_write,
317 status_ready_matrix_f0 => status_ready_matrix_f0,
244 status_ready_matrix_f0 => status_ready_matrix_f0,
318 status_ready_matrix_f1 => status_ready_matrix_f1,
245 status_ready_matrix_f1 => status_ready_matrix_f1,
319 status_ready_matrix_f2 => status_ready_matrix_f2,
246 status_ready_matrix_f2 => status_ready_matrix_f2,
320
247
321 matrix_time_f0 => matrix_time_f0,
248 matrix_time_f0 => matrix_time_f0,
322 matrix_time_f1 => matrix_time_f1,
249 matrix_time_f1 => matrix_time_f1,
323 matrix_time_f2 => matrix_time_f2,
250 matrix_time_f2 => matrix_time_f2,
324
251
325 addr_matrix_f0 => addr_matrix_f0,
252 addr_matrix_f0 => addr_matrix_f0,
326 addr_matrix_f1 => addr_matrix_f1,
253 addr_matrix_f1 => addr_matrix_f1,
327 addr_matrix_f2 => addr_matrix_f2,
254 addr_matrix_f2 => addr_matrix_f2,
328
255
329 length_matrix_f0 => length_matrix_f0,
256 length_matrix_f0 => length_matrix_f0,
330 length_matrix_f1 => length_matrix_f1,
257 length_matrix_f1 => length_matrix_f1,
331 length_matrix_f2 => length_matrix_f2,
258 length_matrix_f2 => length_matrix_f2,
332 -------------------------------------------------------------------------
333 --status_full => status_full, -- TODo
334 --status_full_ack => status_full_ack, -- TODo
335 --status_full_err => status_full_err, -- TODo
336 status_new_err => status_new_err,
259 status_new_err => status_new_err,
337 data_shaping_BW => data_shaping_BW,
260 data_shaping_BW => data_shaping_BW,
338 data_shaping_SP0 => data_shaping_SP0,
261 data_shaping_SP0 => data_shaping_SP0,
339 data_shaping_SP1 => data_shaping_SP1,
262 data_shaping_SP1 => data_shaping_SP1,
340 data_shaping_R0 => data_shaping_R0,
263 data_shaping_R0 => data_shaping_R0,
341 data_shaping_R1 => data_shaping_R1,
264 data_shaping_R1 => data_shaping_R1,
342 data_shaping_R2 => data_shaping_R2,
265 data_shaping_R2 => data_shaping_R2,
343 delta_snapshot => delta_snapshot,
266 delta_snapshot => delta_snapshot,
344 delta_f0 => delta_f0,
267 delta_f0 => delta_f0,
345 delta_f0_2 => delta_f0_2,
268 delta_f0_2 => delta_f0_2,
346 delta_f1 => delta_f1,
269 delta_f1 => delta_f1,
347 delta_f2 => delta_f2,
270 delta_f2 => delta_f2,
348 nb_data_by_buffer => nb_data_by_buffer,
271 nb_data_by_buffer => nb_data_by_buffer,
349 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
350 nb_snapshot_param => nb_snapshot_param,
272 nb_snapshot_param => nb_snapshot_param,
351 enable_f0 => enable_f0,
273 enable_f0 => enable_f0,
352 enable_f1 => enable_f1,
274 enable_f1 => enable_f1,
353 enable_f2 => enable_f2,
275 enable_f2 => enable_f2,
354 enable_f3 => enable_f3,
276 enable_f3 => enable_f3,
355 burst_f0 => burst_f0,
277 burst_f0 => burst_f0,
356 burst_f1 => burst_f1,
278 burst_f1 => burst_f1,
357 burst_f2 => burst_f2,
279 burst_f2 => burst_f2,
358 run => OPEN, --run,
280 run => OPEN,
359 start_date => start_date,
281 start_date => start_date,
360 -- debug_signal => debug_signal,
282 wfp_status_buffer_ready => wfp_status_buffer_ready,
361 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
283 wfp_addr_buffer => wfp_addr_buffer,
362 wfp_addr_buffer => wfp_addr_buffer,-- TODO
284 wfp_length_buffer => wfp_length_buffer,
363 wfp_length_buffer => wfp_length_buffer,-- TODO
364
285
365 wfp_ready_buffer => wfp_ready_buffer,-- TODO
286 wfp_ready_buffer => wfp_ready_buffer,
366 wfp_buffer_time => wfp_buffer_time,-- TODO
287 wfp_buffer_time => wfp_buffer_time,
367 wfp_error_buffer_full => wfp_error_buffer_full, -- TODO
288 wfp_error_buffer_full => wfp_error_buffer_full,
368 -------------------------------------------------------------------------
289 -------------------------------------------------------------------------
369 sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
290 sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
370 sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
291 sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
371 sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16),
292 sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16),
372 sample_f3_valid => sample_f3_val,
293 sample_f3_valid => sample_f3_val,
373 debug_vector => apb_reg_debug_vector
294 debug_vector => apb_reg_debug_vector
374 );
295 );
375
296
376 -----------------------------------------------------------------------------
297 -----------------------------------------------------------------------------
377 -----------------------------------------------------------------------------
298 -----------------------------------------------------------------------------
378 lpp_waveform_1 : lpp_waveform
299 lpp_waveform_1 : lpp_waveform
379 GENERIC MAP (
300 GENERIC MAP (
380 tech => tech,
301 tech => tech,
381 data_size => 6*16,
302 data_size => 6*16,
382 nb_data_by_buffer_size => nb_data_by_buffer_size,
303 nb_data_by_buffer_size => nb_data_by_buffer_size,
383 nb_snapshot_param_size => nb_snapshot_param_size,
304 nb_snapshot_param_size => nb_snapshot_param_size,
384 delta_vector_size => delta_vector_size,
305 delta_vector_size => delta_vector_size,
385 delta_vector_size_f0_2 => delta_vector_size_f0_2
306 delta_vector_size_f0_2 => delta_vector_size_f0_2
386 )
307 )
387 PORT MAP (
308 PORT MAP (
388 clk => clk,
309 clk => clk,
389 rstn => rstn,
310 rstn => rstn,
390
311
391 reg_run => '1',--run,
312 reg_run => '1',--run,
392 reg_start_date => start_date,
313 reg_start_date => start_date,
393 reg_delta_snapshot => delta_snapshot,
314 reg_delta_snapshot => delta_snapshot,
394 reg_delta_f0 => delta_f0,
315 reg_delta_f0 => delta_f0,
395 reg_delta_f0_2 => delta_f0_2,
316 reg_delta_f0_2 => delta_f0_2,
396 reg_delta_f1 => delta_f1,
317 reg_delta_f1 => delta_f1,
397 reg_delta_f2 => delta_f2,
318 reg_delta_f2 => delta_f2,
398
319
399 enable_f0 => enable_f0,
320 enable_f0 => enable_f0,
400 enable_f1 => enable_f1,
321 enable_f1 => enable_f1,
401 enable_f2 => enable_f2,
322 enable_f2 => enable_f2,
402 enable_f3 => enable_f3,
323 enable_f3 => enable_f3,
403 burst_f0 => burst_f0,
324 burst_f0 => burst_f0,
404 burst_f1 => burst_f1,
325 burst_f1 => burst_f1,
405 burst_f2 => burst_f2,
326 burst_f2 => burst_f2,
406
327
407 nb_data_by_buffer => nb_data_by_buffer,
328 nb_data_by_buffer => nb_data_by_buffer,
408 nb_snapshot_param => nb_snapshot_param,
329 nb_snapshot_param => nb_snapshot_param,
409 status_new_err => status_new_err,
330 status_new_err => status_new_err,
410
331
411 status_buffer_ready => wfp_status_buffer_ready,
332 status_buffer_ready => wfp_status_buffer_ready,
412 addr_buffer => wfp_addr_buffer,
333 addr_buffer => wfp_addr_buffer,
413 length_buffer => wfp_length_buffer,
334 length_buffer => wfp_length_buffer,
414 ready_buffer => wfp_ready_buffer,
335 ready_buffer => wfp_ready_buffer,
415 buffer_time => wfp_buffer_time,
336 buffer_time => wfp_buffer_time,
416 error_buffer_full => wfp_error_buffer_full,
337 error_buffer_full => wfp_error_buffer_full,
417
338
418 coarse_time => coarse_time,
339 coarse_time => coarse_time,
419 -- fine_time => fine_time,
340 -- fine_time => fine_time,
420
341
421 --f0
342 --f0
422 data_f0_in_valid => sample_f0_val,
343 data_f0_in_valid => sample_f0_val,
423 data_f0_in => sample_f0_data,
344 data_f0_in => sample_f0_data,
424 data_f0_time => sample_f0_time,
345 data_f0_time => sample_f0_time,
425 --f1
346 --f1
426 data_f1_in_valid => sample_f1_val,
347 data_f1_in_valid => sample_f1_val,
427 data_f1_in => sample_f1_data,
348 data_f1_in => sample_f1_data,
428 data_f1_time => sample_f1_time,
349 data_f1_time => sample_f1_time,
429 --f2
350 --f2
430 data_f2_in_valid => sample_f2_val,
351 data_f2_in_valid => sample_f2_val,
431 data_f2_in => sample_f2_data,
352 data_f2_in => sample_f2_data,
432 data_f2_time => sample_f2_time,
353 data_f2_time => sample_f2_time,
433 --f3
354 --f3
434 data_f3_in_valid => sample_f3_val,
355 data_f3_in_valid => sample_f3_val,
435 data_f3_in => sample_f3_data,
356 data_f3_in => sample_f3_data,
436 data_f3_time => sample_f3_time,
357 data_f3_time => sample_f3_time,
437 -- OUTPUT -- DMA interface
358 -- OUTPUT -- DMA interface
438
359
439 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
360 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
440 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
361 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
441 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
362 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
442 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
363 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
443 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
364 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
444 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
365 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
445 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
366 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
446 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
367 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
447
368
448 );
369 );
449
370
450 -----------------------------------------------------------------------------
371 -----------------------------------------------------------------------------
451 -- Matrix Spectral
372 -- Matrix Spectral
452 -----------------------------------------------------------------------------
373 -----------------------------------------------------------------------------
453 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
374 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
454 NOT(sample_f0_val) & NOT(sample_f0_val);
375 NOT(sample_f0_val) & NOT(sample_f0_val);
455 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
376 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
456 NOT(sample_f1_val) & NOT(sample_f1_val);
377 NOT(sample_f1_val) & NOT(sample_f1_val);
457 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
378 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
458 NOT(sample_f2_val) & NOT(sample_f2_val);
379 NOT(sample_f2_val) & NOT(sample_f2_val);
459
380
460
381
461 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
382 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
462 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
383 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
463 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
384 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
464
385
465 -------------------------------------------------------------------------------
466
467 --ms_softandhard_rstn <= rstn AND run_ms AND run;
468
469 -----------------------------------------------------------------------------
386 -----------------------------------------------------------------------------
470 lpp_lfr_ms_1 : lpp_lfr_ms
387 lpp_lfr_ms_1 : lpp_lfr_ms
471 GENERIC MAP (
388 GENERIC MAP (
472 Mem_use => Mem_use)
389 Mem_use => Mem_use)
473 PORT MAP (
390 PORT MAP (
474 clk => clk,
391 clk => clk,
475 --rstn => ms_softandhard_rstn, --rstn,
476 rstn => rstn,
392 rstn => rstn,
477
393
478 run => '1',--run_ms,
394 run => '1',--run_ms,
479
395
480 start_date => start_date,
396 start_date => start_date,
481
397
482 coarse_time => coarse_time,
398 coarse_time => coarse_time,
483
399
484 sample_f0_wen => sample_f0_wen,
400 sample_f0_wen => sample_f0_wen,
485 sample_f0_wdata => sample_f0_wdata,
401 sample_f0_wdata => sample_f0_wdata,
486 sample_f0_time => sample_f0_time,
402 sample_f0_time => sample_f0_time,
487 sample_f1_wen => sample_f1_wen,
403 sample_f1_wen => sample_f1_wen,
488 sample_f1_wdata => sample_f1_wdata,
404 sample_f1_wdata => sample_f1_wdata,
489 sample_f1_time => sample_f1_time,
405 sample_f1_time => sample_f1_time,
490 sample_f2_wen => sample_f2_wen,
406 sample_f2_wen => sample_f2_wen,
491 sample_f2_wdata => sample_f2_wdata,
407 sample_f2_wdata => sample_f2_wdata,
492 sample_f2_time => sample_f2_time,
408 sample_f2_time => sample_f2_time,
493
409
494 --DMA
410 --DMA
495 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
411 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
496 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
412 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
497 dma_fifo_ren => dma_fifo_ren(4), -- IN
413 dma_fifo_ren => dma_fifo_ren(4), -- IN
498 dma_buffer_new => dma_buffer_new(4), -- OUT
414 dma_buffer_new => dma_buffer_new(4), -- OUT
499 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
415 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
500 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
416 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
501 dma_buffer_full => dma_buffer_full(4), -- IN
417 dma_buffer_full => dma_buffer_full(4), -- IN
502 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
418 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
503
419
504
420
505
421
506 --REG
422 --REG
507 ready_matrix_f0 => ready_matrix_f0,
423 ready_matrix_f0 => ready_matrix_f0,
508 ready_matrix_f1 => ready_matrix_f1,
424 ready_matrix_f1 => ready_matrix_f1,
509 ready_matrix_f2 => ready_matrix_f2,
425 ready_matrix_f2 => ready_matrix_f2,
510 error_buffer_full => error_buffer_full,
426 error_buffer_full => error_buffer_full,
511 error_input_fifo_write => error_input_fifo_write,
427 error_input_fifo_write => error_input_fifo_write,
512
428
513 status_ready_matrix_f0 => status_ready_matrix_f0,
429 status_ready_matrix_f0 => status_ready_matrix_f0,
514 status_ready_matrix_f1 => status_ready_matrix_f1,
430 status_ready_matrix_f1 => status_ready_matrix_f1,
515 status_ready_matrix_f2 => status_ready_matrix_f2,
431 status_ready_matrix_f2 => status_ready_matrix_f2,
516 addr_matrix_f0 => addr_matrix_f0,
432 addr_matrix_f0 => addr_matrix_f0,
517 addr_matrix_f1 => addr_matrix_f1,
433 addr_matrix_f1 => addr_matrix_f1,
518 addr_matrix_f2 => addr_matrix_f2,
434 addr_matrix_f2 => addr_matrix_f2,
519
435
520 length_matrix_f0 => length_matrix_f0,
436 length_matrix_f0 => length_matrix_f0,
521 length_matrix_f1 => length_matrix_f1,
437 length_matrix_f1 => length_matrix_f1,
522 length_matrix_f2 => length_matrix_f2,
438 length_matrix_f2 => length_matrix_f2,
523
439
524 matrix_time_f0 => matrix_time_f0,
440 matrix_time_f0 => matrix_time_f0,
525 matrix_time_f1 => matrix_time_f1,
441 matrix_time_f1 => matrix_time_f1,
526 matrix_time_f2 => matrix_time_f2,
442 matrix_time_f2 => matrix_time_f2,
527
443
528 debug_vector => debug_vector_ms);
444 debug_vector => debug_vector_ms);
529
445
530 -----------------------------------------------------------------------------
446 -----------------------------------------------------------------------------
531 PROCESS (clk, rstn)
447 PROCESS (clk, rstn)
532 BEGIN
448 BEGIN
533 IF rstn = '0' THEN
449 IF rstn = '0' THEN
534 dma_fifo_data_forced_gen <= X"00040003";
450 dma_fifo_data_forced_gen <= X"00040003";
535 ELSIF clk'event AND clk = '1' THEN
451 ELSIF clk'event AND clk = '1' THEN
536 IF dma_fifo_ren(0) = '0' THEN
452 IF dma_fifo_ren(0) = '0' THEN
537 CASE dma_fifo_data_forced_gen IS
453 CASE dma_fifo_data_forced_gen IS
538 WHEN X"00040003" => dma_fifo_data_forced_gen <= X"00050002";
454 WHEN X"00040003" => dma_fifo_data_forced_gen <= X"00050002";
539 WHEN X"00050002" => dma_fifo_data_forced_gen <= X"00060001";
455 WHEN X"00050002" => dma_fifo_data_forced_gen <= X"00060001";
540 WHEN X"00060001" => dma_fifo_data_forced_gen <= X"00040003";
456 WHEN X"00060001" => dma_fifo_data_forced_gen <= X"00040003";
541 WHEN OTHERS => NULL;
457 WHEN OTHERS => NULL;
542 END CASE;
458 END CASE;
543 END IF;
459 END IF;
544 END IF;
460 END IF;
545 END PROCESS;
461 END PROCESS;
546
462
547 dma_fifo_data_forced(32 * 1 -1 DOWNTO 32 * 0) <= dma_fifo_data_forced_gen;
463 dma_fifo_data_forced(32 * 1 -1 DOWNTO 32 * 0) <= dma_fifo_data_forced_gen;
548 dma_fifo_data_forced(32 * 2 -1 DOWNTO 32 * 1) <= X"A0000100";
464 dma_fifo_data_forced(32 * 2 -1 DOWNTO 32 * 1) <= X"A0000100";
549 dma_fifo_data_forced(32 * 3 -1 DOWNTO 32 * 2) <= X"08001000";
465 dma_fifo_data_forced(32 * 3 -1 DOWNTO 32 * 2) <= X"08001000";
550 dma_fifo_data_forced(32 * 4 -1 DOWNTO 32 * 3) <= X"80007000";
466 dma_fifo_data_forced(32 * 4 -1 DOWNTO 32 * 3) <= X"80007000";
551 dma_fifo_data_forced(32 * 5 -1 DOWNTO 32 * 4) <= X"0A000B00";
467 dma_fifo_data_forced(32 * 5 -1 DOWNTO 32 * 4) <= X"0A000B00";
552
468
553 dma_fifo_data_debug <= dma_fifo_data WHEN DEBUG_FORCE_DATA_DMA = 0 ELSE dma_fifo_data_forced;
469 dma_fifo_data_debug <= dma_fifo_data WHEN DEBUG_FORCE_DATA_DMA = 0 ELSE dma_fifo_data_forced;
554
470
555 DMA_SubSystem_1 : DMA_SubSystem
471 DMA_SubSystem_1 : DMA_SubSystem
556 GENERIC MAP (
472 GENERIC MAP (
557 hindex => hindex,
473 hindex => hindex,
558 CUSTOM_DMA => 1)
474 CUSTOM_DMA => 1)
559 PORT MAP (
475 PORT MAP (
560 clk => clk,
476 clk => clk,
561 rstn => rstn,
477 rstn => rstn,
562 run => '1',--run_dma,
478 run => '1',--run_dma,
563 ahbi => ahbi,
479 ahbi => ahbi,
564 ahbo => ahbo,
480 ahbo => ahbo,
565
481
566 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
482 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
567 fifo_data => dma_fifo_data_debug, --fifo_data,
483 fifo_data => dma_fifo_data_debug, --fifo_data,
568 fifo_ren => dma_fifo_ren, --fifo_ren,
484 fifo_ren => dma_fifo_ren, --fifo_ren,
569
485
570 buffer_new => dma_buffer_new, --buffer_new,
486 buffer_new => dma_buffer_new, --buffer_new,
571 buffer_addr => dma_buffer_addr, --buffer_addr,
487 buffer_addr => dma_buffer_addr, --buffer_addr,
572 buffer_length => dma_buffer_length, --buffer_length,
488 buffer_length => dma_buffer_length, --buffer_length,
573 buffer_full => dma_buffer_full, --buffer_full,
489 buffer_full => dma_buffer_full, --buffer_full,
574 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
490 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
575 grant_error => dma_grant_error,
491 grant_error => dma_grant_error,
576 debug_vector => debug_vector(8 DOWNTO 0)
492 debug_vector => debug_vector(8 DOWNTO 0)
577 ); --grant_error);
493 ); --grant_error);
578
494
579 -----------------------------------------------------------------------------
495 -----------------------------------------------------------------------------
580 -- OBSERVATION for SIMULATION
496 -- OBSERVATION for SIMULATION
581 all_channel_sim: FOR I IN 0 TO 5 GENERATE
497 all_channel_sim: FOR I IN 0 TO 5 GENERATE
582 PROCESS (clk, rstn)
498 PROCESS (clk, rstn)
583 BEGIN -- PROCESS
499 BEGIN -- PROCESS
584 IF rstn = '0' THEN -- asynchronous reset (active low)
500 IF rstn = '0' THEN -- asynchronous reset (active low)
585 sample_f0_data_sim(I) <= (OTHERS => '0');
501 sample_f0_data_sim(I) <= (OTHERS => '0');
586 sample_f1_data_sim(I) <= (OTHERS => '0');
502 sample_f1_data_sim(I) <= (OTHERS => '0');
587 sample_f2_data_sim(I) <= (OTHERS => '0');
503 sample_f2_data_sim(I) <= (OTHERS => '0');
588 sample_f3_data_sim(I) <= (OTHERS => '0');
504 sample_f3_data_sim(I) <= (OTHERS => '0');
589 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
505 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
590 IF sample_f0_val = '1' THEN sample_f0_data_sim(I) <= sample_f0_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
506 IF sample_f0_val = '1' THEN sample_f0_data_sim(I) <= sample_f0_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
591 IF sample_f1_val = '1' THEN sample_f1_data_sim(I) <= sample_f1_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
507 IF sample_f1_val = '1' THEN sample_f1_data_sim(I) <= sample_f1_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
592 IF sample_f2_val = '1' THEN sample_f2_data_sim(I) <= sample_f2_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
508 IF sample_f2_val = '1' THEN sample_f2_data_sim(I) <= sample_f2_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
593 IF sample_f3_val = '1' THEN sample_f3_data_sim(I) <= sample_f3_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
509 IF sample_f3_val = '1' THEN sample_f3_data_sim(I) <= sample_f3_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
594 END IF;
510 END IF;
595 END PROCESS;
511 END PROCESS;
596 END GENERATE all_channel_sim;
512 END GENERATE all_channel_sim;
597 -----------------------------------------------------------------------------
513 -----------------------------------------------------------------------------
598
514
599 END beh; No newline at end of file
515 END beh;
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