diff --git a/boards/LFR-EQM/LFR_EQM_RTAX.pdc b/boards/LFR-EQM/LFR_EQM_RTAX.pdc --- a/boards/LFR-EQM/LFR_EQM_RTAX.pdc +++ b/boards/LFR-EQM/LFR_EQM_RTAX.pdc @@ -58,7 +58,7 @@ set_io {data[31]} -pinname 214 -fixed y set_io nSRAM_MBE -pinname 9 -fixed yes -DIRECTION Inout set_io nSRAM_E1 -pinname 20 -fixed yes -DIRECTION Inout set_io nSRAM_E2 -pinname 15 -fixed yes -DIRECTION Inout -set_io nSRAM_SCRUB -pinname 14 -fixed yes -DIRECTION Inout +#set_io nSRAM_SCRUB -pinname 14 -fixed yes -DIRECTION Inout set_io nSRAM_W -pinname 8 -fixed yes -DIRECTION Inout set_io nSRAM_G -pinname 21 -fixed yes -DIRECTION Inout set_io nSRAM_BUSY -pinname 24 -fixed yes -DIRECTION Inout @@ -75,15 +75,15 @@ set_io spw2_sin -pinname 304 -fixed yes set_io spw2_dout -pinname 335 -fixed yes -DIRECTION Inout set_io spw2_sout -pinname 330 -fixed yes -DIRECTION Inout -set_io TAG1 -pinname 195 -fixed yes -DIRECTION Inout -set_io TAG2 -pinname 190 -fixed yes -DIRECTION Inout -set_io TAG3 -pinname 189 -fixed yes -DIRECTION Inout -set_io TAG4 -pinname 188 -fixed yes -DIRECTION Inout -#set_io TAG5 -pinname 187 -fixed yes -DIRECTION Inout -#set_io TAG6 -pinname 184 -fixed yes -DIRECTION Inout -#set_io TAG7 -pinname 200 -fixed yes -DIRECTION Inout -set_io TAG8 -pinname 199 -fixed yes -DIRECTION Inout -#set_io TAG9 -pinname 196 -fixed yes -DIRECTION Inout +set_io {TAG[1]} -pinname 195 -fixed yes -DIRECTION Inout +#set_io {TAG[2]} -pinname 190 -fixed yes -DIRECTION Inout +set_io {TAG[3]} -pinname 189 -fixed yes -DIRECTION Inout +#set_io {TAG[4]} -pinname 188 -fixed yes -DIRECTION Inout +#set_io {TAG[5]} -pinname 187 -fixed yes -DIRECTION Inout +#set_io {TAG[6]} -pinname 184 -fixed yes -DIRECTION Inout +#set_io {TAG[7]} -pinname 200 -fixed yes -DIRECTION Inout +#set_io {TAG[8]} -pinname 199 -fixed yes -DIRECTION Inout +#set_io {TAG[9]} -pinname 196 -fixed yes -DIRECTION Inout set_io bias_fail_sw -pinname 342 -fixed yes -DIRECTION Inout diff --git a/boards/LFR-EQM/LFR_EQM_altran_syn_fanout.sdc b/boards/LFR-EQM/LFR_EQM_altran_syn_fanout.sdc --- a/boards/LFR-EQM/LFR_EQM_altran_syn_fanout.sdc +++ b/boards/LFR-EQM/LFR_EQM_altran_syn_fanout.sdc @@ -1,6 +1,6 @@ # Synopsys, Inc. constraint file -# E:\opt\tortoiseHG_vhdlib\boards\LFR-EQM\LFR_EQM_altran_syn.sdc -# Written on Fri Jun 12 10:24:30 2015 +# E:/opt/tortoiseHG_vhdlib/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_5/../../../boards/LFR-EQM/LFR_EQM_altran_syn_fanout.sdc +# Written on Fri Jun 26 12:55:35 2015 # by Synplify Pro, E-2010.09A-1 Scope Editor # @@ -10,12 +10,12 @@ # # Clocks # -define_clock {clk50MHz} -freq 50 -clockgroup default_clkgroup_0 -define_clock {n:clk_25} -freq 25 -clockgroup default_clkgroup_1 -define_clock {n:clk_24} -freq 24.576 -clockgroup default_clkgroup_2 -define_clock {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_3 -define_clock {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_4 -define_clock {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_5 +define_clock {clk50MHz} -name {clk50MHz} -freq 50 -clockgroup default_clkgroup_0 +define_clock {n:clk_25} -name {n:clk_25} -freq 25 -clockgroup default_clkgroup_1 +define_clock {n:clk_24} -name {n:clk_24} -freq 24.576 -clockgroup default_clkgroup_2 +define_clock {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -name {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_3 +define_clock {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -name {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_4 +define_clock {clk49_152MHz} -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_5 # # Clock to Clock @@ -36,24 +36,21 @@ define_clock {clk49_152MHz} -freq 49. # # Attributes # -define_global_attribute syn_useioff {1} -define_attribute {n:leon3_soc_1\.l3\.cpu.0.leon3_radhard_i.cpu.holdn} syn_maxfan {10000} -define_attribute {n:spw_inputloop\.0\.spw_phy0.rxclki_1} syn_maxfan {10000} -define_attribute {n:spw_inputloop\.1\.spw_phy0.rxclki_1} syn_maxfan {10000} -define_attribute {n:leon3_soc_1\.l3\.cpu.0.leon3_radhard_i.cpu} syn_hier {flatten} -define_global_attribute -disable syn_netlist_hierarchy {1} - - +define_global_attribute {syn_useioff} {1} +define_attribute {n:leon3_soc_1\.l3\.cpu.0.leon3_radhard_i.cpu.holdn} {syn_maxfan} {10000} +define_attribute {n:spw_inputloop\.0\.spw_phy0.rxclki_1} {syn_maxfan} {10000} +define_attribute {n:spw_inputloop\.1\.spw_phy0.rxclki_1} {syn_maxfan} {10000} +define_attribute {n:leon3_soc_1\.l3\.cpu.0.leon3_radhard_i.cpu} {syn_hier} {flatten} +define_global_attribute -disable {syn_netlist_hierarchy} {1} # # I/O Standards # - # # Compile Points # # # Other -# \ No newline at end of file +# diff --git a/designs/LFR-EQM-WFP_MS/TB.vhd b/designs/LFR-EQM-WFP_MS/TB.vhd --- a/designs/LFR-EQM-WFP_MS/TB.vhd +++ b/designs/LFR-EQM-WFP_MS/TB.vhd @@ -124,6 +124,7 @@ ARCHITECTURE beh OF TB IS --SIGNAL TAG4 : STD_ULOGIC; SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0); SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_ram : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL nSRAM_MBE : STD_LOGIC; SIGNAL nSRAM_E1 : STD_LOGIC; SIGNAL nSRAM_E2 : STD_LOGIC; diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -316,8 +316,8 @@ BEGIN -- beh ENABLE_FPU => 1, FPU_NETLIST => 0, ENABLE_DSU => 1, - ENABLE_AHB_UART => 1, - ENABLE_APB_UART => 1, + ENABLE_AHB_UART => 0, + ENABLE_APB_UART => 0, ENABLE_IRQMP => 1, ENABLE_GPT => 1, NB_AHB_MASTER => NB_AHB_MASTER, @@ -514,7 +514,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"000146") -- aa.bb.cc version + top_lfr_version => X"000154") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => LFR_rstn, diff --git a/lib/lpp/lfr_management/lfr_time_management.vhd b/lib/lpp/lfr_management/lfr_time_management.vhd --- a/lib/lpp/lfr_management/lfr_time_management.vhd +++ b/lib/lpp/lfr_management/lfr_time_management.vhd @@ -122,38 +122,26 @@ BEGIN PROCESS (clk, rstn) BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) - state <= DESYNC; + state <= DESYNC; + set_TCU <= '0'; ELSIF clk'event AND clk = '1' THEN -- rising clock edge - --CT_add1 <= '0'; set_TCU <= '0'; CASE state IS WHEN DESYNC => IF tick = '1' THEN state <= SYNC; set_TCU <= new_coarsetime_reg; - --IF new_coarsetime = '0' AND FT_half = '1' THEN - -- CT_add1 <= '1'; - --END IF; - --ELSIF FT_max = '1' THEN - -- CT_add1 <= '1'; END IF; WHEN TRANSITION => IF tick = '1' THEN state <= SYNC; set_TCU <= new_coarsetime_reg; - --IF new_coarsetime = '0' THEN - -- CT_add1 <= '1'; - --END IF; ELSIF FT_wait = '1' THEN - --CT_add1 <= '1'; state <= DESYNC; END IF; WHEN SYNC => IF tick = '1' THEN set_TCU <= new_coarsetime_reg; - --IF new_coarsetime = '0' THEN - -- CT_add1 <= '1'; - --END IF; ELSIF FT_max = '1' THEN state <= TRANSITION; END IF; diff --git a/lib/lpp/lpp_cna/SPI_DAC_DRIVER.vhd b/lib/lpp/lpp_cna/SPI_DAC_DRIVER.vhd --- a/lib/lpp/lpp_cna/SPI_DAC_DRIVER.vhd +++ b/lib/lpp/lpp_cna/SPI_DAC_DRIVER.vhd @@ -42,11 +42,13 @@ ENTITY SPI_DAC_DRIVER IS END ENTITY SPI_DAC_DRIVER; ARCHITECTURE behav OF SPI_DAC_DRIVER IS - SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0'); - SIGNAL INPUTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0'); - SIGNAL SMP_CLK_R : STD_LOGIC := '0'; - SIGNAL shiftcnt : INTEGER := 0; - SIGNAL shifting : STD_LOGIC := '0'; + SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL INPUTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL SMP_CLK_R : STD_LOGIC := '0'; + SIGNAL shiftcnt : INTEGER := 0; + SIGNAL shifting : STD_LOGIC := '0'; + + SIGNAL SCLK_s : STD_LOGIC; BEGIN @@ -58,7 +60,16 @@ BEGIN INPUTREG(datawidth-1 DOWNTO 0) <= DATA(0 TO datawidth-1); END GENERATE; - SCLK <= clk; + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + SCLK_s <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + SCLK_s <= NOT SCLK_s; + + END IF; + END PROCESS; + SCLK <= SCLK_s; PROCESS(clk, rstn) BEGIN diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -140,21 +140,6 @@ ARCHITECTURE beh OF lpp_lfr IS ----------------------------------------------------------------------------- -- ----------------------------------------------------------------------------- --- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); --- SIGNAL data_f0_data_out_valid_s : STD_LOGIC; --- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; - --f1 --- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); --- SIGNAL data_f1_data_out_valid_s : STD_LOGIC; --- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; - --f2 --- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); --- SIGNAL data_f2_data_out_valid_s : STD_LOGIC; --- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; - --f3 --- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); --- SIGNAL data_f3_data_out_valid_s : STD_LOGIC; --- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); @@ -162,57 +147,8 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); - ----------------------------------------------------------------------------- - -- DMA RR - ----------------------------------------------------------------------------- --- SIGNAL dma_sel_valid : STD_LOGIC; --- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); --- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); --- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); --- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); - --- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); --- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); - - ----------------------------------------------------------------------------- - -- DMA_REG - ----------------------------------------------------------------------------- --- SIGNAL ongoing_reg : STD_LOGIC; --- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); --- SIGNAL dma_send_reg : STD_LOGIC; --- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) --- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); --- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - - - ----------------------------------------------------------------------------- - -- DMA - ----------------------------------------------------------------------------- --- SIGNAL dma_send : STD_LOGIC; --- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) --- SIGNAL dma_done : STD_LOGIC; --- SIGNAL dma_ren : STD_LOGIC; --- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); --- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); --- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); - - ----------------------------------------------------------------------------- - -- MS - ----------------------------------------------------------------------------- - --- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); --- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); --- SIGNAL data_ms_valid : STD_LOGIC; --- SIGNAL data_ms_valid_burst : STD_LOGIC; --- SIGNAL data_ms_ren : STD_LOGIC; --- SIGNAL data_ms_done : STD_LOGIC; --- SIGNAL dma_ms_ongoing : STD_LOGIC; - --- SIGNAL run_ms : STD_LOGIC; --- SIGNAL ms_softandhard_rstn : STD_LOGIC; SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); --- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); @@ -220,9 +156,6 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL error_buffer_full : STD_LOGIC; SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); --- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0); --- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0); - ----------------------------------------------------------------------------- SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); @@ -247,17 +180,12 @@ ARCHITECTURE beh OF lpp_lfr IS BEGIN - --apb_reg_debug_vector; ----------------------------------------------------------------------------- sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); sample_time <= coarse_time & fine_time; - --all_channel : FOR i IN 7 DOWNTO 0 GENERATE - -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); - --END GENERATE all_channel; - ----------------------------------------------------------------------------- lpp_lfr_filter_1 : lpp_lfr_filter GENERIC MAP ( @@ -291,7 +219,6 @@ BEGIN lpp_lfr_apbreg_1 : lpp_lfr_apbreg GENERIC MAP ( nb_data_by_buffer_size => nb_data_by_buffer_size, --- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO nb_snapshot_param_size => nb_snapshot_param_size, delta_vector_size => delta_vector_size, delta_vector_size_f0_2 => delta_vector_size_f0_2, @@ -312,8 +239,8 @@ BEGIN ready_matrix_f0 => ready_matrix_f0, ready_matrix_f1 => ready_matrix_f1, ready_matrix_f2 => ready_matrix_f2, - error_buffer_full => error_buffer_full, -- TODO - error_input_fifo_write => error_input_fifo_write, -- TODO + error_buffer_full => error_buffer_full, + error_input_fifo_write => error_input_fifo_write, status_ready_matrix_f0 => status_ready_matrix_f0, status_ready_matrix_f1 => status_ready_matrix_f1, status_ready_matrix_f2 => status_ready_matrix_f2, @@ -329,10 +256,6 @@ BEGIN length_matrix_f0 => length_matrix_f0, length_matrix_f1 => length_matrix_f1, length_matrix_f2 => length_matrix_f2, - ------------------------------------------------------------------------- - --status_full => status_full, -- TODo - --status_full_ack => status_full_ack, -- TODo - --status_full_err => status_full_err, -- TODo status_new_err => status_new_err, data_shaping_BW => data_shaping_BW, data_shaping_SP0 => data_shaping_SP0, @@ -346,7 +269,6 @@ BEGIN delta_f1 => delta_f1, delta_f2 => delta_f2, nb_data_by_buffer => nb_data_by_buffer, --- nb_word_by_buffer => nb_word_by_buffer, -- TODO nb_snapshot_param => nb_snapshot_param, enable_f0 => enable_f0, enable_f1 => enable_f1, @@ -355,16 +277,15 @@ BEGIN burst_f0 => burst_f0, burst_f1 => burst_f1, burst_f2 => burst_f2, - run => OPEN, --run, + run => OPEN, start_date => start_date, --- debug_signal => debug_signal, - wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO - wfp_addr_buffer => wfp_addr_buffer,-- TODO - wfp_length_buffer => wfp_length_buffer,-- TODO + wfp_status_buffer_ready => wfp_status_buffer_ready, + wfp_addr_buffer => wfp_addr_buffer, + wfp_length_buffer => wfp_length_buffer, - wfp_ready_buffer => wfp_ready_buffer,-- TODO - wfp_buffer_time => wfp_buffer_time,-- TODO - wfp_error_buffer_full => wfp_error_buffer_full, -- TODO + wfp_ready_buffer => wfp_ready_buffer, + wfp_buffer_time => wfp_buffer_time, + wfp_error_buffer_full => wfp_error_buffer_full, ------------------------------------------------------------------------- sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16), sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16), @@ -462,17 +383,12 @@ BEGIN sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16)); - ------------------------------------------------------------------------------- - - --ms_softandhard_rstn <= rstn AND run_ms AND run; - ----------------------------------------------------------------------------- lpp_lfr_ms_1 : lpp_lfr_ms GENERIC MAP ( Mem_use => Mem_use) PORT MAP ( clk => clk, - --rstn => ms_softandhard_rstn, --rstn, rstn => rstn, run => '1',--run_ms, @@ -596,4 +512,4 @@ BEGIN END GENERATE all_channel_sim; ----------------------------------------------------------------------------- -END beh; \ No newline at end of file +END beh;