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1 | ||
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2 | ------------------------------------------------------------------------------ | |
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3 | -- This file is a part of the LPP VHDL IP LIBRARY | |
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4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
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5 | -- | |
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6 | -- This program is free software; you can redistribute it and/or modify | |
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7 | -- it under the terms of the GNU General Public License as published by | |
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8 | -- the Free Software Foundation; either version 3 of the License, or | |
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9 | -- (at your option) any later version. | |
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10 | -- | |
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11 | -- This program is distributed in the hope that it will be useful, | |
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12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
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13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
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14 | -- GNU General Public License for more details. | |
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15 | -- | |
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16 | -- You should have received a copy of the GNU General Public License | |
|
17 | -- along with this program; if not, write to the Free Software | |
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18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
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19 | ------------------------------------------------------------------------------- | |
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20 | -- Author : Jean-christophe Pellion | |
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21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
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22 | -- jean-christophe.pellion@easii-ic.com | |
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23 | ------------------------------------------------------------------------------- | |
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24 | -- 1.0 - initial version | |
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25 | ------------------------------------------------------------------------------- | |
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26 | LIBRARY ieee; | |
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27 | USE ieee.std_logic_1164.ALL; | |
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28 | USE ieee.numeric_std.ALL; | |
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29 | LIBRARY grlib; | |
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30 | USE grlib.amba.ALL; | |
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31 | USE grlib.stdlib.ALL; | |
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32 | USE grlib.devices.ALL; | |
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33 | USE GRLIB.DMA2AHB_Package.ALL; | |
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34 | LIBRARY lpp; | |
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35 | USE lpp.lpp_amba.ALL; | |
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36 | USE lpp.apb_devices_list.ALL; | |
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37 | USE lpp.lpp_memory.ALL; | |
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38 | USE lpp.lpp_dma_pkg.ALL; | |
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39 | LIBRARY techmap; | |
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40 | USE techmap.gencomp.ALL; | |
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41 | ||
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42 | ||
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43 | ENTITY lpp_lfr_ms_fsmdma IS | |
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44 | PORT ( | |
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45 | -- AMBA AHB system signals | |
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46 | HCLK : IN STD_ULOGIC; | |
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47 | HRESETn : IN STD_ULOGIC; | |
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48 | ||
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49 | --TIME | |
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50 | data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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51 | ||
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52 | -- fifo interface | |
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53 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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54 | fifo_empty : IN STD_LOGIC; | |
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55 | fifo_ren : OUT STD_LOGIC; | |
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56 | ||
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57 | -- header | |
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58 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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59 | header_val : IN STD_LOGIC; | |
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60 | header_ack : OUT STD_LOGIC; | |
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61 | ||
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62 | -- DMA | |
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63 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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64 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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65 | dma_valid : OUT STD_LOGIC; | |
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66 | dma_valid_burst : OUT STD_LOGIC; | |
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67 | dma_ren : IN STD_LOGIC; | |
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68 | dma_done : IN STD_LOGIC; | |
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69 | ||
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70 | -- Reg out | |
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71 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
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72 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
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73 | ready_matrix_f1 : OUT STD_LOGIC; | |
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74 | ready_matrix_f2 : OUT STD_LOGIC; | |
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75 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
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76 | error_bad_component_error : OUT STD_LOGIC; | |
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77 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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78 | ||
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79 | -- Reg In | |
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80 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |
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81 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |
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82 | status_ready_matrix_f1 : IN STD_LOGIC; | |
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83 | status_ready_matrix_f2 : IN STD_LOGIC; | |
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84 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
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85 | status_error_bad_component_error : IN STD_LOGIC; | |
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86 | ||
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87 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
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88 | config_active_interruption_onError : IN STD_LOGIC; | |
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89 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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90 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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91 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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92 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
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93 | ||
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94 | ); | |
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95 | END; | |
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96 | ||
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97 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS | |
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98 | ----------------------------------------------------------------------------- | |
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99 | -- SIGNAL DMAIn : DMA_In_Type; | |
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100 | -- SIGNAL header_dmai : DMA_In_Type; | |
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101 | -- SIGNAL component_dmai : DMA_In_Type; | |
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102 | -- SIGNAL DMAOut : DMA_OUt_Type; | |
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103 | ----------------------------------------------------------------------------- | |
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104 | ||
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105 | ----------------------------------------------------------------------------- | |
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106 | ----------------------------------------------------------------------------- | |
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107 | TYPE state_DMAWriteBurst IS (IDLE, | |
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108 | CHECK_COMPONENT_TYPE, | |
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109 | WRITE_COARSE_TIME, | |
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110 | WRITE_FINE_TIME, | |
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111 | TRASH_FIFO, | |
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112 | SEND_DATA, | |
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113 | WAIT_DATA_ACK, | |
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114 | CHECK_LENGTH | |
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115 | ); | |
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116 | SIGNAL state : state_DMAWriteBurst; -- := IDLE; | |
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117 | ||
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118 | -- SIGNAL nbSend : INTEGER; | |
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119 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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120 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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121 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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122 | SIGNAL header_check_ok : STD_LOGIC; | |
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123 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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124 | SIGNAL send_matrix : STD_LOGIC; | |
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125 | -- SIGNAL request : STD_LOGIC; | |
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126 | -- SIGNAL remaining_data_request : INTEGER; | |
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127 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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128 | ----------------------------------------------------------------------------- | |
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129 | ----------------------------------------------------------------------------- | |
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130 | SIGNAL header_select : STD_LOGIC; | |
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131 | ||
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132 | SIGNAL header_send : STD_LOGIC; | |
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133 | SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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134 | SIGNAL header_send_ok : STD_LOGIC; | |
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135 | SIGNAL header_send_ko : STD_LOGIC; | |
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136 | ||
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137 | SIGNAL component_send : STD_LOGIC; | |
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138 | SIGNAL component_send_ok : STD_LOGIC; | |
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139 | SIGNAL component_send_ko : STD_LOGIC; | |
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140 | ----------------------------------------------------------------------------- | |
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141 | SIGNAL fifo_ren_trash : STD_LOGIC; | |
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142 | SIGNAL component_fifo_ren : STD_LOGIC; | |
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143 | ||
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144 | ----------------------------------------------------------------------------- | |
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145 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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146 | SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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147 | ||
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148 | BEGIN | |
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149 | ||
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150 | debug_reg <= debug_reg_s; | |
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151 | ||
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152 | ||
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153 | send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE | |
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154 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE | |
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155 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE | |
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156 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE | |
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157 | '0'; | |
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158 | ||
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159 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" | |
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160 | '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE | |
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161 | '1' WHEN component_type = component_type_pre + "0001" ELSE | |
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162 | '0'; | |
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163 | ||
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164 | address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE | |
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165 | addr_matrix_f0_1 WHEN matrix_type = "01" ELSE | |
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166 | addr_matrix_f1 WHEN matrix_type = "10" ELSE | |
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167 | addr_matrix_f2 WHEN matrix_type = "11" ELSE | |
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168 | (OTHERS => '0'); | |
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169 | ||
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170 | ----------------------------------------------------------------------------- | |
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171 | -- DMA control | |
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172 | ----------------------------------------------------------------------------- | |
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173 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) | |
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174 | BEGIN -- PROCESS DMAWriteBurst_p | |
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175 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
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176 | matrix_type <= (OTHERS => '0'); | |
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177 | component_type <= (OTHERS => '0'); | |
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178 | state <= IDLE; | |
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179 | header_ack <= '0'; | |
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180 | ready_matrix_f0_0 <= '0'; | |
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181 | ready_matrix_f0_1 <= '0'; | |
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182 | ready_matrix_f1 <= '0'; | |
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183 | ready_matrix_f2 <= '0'; | |
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184 | error_anticipating_empty_fifo <= '0'; | |
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185 | error_bad_component_error <= '0'; | |
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186 | component_type_pre <= "0000"; | |
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187 | fifo_ren_trash <= '1'; | |
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188 | component_send <= '0'; | |
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189 | address <= (OTHERS => '0'); | |
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190 | header_select <= '0'; | |
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191 | header_send <= '0'; | |
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192 | header_data <= (OTHERS => '0'); | |
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193 | fine_time_reg <= (OTHERS => '0'); | |
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194 | ||
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195 | debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0'); | |
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196 | ||
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197 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
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198 | ||
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199 | CASE state IS | |
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200 | WHEN IDLE => | |
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201 | debug_reg_s(2 DOWNTO 0) <= "000"; | |
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202 | ||
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203 | matrix_type <= header(1 DOWNTO 0); | |
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204 | --component_type <= header(5 DOWNTO 2); | |
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205 | ||
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206 | ready_matrix_f0_0 <= '0'; | |
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207 | ready_matrix_f0_1 <= '0'; | |
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208 | ready_matrix_f1 <= '0'; | |
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209 | ready_matrix_f2 <= '0'; | |
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210 | error_bad_component_error <= '0'; | |
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211 | header_select <= '1'; | |
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212 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN | |
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213 | debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0); | |
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214 | debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2); | |
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215 | ||
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216 | matrix_type <= header(1 DOWNTO 0); | |
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217 | component_type <= header(5 DOWNTO 2); | |
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218 | component_type_pre <= component_type; | |
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219 | state <= CHECK_COMPONENT_TYPE; | |
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220 | END IF; | |
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221 | ||
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222 | WHEN CHECK_COMPONENT_TYPE => | |
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223 | debug_reg_s(2 DOWNTO 0) <= "001"; | |
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224 | ||
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225 | IF header_check_ok = '1' THEN | |
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226 | header_ack <= '1'; | |
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227 | header_send <= '0'; | |
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228 | -- | |
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229 | IF component_type = "0000" THEN | |
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230 | address <= address_matrix; | |
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231 | state <= WRITE_COARSE_TIME; | |
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232 | header_data <= data_time(31 DOWNTO 0); | |
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233 | fine_time_reg <= data_time(47 DOWNTO 32); | |
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234 | header_send <= '1'; | |
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235 | ELSE | |
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236 | state <= SEND_DATA; | |
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237 | END IF; | |
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238 | -- | |
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239 | ELSE | |
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240 | error_bad_component_error <= '1'; | |
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241 | component_type_pre <= "0000"; | |
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242 | header_ack <= '1'; | |
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243 | state <= TRASH_FIFO; | |
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244 | END IF; | |
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245 | ||
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246 | WHEN WRITE_COARSE_TIME => | |
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247 | debug_reg_s(2 DOWNTO 0) <= "010"; | |
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248 | ||
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249 | header_ack <= '0'; | |
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250 | ||
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251 | IF dma_ren = '0' THEN | |
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252 | header_send <= '0'; | |
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253 | ELSE | |
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254 | header_send <= header_send; | |
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255 | END IF; | |
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256 | ||
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257 | ||
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258 | IF header_send_ko = '1' THEN | |
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259 | header_send <= '0'; | |
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260 | state <= TRASH_FIFO; | |
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261 | error_anticipating_empty_fifo <= '1'; | |
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262 | -- TODO : error sending header | |
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263 | ELSIF header_send_ok = '1' THEN | |
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264 | header_send <= '1'; | |
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265 | header_select <= '1'; | |
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266 | header_data(15 DOWNTO 0) <= fine_time_reg; | |
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267 | header_data(31 DOWNTO 16) <= (OTHERS => '0'); | |
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268 | state <= WRITE_FINE_TIME; | |
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269 | address <= address + 4; | |
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270 | END IF; | |
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271 | ||
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272 | ||
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273 | WHEN WRITE_FINE_TIME => | |
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274 | debug_reg_s(2 DOWNTO 0) <= "011"; | |
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275 | ||
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276 | header_ack <= '0'; | |
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277 | header_ack <= '0'; | |
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278 | ||
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279 | IF dma_ren = '0' THEN | |
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280 | header_send <= '0'; | |
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281 | ELSE | |
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282 | header_send <= header_send; | |
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283 | END IF; | |
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284 | ||
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285 | IF header_send_ko = '1' THEN | |
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286 | header_send <= '0'; | |
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287 | state <= TRASH_FIFO; | |
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288 | error_anticipating_empty_fifo <= '1'; | |
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289 | -- TODO : error sending header | |
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290 | ELSIF header_send_ok = '1' THEN | |
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291 | header_send <= '0'; | |
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292 | header_select <= '0'; | |
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293 | state <= SEND_DATA; | |
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294 | address <= address + 4; | |
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295 | END IF; | |
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296 | ||
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297 | WHEN TRASH_FIFO => | |
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298 | debug_reg_s(2 DOWNTO 0) <= "100"; | |
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299 | ||
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300 | header_ack <= '0'; | |
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301 | error_bad_component_error <= '0'; | |
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302 | error_anticipating_empty_fifo <= '0'; | |
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303 | IF fifo_empty = '1' THEN | |
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304 | state <= IDLE; | |
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305 | fifo_ren_trash <= '1'; | |
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306 | ELSE | |
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307 | fifo_ren_trash <= '0'; | |
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308 | END IF; | |
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309 | ||
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310 | WHEN SEND_DATA => | |
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311 | debug_reg_s(2 DOWNTO 0) <= "101"; | |
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312 | ||
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313 | IF fifo_empty = '1' THEN | |
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314 | state <= IDLE; | |
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315 | IF component_type = "1110" THEN --"1110" -- JC | |
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316 | CASE matrix_type IS | |
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317 | WHEN "00" => ready_matrix_f0_0 <= '1'; | |
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318 | WHEN "01" => ready_matrix_f0_1 <= '1'; | |
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319 | WHEN "10" => ready_matrix_f1 <= '1'; | |
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320 | WHEN "11" => ready_matrix_f2 <= '1'; | |
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321 | WHEN OTHERS => NULL; | |
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322 | END CASE; | |
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323 | ||
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324 | END IF; | |
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325 | ELSE | |
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326 | component_send <= '1'; | |
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327 | address <= address; | |
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328 | state <= WAIT_DATA_ACK; | |
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329 | END IF; | |
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330 | ||
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331 | WHEN WAIT_DATA_ACK => | |
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332 | debug_reg_s(2 DOWNTO 0) <= "110"; | |
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333 | ||
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334 | component_send <= '0'; | |
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335 | IF component_send_ok = '1' THEN | |
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336 | address <= address + 64; | |
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337 | state <= SEND_DATA; | |
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338 | ELSIF component_send_ko = '1' THEN | |
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339 | error_anticipating_empty_fifo <= '0'; | |
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340 | state <= TRASH_FIFO; | |
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341 | END IF; | |
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342 | ||
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343 | WHEN CHECK_LENGTH => | |
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344 | debug_reg_s(2 DOWNTO 0) <= "111"; | |
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345 | state <= IDLE; | |
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346 | ||
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347 | WHEN OTHERS => NULL; | |
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348 | END CASE; | |
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349 | ||
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350 | END IF; | |
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351 | END PROCESS DMAWriteFSM_p; | |
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352 | ||
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353 | dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send; | |
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354 | dma_valid <= header_send WHEN header_select = '1' ELSE '0'; | |
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355 | dma_data <= header_data WHEN header_select = '1' ELSE fifo_data; | |
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356 | dma_addr <= address; | |
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357 | fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren; | |
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358 | ||
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359 | component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done; | |
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360 | component_send_ko <= '0'; | |
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361 | ||
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362 | header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done; | |
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363 | header_send_ko <= '0'; | |
|
364 | ||
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365 | END Behavioral; No newline at end of file |
@@ -0,0 +1,344 | |||
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1 | LIBRARY ieee; | |
|
2 | USE ieee.std_logic_1164.ALL; | |
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3 | USE ieee.numeric_std.ALL; | |
|
4 | ||
|
5 | LIBRARY lpp; | |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
|
7 | USE lpp.iir_filter.ALL; | |
|
8 | USE lpp.FILTERcfg.ALL; | |
|
9 | USE lpp.lpp_memory.ALL; | |
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |
|
11 | USE lpp.lpp_top_lfr_pkg.ALL; | |
|
12 | USE lpp.lpp_lfr_pkg.ALL; | |
|
13 | ||
|
14 | LIBRARY techmap; | |
|
15 | USE techmap.gencomp.ALL; | |
|
16 | ||
|
17 | LIBRARY grlib; | |
|
18 | USE grlib.amba.ALL; | |
|
19 | USE grlib.stdlib.ALL; | |
|
20 | USE grlib.devices.ALL; | |
|
21 | USE GRLIB.DMA2AHB_Package.ALL; | |
|
22 | ||
|
23 | ENTITY lpp_top_ms IS | |
|
24 | GENERIC ( | |
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25 | Mem_use : INTEGER := use_RAM; | |
|
26 | nb_burst_available_size : INTEGER := 11; | |
|
27 | nb_snapshot_param_size : INTEGER := 11; | |
|
28 | delta_snapshot_size : INTEGER := 16; | |
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29 | delta_f2_f0_size : INTEGER := 10; | |
|
30 | delta_f2_f1_size : INTEGER := 10; | |
|
31 | ||
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32 | pindex : INTEGER := 4; | |
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33 | paddr : INTEGER := 4; | |
|
34 | pmask : INTEGER := 16#fff#; | |
|
35 | pirq_ms : INTEGER := 0; | |
|
36 | pirq_wfp : INTEGER := 1; | |
|
37 | ||
|
38 | hindex_wfp : INTEGER := 2; | |
|
39 | hindex_ms : INTEGER := 3 | |
|
40 | ||
|
41 | ); | |
|
42 | PORT ( | |
|
43 | clk : IN STD_LOGIC; | |
|
44 | rstn : IN STD_LOGIC; | |
|
45 | -- | |
|
46 | sample_B : IN Samples14v(2 DOWNTO 0); | |
|
47 | sample_E : IN Samples14v(4 DOWNTO 0); | |
|
48 | sample_val : IN STD_LOGIC; | |
|
49 | -- | |
|
50 | apbi : IN apb_slv_in_type; | |
|
51 | apbo : OUT apb_slv_out_type; | |
|
52 | -- | |
|
53 | -- ahbi_wfp : IN AHB_Mst_In_Type; | |
|
54 | -- ahbo_wfp : OUT AHB_Mst_Out_Type; | |
|
55 | -- | |
|
56 | ahbi_ms : IN AHB_Mst_In_Type; | |
|
57 | ahbo_ms : OUT AHB_Mst_Out_Type; | |
|
58 | -- | |
|
59 | -- coarse_time_0 : IN STD_LOGIC; | |
|
60 | -- | |
|
61 | data_shaping_BW : OUT STD_LOGIC | |
|
62 | ); | |
|
63 | END lpp_top_ms; | |
|
64 | ||
|
65 | ARCHITECTURE beh OF lpp_top_ms IS | |
|
66 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
|
67 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
|
68 | -- | |
|
69 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |
|
70 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |
|
71 | SIGNAL data_shaping_R0 : STD_LOGIC; | |
|
72 | SIGNAL data_shaping_R1 : STD_LOGIC; | |
|
73 | -- | |
|
74 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
75 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
76 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
77 | -- | |
|
78 | SIGNAL sample_f0_val : STD_LOGIC; | |
|
79 | SIGNAL sample_f1_val : STD_LOGIC; | |
|
80 | SIGNAL sample_f2_val : STD_LOGIC; | |
|
81 | SIGNAL sample_f3_val : STD_LOGIC; | |
|
82 | -- | |
|
83 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
84 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
85 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
86 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
87 | -- | |
|
88 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
89 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
90 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
91 | ||
|
92 | -- SM | |
|
93 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; | |
|
94 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
|
95 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |
|
96 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |
|
97 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
|
98 | SIGNAL error_bad_component_error : STD_LOGIC; | |
|
99 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
100 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; | |
|
101 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
|
102 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |
|
103 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |
|
104 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |
|
105 | SIGNAL status_error_bad_component_error : STD_LOGIC; | |
|
106 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |
|
107 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |
|
108 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
109 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
110 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
111 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
112 | ||
|
113 | -- WFP | |
|
114 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
115 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
116 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
117 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
118 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
|
119 | SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
|
120 | SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
|
121 | SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
|
122 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
123 | SIGNAL enable_f0 : STD_LOGIC; | |
|
124 | SIGNAL enable_f1 : STD_LOGIC; | |
|
125 | SIGNAL enable_f2 : STD_LOGIC; | |
|
126 | SIGNAL enable_f3 : STD_LOGIC; | |
|
127 | SIGNAL burst_f0 : STD_LOGIC; | |
|
128 | SIGNAL burst_f1 : STD_LOGIC; | |
|
129 | SIGNAL burst_f2 : STD_LOGIC; | |
|
130 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
131 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
132 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
133 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
134 | ||
|
135 | -- | |
|
136 | --SIGNAL time_info : STD_LOGIC_VECTOR( (4*16)-1 DOWNTO 0); | |
|
137 | --SIGNAL data_f0_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; | |
|
138 | --SIGNAL data_f1_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; | |
|
139 | --SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; | |
|
140 | --SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; | |
|
141 | ||
|
142 | -- SIGNAL val_f0_wfp : STD_LOGIC; | |
|
143 | -- SIGNAL val_f1_wfp : STD_LOGIC; | |
|
144 | -- SIGNAL val_f2_wfp : STD_LOGIC; | |
|
145 | -- SIGNAL val_f3_wfp : STD_LOGIC; | |
|
146 | BEGIN | |
|
147 | ||
|
148 | sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |
|
149 | sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); | |
|
150 | ||
|
151 | all_channel: FOR i IN 7 DOWNTO 0 GENERATE | |
|
152 | sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); | |
|
153 | END GENERATE all_channel; | |
|
154 | ||
|
155 | ----------------------------------------------------------------------------- | |
|
156 | lpp_lfr_filter_1 : lpp_lfr_filter | |
|
157 | GENERIC MAP ( | |
|
158 | Mem_use => Mem_use) | |
|
159 | PORT MAP ( | |
|
160 | sample => sample_s, | |
|
161 | sample_val => sample_val, | |
|
162 | clk => clk, | |
|
163 | rstn => rstn, | |
|
164 | data_shaping_SP0 => data_shaping_SP0, | |
|
165 | data_shaping_SP1 => data_shaping_SP1, | |
|
166 | data_shaping_R0 => data_shaping_R0, | |
|
167 | data_shaping_R1 => data_shaping_R1, | |
|
168 | sample_f0_val => sample_f0_val, | |
|
169 | sample_f1_val => sample_f1_val, | |
|
170 | sample_f2_val => sample_f2_val, | |
|
171 | sample_f3_val => sample_f3_val, | |
|
172 | sample_f0_wdata => sample_f0_data, | |
|
173 | sample_f1_wdata => sample_f1_data, | |
|
174 | sample_f2_wdata => sample_f2_data, | |
|
175 | sample_f3_wdata => sample_f3_data); | |
|
176 | ||
|
177 | ----------------------------------------------------------------------------- | |
|
178 | lpp_top_apbreg_1 : lpp_lfr_apbreg | |
|
179 | GENERIC MAP ( | |
|
180 | nb_burst_available_size => nb_burst_available_size, | |
|
181 | nb_snapshot_param_size => nb_snapshot_param_size, | |
|
182 | delta_snapshot_size => delta_snapshot_size, | |
|
183 | delta_f2_f0_size => delta_f2_f0_size, | |
|
184 | delta_f2_f1_size => delta_f2_f1_size, | |
|
185 | pindex => pindex, | |
|
186 | paddr => paddr, | |
|
187 | pmask => pmask, | |
|
188 | pirq_ms => pirq_ms, | |
|
189 | pirq_wfp => pirq_wfp) | |
|
190 | PORT MAP ( | |
|
191 | HCLK => clk, | |
|
192 | HRESETn => rstn, | |
|
193 | apbi => apbi, | |
|
194 | apbo => apbo, | |
|
195 | ||
|
196 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
|
197 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
|
198 | ready_matrix_f1 => ready_matrix_f1, | |
|
199 | ready_matrix_f2 => ready_matrix_f2, | |
|
200 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
201 | error_bad_component_error => error_bad_component_error, | |
|
202 | debug_reg => debug_reg, | |
|
203 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
|
204 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
|
205 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
|
206 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
|
207 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
208 | status_error_bad_component_error => status_error_bad_component_error, | |
|
209 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
|
210 | config_active_interruption_onError => config_active_interruption_onError, | |
|
211 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
|
212 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
|
213 | addr_matrix_f1 => addr_matrix_f1, | |
|
214 | addr_matrix_f2 => addr_matrix_f2, | |
|
215 | ||
|
216 | status_full => status_full, | |
|
217 | status_full_ack => status_full_ack, | |
|
218 | status_full_err => status_full_err, | |
|
219 | status_new_err => status_new_err, | |
|
220 | data_shaping_BW => data_shaping_BW, | |
|
221 | data_shaping_SP0 => data_shaping_SP0, | |
|
222 | data_shaping_SP1 => data_shaping_SP1, | |
|
223 | data_shaping_R0 => data_shaping_R0, | |
|
224 | data_shaping_R1 => data_shaping_R1, | |
|
225 | delta_snapshot => delta_snapshot, | |
|
226 | delta_f2_f1 => delta_f2_f1, | |
|
227 | delta_f2_f0 => delta_f2_f0, | |
|
228 | nb_burst_available => nb_burst_available, | |
|
229 | nb_snapshot_param => nb_snapshot_param, | |
|
230 | enable_f0 => enable_f0, | |
|
231 | enable_f1 => enable_f1, | |
|
232 | enable_f2 => enable_f2, | |
|
233 | enable_f3 => enable_f3, | |
|
234 | burst_f0 => burst_f0, | |
|
235 | burst_f1 => burst_f1, | |
|
236 | burst_f2 => burst_f2, | |
|
237 | addr_data_f0 => addr_data_f0, | |
|
238 | addr_data_f1 => addr_data_f1, | |
|
239 | addr_data_f2 => addr_data_f2, | |
|
240 | addr_data_f3 => addr_data_f3); | |
|
241 | ||
|
242 | ----------------------------------------------------------------------------- | |
|
243 | --lpp_waveform_1: lpp_waveform | |
|
244 | -- GENERIC MAP ( | |
|
245 | -- hindex => hindex_wfp, | |
|
246 | -- tech => inferred, | |
|
247 | -- data_size => 160, | |
|
248 | -- nb_burst_available_size => nb_burst_available_size, | |
|
249 | -- nb_snapshot_param_size => nb_snapshot_param_size, | |
|
250 | -- delta_snapshot_size => delta_snapshot_size, | |
|
251 | -- delta_f2_f0_size => delta_f2_f0_size, | |
|
252 | -- delta_f2_f1_size => delta_f2_f1_size) | |
|
253 | -- PORT MAP ( | |
|
254 | -- clk => clk, | |
|
255 | -- rstn => rstn, | |
|
256 | -- AHB_Master_In => ahbi_wfp, | |
|
257 | -- AHB_Master_Out => ahbo_wfp, | |
|
258 | -- coarse_time_0 => coarse_time_0, | |
|
259 | ||
|
260 | -- delta_snapshot => delta_snapshot, | |
|
261 | -- delta_f2_f1 => delta_f2_f1, | |
|
262 | -- delta_f2_f0 => delta_f2_f0, | |
|
263 | -- enable_f0 => enable_f0, | |
|
264 | -- enable_f1 => enable_f1, | |
|
265 | -- enable_f2 => enable_f2, | |
|
266 | -- enable_f3 => enable_f3, | |
|
267 | -- burst_f0 => burst_f0, | |
|
268 | -- burst_f1 => burst_f1, | |
|
269 | -- burst_f2 => burst_f2, | |
|
270 | -- nb_burst_available => nb_burst_available, | |
|
271 | -- nb_snapshot_param => nb_snapshot_param, | |
|
272 | -- status_full => status_full, | |
|
273 | -- status_full_ack => status_full_ack, | |
|
274 | -- status_full_err => status_full_err, | |
|
275 | -- status_new_err => status_new_err, | |
|
276 | -- addr_data_f0 => addr_data_f0, | |
|
277 | -- addr_data_f1 => addr_data_f1, | |
|
278 | -- addr_data_f2 => addr_data_f2, | |
|
279 | -- addr_data_f3 => addr_data_f3, | |
|
280 | ||
|
281 | -- data_f0_in => data_f0_wfp, | |
|
282 | -- data_f1_in => data_f1_wfp, | |
|
283 | -- data_f2_in => data_f2_wfp, | |
|
284 | -- data_f3_in => data_f3_wfp, | |
|
285 | -- data_f0_in_valid => sample_f0_val, | |
|
286 | -- data_f1_in_valid => sample_f1_val, | |
|
287 | -- data_f2_in_valid => sample_f2_val, | |
|
288 | -- data_f3_in_valid => sample_f3_val); | |
|
289 | ||
|
290 | -- time_info <= (others => '0'); | |
|
291 | ||
|
292 | -- data_f0_wfp <= sample_f0_data & time_info; | |
|
293 | -- data_f1_wfp <= sample_f1_data & time_info; | |
|
294 | -- data_f2_wfp <= sample_f2_data & time_info; | |
|
295 | -- data_f3_wfp <= sample_f3_data & time_info; | |
|
296 | ||
|
297 | ----------------------------------------------------------------------------- | |
|
298 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & | |
|
299 | NOT(sample_f0_val) & NOT(sample_f0_val) ; | |
|
300 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & | |
|
301 | NOT(sample_f1_val) & NOT(sample_f1_val) ; | |
|
302 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & | |
|
303 | NOT(sample_f3_val) & NOT(sample_f3_val) ; | |
|
304 | ||
|
305 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) | |
|
306 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); | |
|
307 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); | |
|
308 | ----------------------------------------------------------------------------- | |
|
309 | lpp_lfr_ms_1: lpp_lfr_ms | |
|
310 | GENERIC MAP ( | |
|
311 | hindex => hindex_ms) | |
|
312 | PORT MAP ( | |
|
313 | clk => clk, | |
|
314 | rstn => rstn, | |
|
315 | sample_f0_wen => sample_f0_wen, | |
|
316 | sample_f0_wdata => sample_f0_wdata, | |
|
317 | sample_f1_wen => sample_f1_wen, | |
|
318 | sample_f1_wdata => sample_f1_wdata, | |
|
319 | sample_f3_wen => sample_f3_wen, | |
|
320 | sample_f3_wdata => sample_f3_wdata, | |
|
321 | AHB_Master_In => ahbi_ms, | |
|
322 | AHB_Master_Out => ahbo_ms, | |
|
323 | ||
|
324 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
|
325 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
|
326 | ready_matrix_f1 => ready_matrix_f1, | |
|
327 | ready_matrix_f2 => ready_matrix_f2, | |
|
328 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
329 | error_bad_component_error => error_bad_component_error, | |
|
330 | debug_reg => debug_reg, | |
|
331 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
|
332 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
|
333 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
|
334 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
|
335 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
336 | status_error_bad_component_error => status_error_bad_component_error, | |
|
337 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
|
338 | config_active_interruption_onError => config_active_interruption_onError, | |
|
339 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
|
340 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
|
341 | addr_matrix_f1 => addr_matrix_f1, | |
|
342 | addr_matrix_f2 => addr_matrix_f2); | |
|
343 | ||
|
344 | END beh; |
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