diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd @@ -0,0 +1,365 @@ + +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +-- 1.0 - initial version +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_dma_pkg.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + + +ENTITY lpp_lfr_ms_fsmdma IS + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + --TIME + data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + + -- fifo interface + fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fifo_empty : IN STD_LOGIC; + fifo_ren : OUT STD_LOGIC; + + -- header + header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + header_val : IN STD_LOGIC; + header_ack : OUT STD_LOGIC; + + -- DMA + dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_valid : OUT STD_LOGIC; + dma_valid_burst : OUT STD_LOGIC; + dma_ren : IN STD_LOGIC; + dma_done : IN STD_LOGIC; + + -- Reg out + ready_matrix_f0_0 : OUT STD_LOGIC; + ready_matrix_f0_1 : OUT STD_LOGIC; + ready_matrix_f1 : OUT STD_LOGIC; + ready_matrix_f2 : OUT STD_LOGIC; + error_anticipating_empty_fifo : OUT STD_LOGIC; + error_bad_component_error : OUT STD_LOGIC; + debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- Reg In + status_ready_matrix_f0_0 : IN STD_LOGIC; + status_ready_matrix_f0_1 : IN STD_LOGIC; + status_ready_matrix_f1 : IN STD_LOGIC; + status_ready_matrix_f2 : IN STD_LOGIC; + status_error_anticipating_empty_fifo : IN STD_LOGIC; + status_error_bad_component_error : IN STD_LOGIC; + + config_active_interruption_onNewMatrix : IN STD_LOGIC; + config_active_interruption_onError : IN STD_LOGIC; + addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + + ); +END; + +ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS + ----------------------------------------------------------------------------- +-- SIGNAL DMAIn : DMA_In_Type; +-- SIGNAL header_dmai : DMA_In_Type; +-- SIGNAL component_dmai : DMA_In_Type; +-- SIGNAL DMAOut : DMA_OUt_Type; + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- + TYPE state_DMAWriteBurst IS (IDLE, + CHECK_COMPONENT_TYPE, + WRITE_COARSE_TIME, + WRITE_FINE_TIME, + TRASH_FIFO, + SEND_DATA, + WAIT_DATA_ACK, + CHECK_LENGTH + ); + SIGNAL state : state_DMAWriteBurst; -- := IDLE; + + -- SIGNAL nbSend : INTEGER; + SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL header_check_ok : STD_LOGIC; + SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL send_matrix : STD_LOGIC; + -- SIGNAL request : STD_LOGIC; +-- SIGNAL remaining_data_request : INTEGER; + SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); + ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- + SIGNAL header_select : STD_LOGIC; + + SIGNAL header_send : STD_LOGIC; + SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL header_send_ok : STD_LOGIC; + SIGNAL header_send_ko : STD_LOGIC; + + SIGNAL component_send : STD_LOGIC; + SIGNAL component_send_ok : STD_LOGIC; + SIGNAL component_send_ko : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL fifo_ren_trash : STD_LOGIC; + SIGNAL component_fifo_ren : STD_LOGIC; + + ----------------------------------------------------------------------------- + SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); + +BEGIN + + debug_reg <= debug_reg_s; + + + send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE + '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE + '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE + '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE + '0'; + + header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" + '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE + '1' WHEN component_type = component_type_pre + "0001" ELSE + '0'; + + address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE + addr_matrix_f0_1 WHEN matrix_type = "01" ELSE + addr_matrix_f1 WHEN matrix_type = "10" ELSE + addr_matrix_f2 WHEN matrix_type = "11" ELSE + (OTHERS => '0'); + + ----------------------------------------------------------------------------- + -- DMA control + ----------------------------------------------------------------------------- + DMAWriteFSM_p : PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS DMAWriteBurst_p + IF HRESETn = '0' THEN -- asynchronous reset (active low) + matrix_type <= (OTHERS => '0'); + component_type <= (OTHERS => '0'); + state <= IDLE; + header_ack <= '0'; + ready_matrix_f0_0 <= '0'; + ready_matrix_f0_1 <= '0'; + ready_matrix_f1 <= '0'; + ready_matrix_f2 <= '0'; + error_anticipating_empty_fifo <= '0'; + error_bad_component_error <= '0'; + component_type_pre <= "0000"; + fifo_ren_trash <= '1'; + component_send <= '0'; + address <= (OTHERS => '0'); + header_select <= '0'; + header_send <= '0'; + header_data <= (OTHERS => '0'); + fine_time_reg <= (OTHERS => '0'); + + debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0'); + + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + + CASE state IS + WHEN IDLE => + debug_reg_s(2 DOWNTO 0) <= "000"; + + matrix_type <= header(1 DOWNTO 0); + --component_type <= header(5 DOWNTO 2); + + ready_matrix_f0_0 <= '0'; + ready_matrix_f0_1 <= '0'; + ready_matrix_f1 <= '0'; + ready_matrix_f2 <= '0'; + error_bad_component_error <= '0'; + header_select <= '1'; + IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN + debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0); + debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2); + + matrix_type <= header(1 DOWNTO 0); + component_type <= header(5 DOWNTO 2); + component_type_pre <= component_type; + state <= CHECK_COMPONENT_TYPE; + END IF; + + WHEN CHECK_COMPONENT_TYPE => + debug_reg_s(2 DOWNTO 0) <= "001"; + + IF header_check_ok = '1' THEN + header_ack <= '1'; + header_send <= '0'; + -- + IF component_type = "0000" THEN + address <= address_matrix; + state <= WRITE_COARSE_TIME; + header_data <= data_time(31 DOWNTO 0); + fine_time_reg <= data_time(47 DOWNTO 32); + header_send <= '1'; + ELSE + state <= SEND_DATA; + END IF; + -- + ELSE + error_bad_component_error <= '1'; + component_type_pre <= "0000"; + header_ack <= '1'; + state <= TRASH_FIFO; + END IF; + + WHEN WRITE_COARSE_TIME => + debug_reg_s(2 DOWNTO 0) <= "010"; + + header_ack <= '0'; + + IF dma_ren = '0' THEN + header_send <= '0'; + ELSE + header_send <= header_send; + END IF; + + + IF header_send_ko = '1' THEN + header_send <= '0'; + state <= TRASH_FIFO; + error_anticipating_empty_fifo <= '1'; + -- TODO : error sending header + ELSIF header_send_ok = '1' THEN + header_send <= '1'; + header_select <= '1'; + header_data(15 DOWNTO 0) <= fine_time_reg; + header_data(31 DOWNTO 16) <= (OTHERS => '0'); + state <= WRITE_FINE_TIME; + address <= address + 4; + END IF; + + + WHEN WRITE_FINE_TIME => + debug_reg_s(2 DOWNTO 0) <= "011"; + + header_ack <= '0'; + header_ack <= '0'; + + IF dma_ren = '0' THEN + header_send <= '0'; + ELSE + header_send <= header_send; + END IF; + + IF header_send_ko = '1' THEN + header_send <= '0'; + state <= TRASH_FIFO; + error_anticipating_empty_fifo <= '1'; + -- TODO : error sending header + ELSIF header_send_ok = '1' THEN + header_send <= '0'; + header_select <= '0'; + state <= SEND_DATA; + address <= address + 4; + END IF; + + WHEN TRASH_FIFO => + debug_reg_s(2 DOWNTO 0) <= "100"; + + header_ack <= '0'; + error_bad_component_error <= '0'; + error_anticipating_empty_fifo <= '0'; + IF fifo_empty = '1' THEN + state <= IDLE; + fifo_ren_trash <= '1'; + ELSE + fifo_ren_trash <= '0'; + END IF; + + WHEN SEND_DATA => + debug_reg_s(2 DOWNTO 0) <= "101"; + + IF fifo_empty = '1' THEN + state <= IDLE; + IF component_type = "1110" THEN --"1110" -- JC + CASE matrix_type IS + WHEN "00" => ready_matrix_f0_0 <= '1'; + WHEN "01" => ready_matrix_f0_1 <= '1'; + WHEN "10" => ready_matrix_f1 <= '1'; + WHEN "11" => ready_matrix_f2 <= '1'; + WHEN OTHERS => NULL; + END CASE; + + END IF; + ELSE + component_send <= '1'; + address <= address; + state <= WAIT_DATA_ACK; + END IF; + + WHEN WAIT_DATA_ACK => + debug_reg_s(2 DOWNTO 0) <= "110"; + + component_send <= '0'; + IF component_send_ok = '1' THEN + address <= address + 64; + state <= SEND_DATA; + ELSIF component_send_ko = '1' THEN + error_anticipating_empty_fifo <= '0'; + state <= TRASH_FIFO; + END IF; + + WHEN CHECK_LENGTH => + debug_reg_s(2 DOWNTO 0) <= "111"; + state <= IDLE; + + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS DMAWriteFSM_p; + + dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send; + dma_valid <= header_send WHEN header_select = '1' ELSE '0'; + dma_data <= header_data WHEN header_select = '1' ELSE fifo_data; + dma_addr <= address; + fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren; + + component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done; + component_send_ko <= '0'; + + header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done; + header_send_ko <= '0'; + +END Behavioral; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_top_ms.vhd b/lib/lpp/lpp_top_lfr/lpp_top_ms.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_top_lfr/lpp_top_ms.vhd @@ -0,0 +1,344 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_waveform_pkg.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +USE lpp.lpp_lfr_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +ENTITY lpp_top_ms IS + GENERIC ( + Mem_use : INTEGER := use_RAM; + nb_burst_available_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10; + + pindex : INTEGER := 4; + paddr : INTEGER := 4; + pmask : INTEGER := 16#fff#; + pirq_ms : INTEGER := 0; + pirq_wfp : INTEGER := 1; + + hindex_wfp : INTEGER := 2; + hindex_ms : INTEGER := 3 + + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + -- + sample_B : IN Samples14v(2 DOWNTO 0); + sample_E : IN Samples14v(4 DOWNTO 0); + sample_val : IN STD_LOGIC; + -- + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + -- +-- ahbi_wfp : IN AHB_Mst_In_Type; +-- ahbo_wfp : OUT AHB_Mst_Out_Type; + -- + ahbi_ms : IN AHB_Mst_In_Type; + ahbo_ms : OUT AHB_Mst_Out_Type; + -- +-- coarse_time_0 : IN STD_LOGIC; + -- + data_shaping_BW : OUT STD_LOGIC + ); +END lpp_top_ms; + +ARCHITECTURE beh OF lpp_top_ms IS + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_s : Samples(7 DOWNTO 0); + -- + SIGNAL data_shaping_SP0 : STD_LOGIC; + SIGNAL data_shaping_SP1 : STD_LOGIC; + SIGNAL data_shaping_R0 : STD_LOGIC; + SIGNAL data_shaping_R1 : STD_LOGIC; + -- + SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + -- + SIGNAL sample_f0_val : STD_LOGIC; + SIGNAL sample_f1_val : STD_LOGIC; + SIGNAL sample_f2_val : STD_LOGIC; + SIGNAL sample_f3_val : STD_LOGIC; + -- + SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + + -- SM + SIGNAL ready_matrix_f0_0 : STD_LOGIC; + SIGNAL ready_matrix_f0_1 : STD_LOGIC; + SIGNAL ready_matrix_f1 : STD_LOGIC; + SIGNAL ready_matrix_f2 : STD_LOGIC; + SIGNAL error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL error_bad_component_error : STD_LOGIC; + SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; + SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; + SIGNAL status_ready_matrix_f1 : STD_LOGIC; + SIGNAL status_ready_matrix_f2 : STD_LOGIC; + SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL status_error_bad_component_error : STD_LOGIC; + SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; + SIGNAL config_active_interruption_onError : STD_LOGIC; + SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- WFP + SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + SIGNAL enable_f0 : STD_LOGIC; + SIGNAL enable_f1 : STD_LOGIC; + SIGNAL enable_f2 : STD_LOGIC; + SIGNAL enable_f3 : STD_LOGIC; + SIGNAL burst_f0 : STD_LOGIC; + SIGNAL burst_f1 : STD_LOGIC; + SIGNAL burst_f2 : STD_LOGIC; + SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- + --SIGNAL time_info : STD_LOGIC_VECTOR( (4*16)-1 DOWNTO 0); + --SIGNAL data_f0_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; + --SIGNAL data_f1_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; + --SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; + --SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; + + -- SIGNAL val_f0_wfp : STD_LOGIC; + -- SIGNAL val_f1_wfp : STD_LOGIC; + -- SIGNAL val_f2_wfp : STD_LOGIC; + -- SIGNAL val_f3_wfp : STD_LOGIC; +BEGIN + + sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); + sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); + + all_channel: FOR i IN 7 DOWNTO 0 GENERATE + sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); + END GENERATE all_channel; + + ----------------------------------------------------------------------------- + lpp_lfr_filter_1 : lpp_lfr_filter + GENERIC MAP ( + Mem_use => Mem_use) + PORT MAP ( + sample => sample_s, + sample_val => sample_val, + clk => clk, + rstn => rstn, + data_shaping_SP0 => data_shaping_SP0, + data_shaping_SP1 => data_shaping_SP1, + data_shaping_R0 => data_shaping_R0, + data_shaping_R1 => data_shaping_R1, + sample_f0_val => sample_f0_val, + sample_f1_val => sample_f1_val, + sample_f2_val => sample_f2_val, + sample_f3_val => sample_f3_val, + sample_f0_wdata => sample_f0_data, + sample_f1_wdata => sample_f1_data, + sample_f2_wdata => sample_f2_data, + sample_f3_wdata => sample_f3_data); + + ----------------------------------------------------------------------------- + lpp_top_apbreg_1 : lpp_lfr_apbreg + GENERIC MAP ( + nb_burst_available_size => nb_burst_available_size, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size, + pindex => pindex, + paddr => paddr, + pmask => pmask, + pirq_ms => pirq_ms, + pirq_wfp => pirq_wfp) + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + apbi => apbi, + apbo => apbo, + + ready_matrix_f0_0 => ready_matrix_f0_0, + ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_anticipating_empty_fifo => error_anticipating_empty_fifo, + error_bad_component_error => error_bad_component_error, + debug_reg => debug_reg, + status_ready_matrix_f0_0 => status_ready_matrix_f0_0, + status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, + status_error_bad_component_error => status_error_bad_component_error, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + addr_matrix_f0_0 => addr_matrix_f0_0, + addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2, + + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + status_new_err => status_new_err, + data_shaping_BW => data_shaping_BW, + data_shaping_SP0 => data_shaping_SP0, + data_shaping_SP1 => data_shaping_SP1, + data_shaping_R0 => data_shaping_R0, + data_shaping_R1 => data_shaping_R1, + delta_snapshot => delta_snapshot, + delta_f2_f1 => delta_f2_f1, + delta_f2_f0 => delta_f2_f0, + nb_burst_available => nb_burst_available, + nb_snapshot_param => nb_snapshot_param, + enable_f0 => enable_f0, + enable_f1 => enable_f1, + enable_f2 => enable_f2, + enable_f3 => enable_f3, + burst_f0 => burst_f0, + burst_f1 => burst_f1, + burst_f2 => burst_f2, + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3); + + ----------------------------------------------------------------------------- + --lpp_waveform_1: lpp_waveform + -- GENERIC MAP ( + -- hindex => hindex_wfp, + -- tech => inferred, + -- data_size => 160, + -- nb_burst_available_size => nb_burst_available_size, + -- nb_snapshot_param_size => nb_snapshot_param_size, + -- delta_snapshot_size => delta_snapshot_size, + -- delta_f2_f0_size => delta_f2_f0_size, + -- delta_f2_f1_size => delta_f2_f1_size) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- AHB_Master_In => ahbi_wfp, + -- AHB_Master_Out => ahbo_wfp, + -- coarse_time_0 => coarse_time_0, + + -- delta_snapshot => delta_snapshot, + -- delta_f2_f1 => delta_f2_f1, + -- delta_f2_f0 => delta_f2_f0, + -- enable_f0 => enable_f0, + -- enable_f1 => enable_f1, + -- enable_f2 => enable_f2, + -- enable_f3 => enable_f3, + -- burst_f0 => burst_f0, + -- burst_f1 => burst_f1, + -- burst_f2 => burst_f2, + -- nb_burst_available => nb_burst_available, + -- nb_snapshot_param => nb_snapshot_param, + -- status_full => status_full, + -- status_full_ack => status_full_ack, + -- status_full_err => status_full_err, + -- status_new_err => status_new_err, + -- addr_data_f0 => addr_data_f0, + -- addr_data_f1 => addr_data_f1, + -- addr_data_f2 => addr_data_f2, + -- addr_data_f3 => addr_data_f3, + + -- data_f0_in => data_f0_wfp, + -- data_f1_in => data_f1_wfp, + -- data_f2_in => data_f2_wfp, + -- data_f3_in => data_f3_wfp, + -- data_f0_in_valid => sample_f0_val, + -- data_f1_in_valid => sample_f1_val, + -- data_f2_in_valid => sample_f2_val, + -- data_f3_in_valid => sample_f3_val); + +-- time_info <= (others => '0'); + +-- data_f0_wfp <= sample_f0_data & time_info; +-- data_f1_wfp <= sample_f1_data & time_info; +-- data_f2_wfp <= sample_f2_data & time_info; +-- data_f3_wfp <= sample_f3_data & time_info; + + ----------------------------------------------------------------------------- + sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & + NOT(sample_f0_val) & NOT(sample_f0_val) ; + sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & + NOT(sample_f1_val) & NOT(sample_f1_val) ; + sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & + NOT(sample_f3_val) & NOT(sample_f3_val) ; + + sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) + sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); + sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); + ----------------------------------------------------------------------------- + lpp_lfr_ms_1: lpp_lfr_ms + GENERIC MAP ( + hindex => hindex_ms) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_f0_wen => sample_f0_wen, + sample_f0_wdata => sample_f0_wdata, + sample_f1_wen => sample_f1_wen, + sample_f1_wdata => sample_f1_wdata, + sample_f3_wen => sample_f3_wen, + sample_f3_wdata => sample_f3_wdata, + AHB_Master_In => ahbi_ms, + AHB_Master_Out => ahbo_ms, + + ready_matrix_f0_0 => ready_matrix_f0_0, + ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_anticipating_empty_fifo => error_anticipating_empty_fifo, + error_bad_component_error => error_bad_component_error, + debug_reg => debug_reg, + status_ready_matrix_f0_0 => status_ready_matrix_f0_0, + status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, + status_error_bad_component_error => status_error_bad_component_error, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + addr_matrix_f0_0 => addr_matrix_f0_0, + addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2); + +END beh;