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add missing files : lpp_lfr_ms
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r315:6d39d17625aa (MINI-LFR) WFP_MS-0-1-3 JC
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1
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
10 --
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
15 --
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
25 -------------------------------------------------------------------------------
26 LIBRARY ieee;
27 USE ieee.std_logic_1164.ALL;
28 USE ieee.numeric_std.ALL;
29 LIBRARY grlib;
30 USE grlib.amba.ALL;
31 USE grlib.stdlib.ALL;
32 USE grlib.devices.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
34 LIBRARY lpp;
35 USE lpp.lpp_amba.ALL;
36 USE lpp.apb_devices_list.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_dma_pkg.ALL;
39 LIBRARY techmap;
40 USE techmap.gencomp.ALL;
41
42
43 ENTITY lpp_lfr_ms_fsmdma IS
44 PORT (
45 -- AMBA AHB system signals
46 HCLK : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
48
49 --TIME
50 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
51
52 -- fifo interface
53 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 fifo_empty : IN STD_LOGIC;
55 fifo_ren : OUT STD_LOGIC;
56
57 -- header
58 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 header_val : IN STD_LOGIC;
60 header_ack : OUT STD_LOGIC;
61
62 -- DMA
63 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 dma_valid : OUT STD_LOGIC;
66 dma_valid_burst : OUT STD_LOGIC;
67 dma_ren : IN STD_LOGIC;
68 dma_done : IN STD_LOGIC;
69
70 -- Reg out
71 ready_matrix_f0_0 : OUT STD_LOGIC;
72 ready_matrix_f0_1 : OUT STD_LOGIC;
73 ready_matrix_f1 : OUT STD_LOGIC;
74 ready_matrix_f2 : OUT STD_LOGIC;
75 error_anticipating_empty_fifo : OUT STD_LOGIC;
76 error_bad_component_error : OUT STD_LOGIC;
77 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78
79 -- Reg In
80 status_ready_matrix_f0_0 : IN STD_LOGIC;
81 status_ready_matrix_f0_1 : IN STD_LOGIC;
82 status_ready_matrix_f1 : IN STD_LOGIC;
83 status_ready_matrix_f2 : IN STD_LOGIC;
84 status_error_anticipating_empty_fifo : IN STD_LOGIC;
85 status_error_bad_component_error : IN STD_LOGIC;
86
87 config_active_interruption_onNewMatrix : IN STD_LOGIC;
88 config_active_interruption_onError : IN STD_LOGIC;
89 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
93
94 );
95 END;
96
97 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
98 -----------------------------------------------------------------------------
99 -- SIGNAL DMAIn : DMA_In_Type;
100 -- SIGNAL header_dmai : DMA_In_Type;
101 -- SIGNAL component_dmai : DMA_In_Type;
102 -- SIGNAL DMAOut : DMA_OUt_Type;
103 -----------------------------------------------------------------------------
104
105 -----------------------------------------------------------------------------
106 -----------------------------------------------------------------------------
107 TYPE state_DMAWriteBurst IS (IDLE,
108 CHECK_COMPONENT_TYPE,
109 WRITE_COARSE_TIME,
110 WRITE_FINE_TIME,
111 TRASH_FIFO,
112 SEND_DATA,
113 WAIT_DATA_ACK,
114 CHECK_LENGTH
115 );
116 SIGNAL state : state_DMAWriteBurst; -- := IDLE;
117
118 -- SIGNAL nbSend : INTEGER;
119 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
121 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
122 SIGNAL header_check_ok : STD_LOGIC;
123 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
124 SIGNAL send_matrix : STD_LOGIC;
125 -- SIGNAL request : STD_LOGIC;
126 -- SIGNAL remaining_data_request : INTEGER;
127 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
128 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
130 SIGNAL header_select : STD_LOGIC;
131
132 SIGNAL header_send : STD_LOGIC;
133 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
134 SIGNAL header_send_ok : STD_LOGIC;
135 SIGNAL header_send_ko : STD_LOGIC;
136
137 SIGNAL component_send : STD_LOGIC;
138 SIGNAL component_send_ok : STD_LOGIC;
139 SIGNAL component_send_ko : STD_LOGIC;
140 -----------------------------------------------------------------------------
141 SIGNAL fifo_ren_trash : STD_LOGIC;
142 SIGNAL component_fifo_ren : STD_LOGIC;
143
144 -----------------------------------------------------------------------------
145 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
147
148 BEGIN
149
150 debug_reg <= debug_reg_s;
151
152
153 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
154 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
155 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
156 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
157 '0';
158
159 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
160 '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
161 '1' WHEN component_type = component_type_pre + "0001" ELSE
162 '0';
163
164 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
165 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
166 addr_matrix_f1 WHEN matrix_type = "10" ELSE
167 addr_matrix_f2 WHEN matrix_type = "11" ELSE
168 (OTHERS => '0');
169
170 -----------------------------------------------------------------------------
171 -- DMA control
172 -----------------------------------------------------------------------------
173 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
174 BEGIN -- PROCESS DMAWriteBurst_p
175 IF HRESETn = '0' THEN -- asynchronous reset (active low)
176 matrix_type <= (OTHERS => '0');
177 component_type <= (OTHERS => '0');
178 state <= IDLE;
179 header_ack <= '0';
180 ready_matrix_f0_0 <= '0';
181 ready_matrix_f0_1 <= '0';
182 ready_matrix_f1 <= '0';
183 ready_matrix_f2 <= '0';
184 error_anticipating_empty_fifo <= '0';
185 error_bad_component_error <= '0';
186 component_type_pre <= "0000";
187 fifo_ren_trash <= '1';
188 component_send <= '0';
189 address <= (OTHERS => '0');
190 header_select <= '0';
191 header_send <= '0';
192 header_data <= (OTHERS => '0');
193 fine_time_reg <= (OTHERS => '0');
194
195 debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0');
196
197 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
198
199 CASE state IS
200 WHEN IDLE =>
201 debug_reg_s(2 DOWNTO 0) <= "000";
202
203 matrix_type <= header(1 DOWNTO 0);
204 --component_type <= header(5 DOWNTO 2);
205
206 ready_matrix_f0_0 <= '0';
207 ready_matrix_f0_1 <= '0';
208 ready_matrix_f1 <= '0';
209 ready_matrix_f2 <= '0';
210 error_bad_component_error <= '0';
211 header_select <= '1';
212 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
213 debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0);
214 debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2);
215
216 matrix_type <= header(1 DOWNTO 0);
217 component_type <= header(5 DOWNTO 2);
218 component_type_pre <= component_type;
219 state <= CHECK_COMPONENT_TYPE;
220 END IF;
221
222 WHEN CHECK_COMPONENT_TYPE =>
223 debug_reg_s(2 DOWNTO 0) <= "001";
224
225 IF header_check_ok = '1' THEN
226 header_ack <= '1';
227 header_send <= '0';
228 --
229 IF component_type = "0000" THEN
230 address <= address_matrix;
231 state <= WRITE_COARSE_TIME;
232 header_data <= data_time(31 DOWNTO 0);
233 fine_time_reg <= data_time(47 DOWNTO 32);
234 header_send <= '1';
235 ELSE
236 state <= SEND_DATA;
237 END IF;
238 --
239 ELSE
240 error_bad_component_error <= '1';
241 component_type_pre <= "0000";
242 header_ack <= '1';
243 state <= TRASH_FIFO;
244 END IF;
245
246 WHEN WRITE_COARSE_TIME =>
247 debug_reg_s(2 DOWNTO 0) <= "010";
248
249 header_ack <= '0';
250
251 IF dma_ren = '0' THEN
252 header_send <= '0';
253 ELSE
254 header_send <= header_send;
255 END IF;
256
257
258 IF header_send_ko = '1' THEN
259 header_send <= '0';
260 state <= TRASH_FIFO;
261 error_anticipating_empty_fifo <= '1';
262 -- TODO : error sending header
263 ELSIF header_send_ok = '1' THEN
264 header_send <= '1';
265 header_select <= '1';
266 header_data(15 DOWNTO 0) <= fine_time_reg;
267 header_data(31 DOWNTO 16) <= (OTHERS => '0');
268 state <= WRITE_FINE_TIME;
269 address <= address + 4;
270 END IF;
271
272
273 WHEN WRITE_FINE_TIME =>
274 debug_reg_s(2 DOWNTO 0) <= "011";
275
276 header_ack <= '0';
277 header_ack <= '0';
278
279 IF dma_ren = '0' THEN
280 header_send <= '0';
281 ELSE
282 header_send <= header_send;
283 END IF;
284
285 IF header_send_ko = '1' THEN
286 header_send <= '0';
287 state <= TRASH_FIFO;
288 error_anticipating_empty_fifo <= '1';
289 -- TODO : error sending header
290 ELSIF header_send_ok = '1' THEN
291 header_send <= '0';
292 header_select <= '0';
293 state <= SEND_DATA;
294 address <= address + 4;
295 END IF;
296
297 WHEN TRASH_FIFO =>
298 debug_reg_s(2 DOWNTO 0) <= "100";
299
300 header_ack <= '0';
301 error_bad_component_error <= '0';
302 error_anticipating_empty_fifo <= '0';
303 IF fifo_empty = '1' THEN
304 state <= IDLE;
305 fifo_ren_trash <= '1';
306 ELSE
307 fifo_ren_trash <= '0';
308 END IF;
309
310 WHEN SEND_DATA =>
311 debug_reg_s(2 DOWNTO 0) <= "101";
312
313 IF fifo_empty = '1' THEN
314 state <= IDLE;
315 IF component_type = "1110" THEN --"1110" -- JC
316 CASE matrix_type IS
317 WHEN "00" => ready_matrix_f0_0 <= '1';
318 WHEN "01" => ready_matrix_f0_1 <= '1';
319 WHEN "10" => ready_matrix_f1 <= '1';
320 WHEN "11" => ready_matrix_f2 <= '1';
321 WHEN OTHERS => NULL;
322 END CASE;
323
324 END IF;
325 ELSE
326 component_send <= '1';
327 address <= address;
328 state <= WAIT_DATA_ACK;
329 END IF;
330
331 WHEN WAIT_DATA_ACK =>
332 debug_reg_s(2 DOWNTO 0) <= "110";
333
334 component_send <= '0';
335 IF component_send_ok = '1' THEN
336 address <= address + 64;
337 state <= SEND_DATA;
338 ELSIF component_send_ko = '1' THEN
339 error_anticipating_empty_fifo <= '0';
340 state <= TRASH_FIFO;
341 END IF;
342
343 WHEN CHECK_LENGTH =>
344 debug_reg_s(2 DOWNTO 0) <= "111";
345 state <= IDLE;
346
347 WHEN OTHERS => NULL;
348 END CASE;
349
350 END IF;
351 END PROCESS DMAWriteFSM_p;
352
353 dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send;
354 dma_valid <= header_send WHEN header_select = '1' ELSE '0';
355 dma_data <= header_data WHEN header_select = '1' ELSE fifo_data;
356 dma_addr <= address;
357 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren;
358
359 component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done;
360 component_send_ko <= '0';
361
362 header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done;
363 header_send_ko <= '0';
364
365 END Behavioral; No newline at end of file
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_lfr_pkg.ALL;
13
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
16
17 LIBRARY grlib;
18 USE grlib.amba.ALL;
19 USE grlib.stdlib.ALL;
20 USE grlib.devices.ALL;
21 USE GRLIB.DMA2AHB_Package.ALL;
22
23 ENTITY lpp_top_ms IS
24 GENERIC (
25 Mem_use : INTEGER := use_RAM;
26 nb_burst_available_size : INTEGER := 11;
27 nb_snapshot_param_size : INTEGER := 11;
28 delta_snapshot_size : INTEGER := 16;
29 delta_f2_f0_size : INTEGER := 10;
30 delta_f2_f1_size : INTEGER := 10;
31
32 pindex : INTEGER := 4;
33 paddr : INTEGER := 4;
34 pmask : INTEGER := 16#fff#;
35 pirq_ms : INTEGER := 0;
36 pirq_wfp : INTEGER := 1;
37
38 hindex_wfp : INTEGER := 2;
39 hindex_ms : INTEGER := 3
40
41 );
42 PORT (
43 clk : IN STD_LOGIC;
44 rstn : IN STD_LOGIC;
45 --
46 sample_B : IN Samples14v(2 DOWNTO 0);
47 sample_E : IN Samples14v(4 DOWNTO 0);
48 sample_val : IN STD_LOGIC;
49 --
50 apbi : IN apb_slv_in_type;
51 apbo : OUT apb_slv_out_type;
52 --
53 -- ahbi_wfp : IN AHB_Mst_In_Type;
54 -- ahbo_wfp : OUT AHB_Mst_Out_Type;
55 --
56 ahbi_ms : IN AHB_Mst_In_Type;
57 ahbo_ms : OUT AHB_Mst_Out_Type;
58 --
59 -- coarse_time_0 : IN STD_LOGIC;
60 --
61 data_shaping_BW : OUT STD_LOGIC
62 );
63 END lpp_top_ms;
64
65 ARCHITECTURE beh OF lpp_top_ms IS
66 SIGNAL sample : Samples14v(7 DOWNTO 0);
67 SIGNAL sample_s : Samples(7 DOWNTO 0);
68 --
69 SIGNAL data_shaping_SP0 : STD_LOGIC;
70 SIGNAL data_shaping_SP1 : STD_LOGIC;
71 SIGNAL data_shaping_R0 : STD_LOGIC;
72 SIGNAL data_shaping_R1 : STD_LOGIC;
73 --
74 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
76 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
77 --
78 SIGNAL sample_f0_val : STD_LOGIC;
79 SIGNAL sample_f1_val : STD_LOGIC;
80 SIGNAL sample_f2_val : STD_LOGIC;
81 SIGNAL sample_f3_val : STD_LOGIC;
82 --
83 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
84 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
85 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
86 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
87 --
88 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91
92 -- SM
93 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
94 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
95 SIGNAL ready_matrix_f1 : STD_LOGIC;
96 SIGNAL ready_matrix_f2 : STD_LOGIC;
97 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
98 SIGNAL error_bad_component_error : STD_LOGIC;
99 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
100 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
101 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
102 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
103 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
104 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
105 SIGNAL status_error_bad_component_error : STD_LOGIC;
106 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
107 SIGNAL config_active_interruption_onError : STD_LOGIC;
108 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
112
113 -- WFP
114 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
115 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
116 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
119 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
120 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
121 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
122 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
123 SIGNAL enable_f0 : STD_LOGIC;
124 SIGNAL enable_f1 : STD_LOGIC;
125 SIGNAL enable_f2 : STD_LOGIC;
126 SIGNAL enable_f3 : STD_LOGIC;
127 SIGNAL burst_f0 : STD_LOGIC;
128 SIGNAL burst_f1 : STD_LOGIC;
129 SIGNAL burst_f2 : STD_LOGIC;
130 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
134
135 --
136 --SIGNAL time_info : STD_LOGIC_VECTOR( (4*16)-1 DOWNTO 0);
137 --SIGNAL data_f0_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
138 --SIGNAL data_f1_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
139 --SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
140 --SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
141
142 -- SIGNAL val_f0_wfp : STD_LOGIC;
143 -- SIGNAL val_f1_wfp : STD_LOGIC;
144 -- SIGNAL val_f2_wfp : STD_LOGIC;
145 -- SIGNAL val_f3_wfp : STD_LOGIC;
146 BEGIN
147
148 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
149 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
150
151 all_channel: FOR i IN 7 DOWNTO 0 GENERATE
152 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
153 END GENERATE all_channel;
154
155 -----------------------------------------------------------------------------
156 lpp_lfr_filter_1 : lpp_lfr_filter
157 GENERIC MAP (
158 Mem_use => Mem_use)
159 PORT MAP (
160 sample => sample_s,
161 sample_val => sample_val,
162 clk => clk,
163 rstn => rstn,
164 data_shaping_SP0 => data_shaping_SP0,
165 data_shaping_SP1 => data_shaping_SP1,
166 data_shaping_R0 => data_shaping_R0,
167 data_shaping_R1 => data_shaping_R1,
168 sample_f0_val => sample_f0_val,
169 sample_f1_val => sample_f1_val,
170 sample_f2_val => sample_f2_val,
171 sample_f3_val => sample_f3_val,
172 sample_f0_wdata => sample_f0_data,
173 sample_f1_wdata => sample_f1_data,
174 sample_f2_wdata => sample_f2_data,
175 sample_f3_wdata => sample_f3_data);
176
177 -----------------------------------------------------------------------------
178 lpp_top_apbreg_1 : lpp_lfr_apbreg
179 GENERIC MAP (
180 nb_burst_available_size => nb_burst_available_size,
181 nb_snapshot_param_size => nb_snapshot_param_size,
182 delta_snapshot_size => delta_snapshot_size,
183 delta_f2_f0_size => delta_f2_f0_size,
184 delta_f2_f1_size => delta_f2_f1_size,
185 pindex => pindex,
186 paddr => paddr,
187 pmask => pmask,
188 pirq_ms => pirq_ms,
189 pirq_wfp => pirq_wfp)
190 PORT MAP (
191 HCLK => clk,
192 HRESETn => rstn,
193 apbi => apbi,
194 apbo => apbo,
195
196 ready_matrix_f0_0 => ready_matrix_f0_0,
197 ready_matrix_f0_1 => ready_matrix_f0_1,
198 ready_matrix_f1 => ready_matrix_f1,
199 ready_matrix_f2 => ready_matrix_f2,
200 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
201 error_bad_component_error => error_bad_component_error,
202 debug_reg => debug_reg,
203 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
204 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
205 status_ready_matrix_f1 => status_ready_matrix_f1,
206 status_ready_matrix_f2 => status_ready_matrix_f2,
207 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
208 status_error_bad_component_error => status_error_bad_component_error,
209 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
210 config_active_interruption_onError => config_active_interruption_onError,
211 addr_matrix_f0_0 => addr_matrix_f0_0,
212 addr_matrix_f0_1 => addr_matrix_f0_1,
213 addr_matrix_f1 => addr_matrix_f1,
214 addr_matrix_f2 => addr_matrix_f2,
215
216 status_full => status_full,
217 status_full_ack => status_full_ack,
218 status_full_err => status_full_err,
219 status_new_err => status_new_err,
220 data_shaping_BW => data_shaping_BW,
221 data_shaping_SP0 => data_shaping_SP0,
222 data_shaping_SP1 => data_shaping_SP1,
223 data_shaping_R0 => data_shaping_R0,
224 data_shaping_R1 => data_shaping_R1,
225 delta_snapshot => delta_snapshot,
226 delta_f2_f1 => delta_f2_f1,
227 delta_f2_f0 => delta_f2_f0,
228 nb_burst_available => nb_burst_available,
229 nb_snapshot_param => nb_snapshot_param,
230 enable_f0 => enable_f0,
231 enable_f1 => enable_f1,
232 enable_f2 => enable_f2,
233 enable_f3 => enable_f3,
234 burst_f0 => burst_f0,
235 burst_f1 => burst_f1,
236 burst_f2 => burst_f2,
237 addr_data_f0 => addr_data_f0,
238 addr_data_f1 => addr_data_f1,
239 addr_data_f2 => addr_data_f2,
240 addr_data_f3 => addr_data_f3);
241
242 -----------------------------------------------------------------------------
243 --lpp_waveform_1: lpp_waveform
244 -- GENERIC MAP (
245 -- hindex => hindex_wfp,
246 -- tech => inferred,
247 -- data_size => 160,
248 -- nb_burst_available_size => nb_burst_available_size,
249 -- nb_snapshot_param_size => nb_snapshot_param_size,
250 -- delta_snapshot_size => delta_snapshot_size,
251 -- delta_f2_f0_size => delta_f2_f0_size,
252 -- delta_f2_f1_size => delta_f2_f1_size)
253 -- PORT MAP (
254 -- clk => clk,
255 -- rstn => rstn,
256 -- AHB_Master_In => ahbi_wfp,
257 -- AHB_Master_Out => ahbo_wfp,
258 -- coarse_time_0 => coarse_time_0,
259
260 -- delta_snapshot => delta_snapshot,
261 -- delta_f2_f1 => delta_f2_f1,
262 -- delta_f2_f0 => delta_f2_f0,
263 -- enable_f0 => enable_f0,
264 -- enable_f1 => enable_f1,
265 -- enable_f2 => enable_f2,
266 -- enable_f3 => enable_f3,
267 -- burst_f0 => burst_f0,
268 -- burst_f1 => burst_f1,
269 -- burst_f2 => burst_f2,
270 -- nb_burst_available => nb_burst_available,
271 -- nb_snapshot_param => nb_snapshot_param,
272 -- status_full => status_full,
273 -- status_full_ack => status_full_ack,
274 -- status_full_err => status_full_err,
275 -- status_new_err => status_new_err,
276 -- addr_data_f0 => addr_data_f0,
277 -- addr_data_f1 => addr_data_f1,
278 -- addr_data_f2 => addr_data_f2,
279 -- addr_data_f3 => addr_data_f3,
280
281 -- data_f0_in => data_f0_wfp,
282 -- data_f1_in => data_f1_wfp,
283 -- data_f2_in => data_f2_wfp,
284 -- data_f3_in => data_f3_wfp,
285 -- data_f0_in_valid => sample_f0_val,
286 -- data_f1_in_valid => sample_f1_val,
287 -- data_f2_in_valid => sample_f2_val,
288 -- data_f3_in_valid => sample_f3_val);
289
290 -- time_info <= (others => '0');
291
292 -- data_f0_wfp <= sample_f0_data & time_info;
293 -- data_f1_wfp <= sample_f1_data & time_info;
294 -- data_f2_wfp <= sample_f2_data & time_info;
295 -- data_f3_wfp <= sample_f3_data & time_info;
296
297 -----------------------------------------------------------------------------
298 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
299 NOT(sample_f0_val) & NOT(sample_f0_val) ;
300 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
301 NOT(sample_f1_val) & NOT(sample_f1_val) ;
302 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
303 NOT(sample_f3_val) & NOT(sample_f3_val) ;
304
305 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
306 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
307 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
308 -----------------------------------------------------------------------------
309 lpp_lfr_ms_1: lpp_lfr_ms
310 GENERIC MAP (
311 hindex => hindex_ms)
312 PORT MAP (
313 clk => clk,
314 rstn => rstn,
315 sample_f0_wen => sample_f0_wen,
316 sample_f0_wdata => sample_f0_wdata,
317 sample_f1_wen => sample_f1_wen,
318 sample_f1_wdata => sample_f1_wdata,
319 sample_f3_wen => sample_f3_wen,
320 sample_f3_wdata => sample_f3_wdata,
321 AHB_Master_In => ahbi_ms,
322 AHB_Master_Out => ahbo_ms,
323
324 ready_matrix_f0_0 => ready_matrix_f0_0,
325 ready_matrix_f0_1 => ready_matrix_f0_1,
326 ready_matrix_f1 => ready_matrix_f1,
327 ready_matrix_f2 => ready_matrix_f2,
328 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
329 error_bad_component_error => error_bad_component_error,
330 debug_reg => debug_reg,
331 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
332 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
333 status_ready_matrix_f1 => status_ready_matrix_f1,
334 status_ready_matrix_f2 => status_ready_matrix_f2,
335 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
336 status_error_bad_component_error => status_error_bad_component_error,
337 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
338 config_active_interruption_onError => config_active_interruption_onError,
339 addr_matrix_f0_0 => addr_matrix_f0_0,
340 addr_matrix_f0_1 => addr_matrix_f0_1,
341 addr_matrix_f1 => addr_matrix_f1,
342 addr_matrix_f2 => addr_matrix_f2);
343
344 END beh;
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