HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r202:6582fbd4a734

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paul -

r202:6582fbd4a734 paul

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r202:6582fbd4a734

lib/lpp/lpp_memory/SSRAM_plugin.vhd +2 -5

             Type stateT is (idle,st1,st2,st3,st4);
             signal state : stateT;
-            SIGNAL nclk : STD_LOGIC;
             begin
             process(clk , mem_ctrlr_o.RAMSN(0))
                 end if;
             end process;
-            nclk <= NOT clk;
             ssram_clk_pad : outpad generic map (tech => tech)
-                port map (SSRAM_CLK,nclk);
+                port map (SSRAM_CLK,not clk);
             nBWaint  <=  mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0);
             ZZ_pad : outpad generic map (tech => tech)
                 port map (ZZ, '0');
-            end architecture;
+            end architecture;
  No newline at end of file

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