# HG changeset patch
# User paul
# Date 2013-07-11 08:07:50
# Node ID 6582fbd4a7342abc4366f3991dbc44f2c77e4a45
# Parent  f870e0078492861f467f1004ee8d148d1a48c425

commit before update

diff --git a/lib/lpp/lpp_memory/SSRAM_plugin.vhd b/lib/lpp/lpp_memory/SSRAM_plugin.vhd
--- a/lib/lpp/lpp_memory/SSRAM_plugin.vhd
+++ b/lib/lpp/lpp_memory/SSRAM_plugin.vhd
@@ -80,8 +80,6 @@ signal nCE3int   : std_logic:='1';
 Type stateT is (idle,st1,st2,st3,st4);
 signal state : stateT;
 
-SIGNAL nclk : STD_LOGIC;
-
 begin
 
 process(clk , mem_ctrlr_o.RAMSN(0))
@@ -104,9 +102,8 @@ begin
     end if;
 end process;
 
-nclk <= NOT clk;
 ssram_clk_pad : outpad generic map (tech => tech)
-    port map (SSRAM_CLK,nclk);
+    port map (SSRAM_CLK,not clk);
 
 
 nBWaint  <=  mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0);
@@ -184,4 +181,4 @@ MODE_pad : outpad generic map (tech => t
 ZZ_pad : outpad generic map (tech => tech)
     port map (ZZ, '0');
 
-end architecture;
+end architecture;
\ No newline at end of file