| @@ -80,8 +80,6 signal nCE3int : std_logic:='1'; | |||
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80 | 80 | Type stateT is (idle,st1,st2,st3,st4); |
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81 | 81 | signal state : stateT; |
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82 | 82 | |
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83 | SIGNAL nclk : STD_LOGIC; | |
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84 | ||
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85 | 83 | begin |
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86 | 84 | |
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87 | 85 | process(clk , mem_ctrlr_o.RAMSN(0)) |
| @@ -104,9 +102,8 begin | |||
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104 | 102 | end if; |
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105 | 103 | end process; |
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106 | 104 | |
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107 | nclk <= NOT clk; | |
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108 | 105 | ssram_clk_pad : outpad generic map (tech => tech) |
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109 | port map (SSRAM_CLK,nclk); | |
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106 | port map (SSRAM_CLK,not clk); | |
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110 | 107 | |
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111 | 108 | |
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112 | 109 | nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0); |
| @@ -184,4 +181,4 MODE_pad : outpad generic map (tech => t | |||
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184 | 181 | ZZ_pad : outpad generic map (tech => tech) |
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185 | 182 | port map (ZZ, '0'); |
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186 | 183 | |
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187 |
end architecture; |
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184 | end architecture; No newline at end of file | |
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