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1 | NO CONTENT: modified file, binary diff hidden |
@@ -23,10 +23,15 | |||
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23 | 23 | |
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24 | 24 | LIBRARY ieee; |
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25 | 25 | USE ieee.std_logic_1164.ALL; |
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26 | USE ieee.numeric_std.all; | |
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26 | 27 | |
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27 | 28 | LIBRARY lpp; |
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28 | 29 | USE lpp.cic_pkg.ALL; |
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29 | 30 | USE lpp.data_type_pkg.ALL; |
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31 | USE lpp.iir_filter.ALL; | |
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32 | ||
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33 | LIBRARY techmap; | |
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34 | USE techmap.gencomp.ALL; | |
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30 | 35 | |
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31 | 36 | ENTITY cic_lfr IS |
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32 | 37 | GENERIC( |
@@ -50,21 +55,225 ENTITY cic_lfr IS | |||
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50 | 55 | END cic_lfr; |
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51 | 56 | |
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52 | 57 | ARCHITECTURE beh OF cic_lfr IS |
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58 | -- | |
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59 | CONSTANT S_parameter : INTEGER := 2; | |
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60 | -- | |
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53 | 61 | SIGNAL sel_sample : STD_LOGIC_VECTOR(2 DOWNTO 0); |
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54 |
SIGNAL sample_temp : sample_vector( |
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62 | SIGNAL sample_temp : sample_vector(5 DOWNTO 0,15 DOWNTO 0); | |
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55 | 63 | SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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64 | ||
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65 | SIGNAL OPERATION : STD_LOGIC_VECTOR(14 DOWNTO 0); | |
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66 | ||
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67 | -- ALU | |
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68 | SIGNAL data_in_A : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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69 | SIGNAL data_in_B : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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70 | SIGNAL data_in_Carry : STD_LOGIC; | |
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71 | SIGNAL data_out_Carry : STD_LOGIC; | |
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72 | ||
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73 | SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter DOWNTO 0); | |
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74 | ||
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75 | ----------------------------------------------------------------------------- | |
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76 | TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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77 | SIGNAL base_addr_INT : ARRAY_OF_ADDR; | |
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78 | CONSTANT base_addr_delta : INTEGER := 40; | |
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79 | SIGNAL addr_base_sel : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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80 | SIGNAL addr_gen: STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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81 | SIGNAL addr_read: STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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82 | SIGNAL addr_write: STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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83 | SIGNAL data_we: STD_LOGIC; | |
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84 | SIGNAL data_wen : STD_LOGIC; | |
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85 | SIGNAL data_write : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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86 | SIGNAL data_read : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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87 | ----------------------------------------------------------------------------- | |
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88 | SIGNAL sample_out_reg16 : sample_vector(5 DOWNTO 0, 15 DOWNTO 0); | |
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89 | SIGNAL sample_out_reg256 : sample_vector(5 DOWNTO 0, 15 DOWNTO 0); | |
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90 | SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(6 DOWNTO 0); | |
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91 | SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6 DOWNTO 0); | |
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92 | SIGNAL data_out_16_valid_s : STD_LOGIC; | |
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93 | SIGNAL data_out_256_valid_s : STD_LOGIC; | |
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94 | ||
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56 | 95 | BEGIN |
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57 | 96 | |
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58 | 97 | ----------------------------------------------------------------------------- |
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59 | 98 | -- SEL_SAMPLE |
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60 | 99 | ----------------------------------------------------------------------------- |
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100 | sel_sample <= OPERATION(5 DOWNTO 3); | |
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61 | 101 | all_bit: FOR I IN 15 DOWNTO 0 GENERATE |
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62 | 102 | sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I); |
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63 |
sample_temp(1,I) <= data_in( |
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64 |
sample_temp(2,I) <= |
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65 |
sample_temp(3,I) <= |
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66 | sample(I) <= sample_temp(2,I) WHEN sel_sample(2) = '0' ELSE sample_temp(3,I); | |
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103 | sample_temp(1,I) <= data_in(2,I) WHEN sel_sample(0) = '0' ELSE data_in(3,I); | |
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104 | sample_temp(2,I) <= data_in(4,I) WHEN sel_sample(0) = '0' ELSE data_in(5,I); | |
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105 | sample_temp(3,I) <= data_write(I) WHEN sel_sample(0) = '0' ELSE '0'; | |
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106 | ||
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107 | sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I); | |
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108 | sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE sample_temp(3,I); | |
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109 | ||
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110 | sample(I) <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I); | |
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111 | END GENERATE all_bit; | |
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112 | ||
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113 | data_in_A <= sample; | |
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114 | ||
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115 | ----------------------------------------------------------------------------- | |
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116 | -- ALU | |
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117 | ----------------------------------------------------------------------------- | |
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118 | ALU: cic_lfr_add_sub | |
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119 | PORT MAP ( | |
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120 | clk => clk, | |
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121 | rstn => rstn, | |
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122 | run => run, | |
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123 | ||
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124 | OP => OPERATION(1 DOWNTO 0), | |
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125 | ||
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126 | data_in_A => sample, | |
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127 | data_in_B => data_read, | |
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128 | data_in_Carry => data_in_Carry, | |
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129 | ||
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130 | data_out => data_write, | |
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131 | data_out_Carry => data_out_Carry); | |
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132 | ||
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133 | PROCESS (clk, rstn) | |
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134 | BEGIN -- PROCESS | |
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135 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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136 | carry_reg <= (OTHERS => '0'); | |
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137 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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138 | carry_reg(0) <= data_out_Carry; | |
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139 | all_carry: FOR I IN S_parameter DOWNTO 1 LOOP | |
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140 | carry_reg(I) <= carry_reg(I-1); | |
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141 | END LOOP all_carry; | |
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142 | END IF; | |
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143 | END PROCESS; | |
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144 | ||
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145 | data_in_Carry <= carry_reg(S_parameter-1) WHEN OPERATION(2) = '0' ELSE carry_reg(S_parameter); | |
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146 | ||
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147 | ----------------------------------------------------------------------------- | |
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148 | -- MEMORY | |
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149 | ----------------------------------------------------------------------------- | |
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150 | all_channel: FOR I IN 5 DOWNTO 0 GENERATE | |
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151 | all_bit: FOR J IN 7 DOWNTO 0 GENERATE | |
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152 | base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0'; | |
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67 | 153 | END GENERATE all_bit; |
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154 | END GENERATE all_channel; | |
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155 | ||
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156 | addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(11 DOWNTO 9)))); | |
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157 | ||
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158 | ||
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159 | cic_lfr_address_gen_1: cic_lfr_address_gen | |
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160 | PORT MAP ( | |
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161 | clk => clk, | |
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162 | rstn => rstn, | |
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163 | run => run, | |
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164 | ||
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165 | addr_base => addr_base_sel, | |
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166 | addr_init => OPERATION(7), | |
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167 | addr_add_1 => OPERATION(8), | |
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168 | addr => addr_gen); | |
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169 | ||
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170 | ||
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171 | addr_read <= addr_gen WHEN OPERATION(14 DOWNTO 12) = "000" ELSE | |
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172 | STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+2,8)) WHEN OPERATION(14 DOWNTO 12) = "001" ELSE | |
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173 | STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+5,8)) WHEN OPERATION(14 DOWNTO 12) = "010" ELSE | |
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174 | STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+8,8)) WHEN OPERATION(14 DOWNTO 12) = "011" ELSE | |
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175 | STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+6,8)); | |
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176 | ||
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177 | PROCESS (clk, rstn) | |
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178 | BEGIN -- PROCESS | |
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179 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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180 | addr_write <= (OTHERS => '0'); | |
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181 | data_we <= '0'; | |
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182 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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183 | addr_write <= addr_read; | |
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184 | data_we <= OPERATION(6); | |
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185 | END IF; | |
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186 | END PROCESS; | |
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187 | ||
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188 | memCEL : IF use_RAM_nCEL = 0 GENERATE | |
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189 | data_wen <= NOT data_we; | |
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190 | RAMblk : RAM_CEL | |
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191 | GENERIC MAP(16, 8) | |
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192 | PORT MAP( | |
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193 | WD => data_write, | |
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194 | RD => data_read, | |
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195 | WEN => data_wen, | |
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196 | REN => '0', | |
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197 | WADDR => addr_write, | |
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198 | RADDR => addr_read, | |
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199 | RWCLK => clk, | |
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200 | RESET => rstn | |
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201 | ) ; | |
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202 | END GENERATE; | |
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203 | ||
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204 | memRAM : IF use_RAM_nCEL = 1 GENERATE | |
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205 | SRAM : syncram_2p | |
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206 | GENERIC MAP(tech, 8, 16) | |
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207 | PORT MAP(clk, '1', addr_read, data_read, | |
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208 | clk, data_we, addr_write, data_write); | |
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209 | END GENERATE; | |
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210 | ||
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211 | ----------------------------------------------------------------------------- | |
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212 | -- CONTROL | |
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213 | ----------------------------------------------------------------------------- | |
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214 | cic_lfr_control_1: cic_lfr_control | |
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215 | PORT MAP ( | |
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216 | clk => clk, | |
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217 | rstn => rstn, | |
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218 | run => run, | |
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219 | data_in_valid => data_in_valid, | |
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220 | data_out_16_valid => data_out_16_valid_s, | |
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221 | data_out_256_valid => data_out_256_valid_s, | |
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222 | OPERATION => OPERATION); | |
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223 | ||
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224 | PROCESS (clk, rstn) | |
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225 | BEGIN -- PROCESS | |
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226 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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227 | sample_valid_reg16 <= "0000001"; | |
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228 | sample_valid_reg256 <= "0000001"; | |
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229 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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230 | IF run = '0' THEN | |
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231 | sample_valid_reg16 <= "0000001"; | |
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232 | sample_valid_reg256 <= "0000001"; | |
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233 | ELSE | |
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234 | IF data_out_16_valid_s = '1' OR sample_valid_reg16(6) = '1' THEN | |
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235 | sample_valid_reg16 <= sample_valid_reg16(5 DOWNTO 0) & sample_valid_reg16(6); | |
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236 | END IF; | |
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237 | IF data_out_256_valid_s = '1' OR sample_valid_reg256(6) = '1' THEN | |
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238 | sample_valid_reg256 <= sample_valid_reg256(5 DOWNTO 0) & sample_valid_reg256(6); | |
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239 | END IF; | |
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240 | END IF; | |
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241 | END IF; | |
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242 | END PROCESS; | |
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243 | ||
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244 | data_out_16_valid <= sample_valid_reg16(6); | |
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245 | data_out_256_valid <= sample_valid_reg256(6); | |
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246 | ||
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247 | ----------------------------------------------------------------------------- | |
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248 | data_out_256 <= sample_out_reg256; | |
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249 | data_out_16 <= sample_out_reg16; | |
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250 | ||
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251 | all_channel_out: FOR I IN 5 DOWNTO 0 GENERATE | |
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252 | all_bits: FOR J IN 15 DOWNTO 0 GENERATE | |
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253 | ||
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254 | PROCESS (clk, rstn) | |
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255 | BEGIN -- PROCESS | |
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256 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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257 | sample_out_reg16(I,J) <= '0'; | |
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258 | sample_out_reg256(I,J) <= '0'; | |
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259 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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260 | IF run = '0' THEN | |
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261 | sample_out_reg16(I,J) <= '0'; | |
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262 | sample_out_reg256(I,J) <= '0'; | |
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263 | ELSE | |
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264 | IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s = '1' THEN | |
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265 | sample_out_reg16(I,J) <= data_write(J); | |
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266 | END IF; | |
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267 | IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s = '1' THEN | |
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268 | sample_out_reg256(I,J) <= data_write(J); | |
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269 | END IF; | |
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270 | END IF; | |
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271 | END IF; | |
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272 | END PROCESS; | |
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273 | ||
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274 | END GENERATE all_bits; | |
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275 | END GENERATE all_channel_out; | |
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276 | ||
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68 | 277 |
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69 | 278 | END beh; |
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70 | 279 |
@@ -39,20 +39,8 ENTITY cic_lfr_control IS | |||
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39 | 39 | data_in_valid : IN STD_LOGIC; |
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40 | 40 | data_out_16_valid : OUT STD_LOGIC; |
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41 | 41 | data_out_256_valid : OUT STD_LOGIC; |
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42 | -- dataflow | |
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43 | sel_sample : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
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44 | 42 | -- |
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45 | op_valid : OUT STD_LOGIC; | |
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46 | op_ADD_SUBn : OUT STD_LOGIC; | |
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47 | -- | |
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48 | r_addr_init : OUT STD_LOGIC; | |
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49 | r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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50 | r_addr_add1 : OUT STD_LOGIC; | |
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51 | -- | |
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52 | w_en : OUT STD_LOGIC; | |
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53 | w_addr_init : OUT STD_LOGIC; | |
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54 | w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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55 | w_addr_add1 : OUT STD_LOGIC | |
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43 | OPERATION : OUT STD_LOGIC_VECTOR(14 DOWNTO 0) | |
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56 | 44 | ); |
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57 | 45 | |
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58 | 46 | END cic_lfr_control; |
@@ -60,222 +48,163 END cic_lfr_control; | |||
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60 | 48 | ARCHITECTURE beh OF cic_lfr_control IS |
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61 | 49 | |
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62 | 50 | TYPE STATE_CIC_LFR_TYPE IS (IDLE, |
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63 | ||
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64 |
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65 |
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66 | INT_0_d2, INT_1_d2, INT_2_d2, | |
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67 | ||
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68 | WAIT_INT_to_COMB_16, | |
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69 | ||
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70 | COMB_0_16_d0, COMB_1_16_d0, COMB_2_16_d0, | |
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71 | COMB_0_16_d1, COMB_1_16_d1, COMB_2_16_d1, | |
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72 | ||
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73 | COMB_0_256_d0, COMB_1_256_d0, COMB_2_256_d0, | |
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74 | COMB_0_256_d1, COMB_1_256_d1, COMB_2_256_d1, | |
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75 | COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2, | |
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76 | ||
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77 | READ_INT_2_d0, | |
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78 | READ_INT_2_d1, | |
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79 | ||
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80 | Wait_step, | |
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81 | INT_0, INT_1, INT_2 | |
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51 | RUN_PROG_I, | |
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52 | RUN_PROG_C16, | |
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53 | RUN_PROG_C256 | |
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82 | 54 | ); |
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83 | 55 | |
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84 | 56 | SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE; |
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85 | SIGNAL STATE_CIC_LFR_pre : STATE_CIC_LFR_TYPE; | |
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86 | 57 | |
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87 | SIGNAL nb_data_receipt : INTEGER; | |
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88 |
SIGNAL current_c |
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89 | ||
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90 | TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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58 | SIGNAL nb_data_receipt : INTEGER := 0; | |
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59 | SIGNAL current_cmd : INTEGER := 0; | |
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60 | SIGNAL current_channel : INTEGER := 0; | |
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61 | SIGNAL sample_16_odd : STD_LOGIC; | |
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62 | SIGNAL sample_256_odd : STD_LOGIC; | |
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91 | 63 | |
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92 | SIGNAL base_addr_INT : ARRAY_OF_ADDR; | |
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93 | CONSTANT base_addr_delta : INTEGER := 40; | |
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64 | TYPE PROGRAM_ARRAY IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(11 DOWNTO 0); | |
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65 | --OPERATION( 8 DOWNTO 0) <= PROGRAM_ARRAY( 8 DOWNTO 0) sauf pour PROG_I(0) | |
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66 | --OPERATION(13 DOWNTO 12) <= PROGRAM_ARRAY(10 DOWNTO 9) | |
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67 | --OPERATION(11 DOWNTO 9) <= current_channel | |
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68 | --OPERATION(14) <= PROGRAM_ARRAY(11) selon sample_X_odd et l'etat | |
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69 | CONSTANT PROG : PROGRAM_ARRAY(0 TO 28) := | |
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70 | ( | |
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71 | --PROG I | |
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72 | "0001"&X"C0", --0 | |
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73 | "0001"&X"70", --1 | |
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74 | "0001"&X"70", --2 | |
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75 | "0001"&X"7A", --3 | |
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76 | "0001"&X"7A", --4 | |
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77 | "0001"&X"7A", --5 | |
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78 | "0001"&X"7A", --6 | |
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79 | "0001"&X"7A", --7 | |
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80 | "0001"&X"7A", --8 | |
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81 | --PROG_C16 | |
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82 | "0010"&X"38", --9 | |
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83 | "1001"&X"71", --10 | |
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84 | "1001"&X"71", --11 | |
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85 | "1001"&X"71", --12 | |
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86 | "0100"&X"38", --13 | |
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87 | "1001"&X"77", --14 | |
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88 | "1001"&X"77", --15 | |
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89 | "1001"&X"77", --16 | |
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90 | --PROG_C256 | |
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91 | "0010"&X"38", --17 | |
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92 | "1001"&X"71", --18 | |
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93 | "1001"&X"71", --19 | |
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94 | "1001"&X"71", --20 | |
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95 | "0100"&X"38", --21 | |
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96 | "1001"&X"77", --22 | |
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97 | "1001"&X"77", --23 | |
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98 | "1001"&X"77", --24 | |
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99 | "0110"&X"38", --25 | |
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100 | "1001"&X"77", --26 | |
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101 | "1001"&X"77", --27 | |
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102 | "1001"&X"77" --28 | |
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103 | ); | |
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94 | 104 | |
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95 | CONSTANT SEL_OUT : INTEGER := 6; | |
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96 | 105 | |
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97 | signal nb_cycle_wait : integer; | |
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106 | CONSTANT PROG_START_I : INTEGER := 0; | |
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107 | CONSTANT PROG_END_I : INTEGER := 8; | |
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108 | CONSTANT PROG_START_C16 : INTEGER := 9; | |
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109 | CONSTANT PROG_END_C16 : INTEGER := 16; | |
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110 | CONSTANT PROG_START_C256 : INTEGER := 17; | |
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111 | CONSTANT PROG_END_C256 : INTEGER := 28; | |
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112 | ||
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98 | 113 | BEGIN |
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99 | 114 | |
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100 | all_channel: FOR I IN 5 DOWNTO 0 GENERATE | |
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101 | all_bit: FOR J IN 7 DOWNTO 0 GENERATE | |
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102 | base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0'; | |
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103 | END GENERATE all_bit; | |
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104 | END GENERATE all_channel; | |
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115 | OPERATION( 1 DOWNTO 0) <= PROG(current_cmd)( 1 DOWNTO 0); | |
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116 | OPERATION( 2 ) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE | |
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117 | PROG(current_cmd)( 2 ); | |
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118 | OPERATION( 5 DOWNTO 3) <= STD_LOGIC_VECTOR(to_unsigned(current_channel,3)) WHEN STATE_CIC_LFR = RUN_PROG_I AND current_cmd = 0 ELSE | |
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119 | PROG(current_cmd)(5 DOWNTO 3); | |
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120 | OPERATION( 8 DOWNTO 6) <= "000" WHEN STATE_CIC_LFR = IDLE ELSE | |
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121 | PROG(current_cmd)( 8 DOWNTO 6); | |
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122 | OPERATION(11 DOWNTO 9) <= STD_LOGIC_VECTOR(to_unsigned(current_channel,3)); | |
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123 | OPERATION(13 DOWNTO 12) <= PROG(current_cmd)(10 DOWNTO 9); | |
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124 | OPERATION(14) <= PROG(current_cmd)(11) AND sample_16_odd WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE | |
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125 | PROG(current_cmd)(11) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0'; | |
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105 | 126 | |
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106 | 127 | PROCESS (clk, rstn) |
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107 | BEGIN -- PROCESS | |
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108 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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128 | BEGIN | |
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129 | IF rstn = '0' THEN | |
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109 | 130 |
STATE_CIC_LFR |
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110 | -- | |
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111 | data_out_16_valid <= '0'; | |
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112 | data_out_256_valid <= '0'; | |
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113 | -- | |
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114 | sel_sample <= (OTHERS => '0'); | |
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115 | -- | |
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116 | op_valid <= '0'; | |
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117 | op_ADD_SUBn <= '0'; | |
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118 | -- | |
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119 | r_addr_init <= '0'; | |
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120 | r_addr_base <= (OTHERS => '0'); | |
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121 | r_addr_add1 <= '0'; | |
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122 | -- | |
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123 | w_en <= '1'; | |
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124 | w_addr_init <= '0'; | |
|
125 | w_addr_base <= (OTHERS => '0'); | |
|
126 | w_addr_add1 <= '0'; | |
|
127 | -- | |
|
128 | 131 | nb_data_receipt <= 0; |
|
129 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
130 | data_out_16_valid <= '0'; | |
|
131 |
|
|
|
132 |
|
|
|
133 | op_ADD_SUBn <= '0'; | |
|
134 | r_addr_init <= '0'; | |
|
135 | r_addr_base <= (OTHERS => '0'); | |
|
136 | r_addr_add1 <= '0'; | |
|
137 | w_en <= '1'; | |
|
138 | w_addr_init <= '0'; | |
|
139 | w_addr_base <= (OTHERS => '0'); | |
|
140 | w_addr_add1 <= '0'; | |
|
141 | ||
|
142 | IF run = '0' THEN | |
|
143 | STATE_CIC_LFR <= IDLE; | |
|
144 | -- | |
|
132 | current_channel <= 0; | |
|
133 | current_cmd <= 0; | |
|
134 | sample_16_odd <= '0'; | |
|
135 | sample_256_odd <= '0'; | |
|
145 | 136 |
|
|
146 | 137 |
|
|
147 |
|
|
|
148 | sel_sample <= (OTHERS => '0'); | |
|
149 | -- | |
|
150 | op_valid <= '0'; | |
|
151 | op_ADD_SUBn <= '0'; | |
|
152 | -- | |
|
153 | r_addr_init <= '0'; | |
|
154 | r_addr_base <= (OTHERS => '0'); | |
|
155 | r_addr_add1 <= '0'; | |
|
156 | -- | |
|
157 | w_en <= '1'; | |
|
158 | w_addr_init <= '0'; | |
|
159 | w_addr_base <= (OTHERS => '0'); | |
|
160 | w_addr_add1 <= '0'; | |
|
161 | -- | |
|
162 | nb_data_receipt <= 0; | |
|
163 | current_channel <= 0; | |
|
164 | ELSE | |
|
165 | CASE STATE_CIC_LFR IS | |
|
166 | WHEN IDLE => | |
|
138 | ||
|
139 | ELSIF clk'event AND clk = '1' THEN | |
|
167 | 140 |
|
|
168 | 141 |
|
|
169 | -- | |
|
170 | sel_sample <= (OTHERS => '0'); | |
|
171 | -- | |
|
172 | op_valid <= '0'; | |
|
173 | op_ADD_SUBn <= '0'; | |
|
174 | -- | |
|
175 | r_addr_init <= '0'; | |
|
176 | r_addr_base <= (OTHERS => '0'); | |
|
177 | r_addr_add1 <= '0'; | |
|
178 | -- | |
|
179 | w_en <= '1'; | |
|
180 | w_addr_init <= '0'; | |
|
181 | w_addr_base <= (OTHERS => '0'); | |
|
182 | w_addr_add1 <= '0'; | |
|
183 | -- | |
|
142 | CASE STATE_CIC_LFR IS | |
|
143 | WHEN IDLE => | |
|
184 | 144 |
|
|
185 | nb_data_receipt <= nb_data_receipt+1; | |
|
145 | STATE_CIC_LFR <= RUN_PROG_I; | |
|
146 | current_cmd <= PROG_START_I; | |
|
186 | 147 |
|
|
187 | STATE_CIC_LFR <= INT_0_d0; | |
|
188 | END IF; | |
|
189 | ||
|
190 | ||
|
191 | WHEN WAIT_step => --------------------------------------------------- | |
|
192 | IF nb_cycle_wait > 0 THEN | |
|
193 | nb_cycle_wait <= nb_cycle_wait -1; | |
|
194 | ELSE | |
|
195 | STATE_CIC_LFR <= STATE_CIC_LFR_pre; | |
|
148 | nb_data_receipt <= nb_data_receipt + 1; | |
|
196 | 149 |
|
|
197 | 150 |
|
|
198 | ||
|
199 | WHEN INT_0 => ------------------------------------------------------- | |
|
200 | sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)); | |
|
201 | r_addr_init <= '1'; | |
|
202 | r_addr_base <= base_addr_INT(current_channel); | |
|
203 | nb_cycle_wait <= 1; | |
|
204 | op_ADD_SUBn <= '1'; | |
|
205 | op_valid <= '1'; | |
|
206 | STATE_CIC_LFR <= WAIT_step; | |
|
207 |
STATE_CIC_LFR |
|
|
151 | WHEN RUN_PROG_I => | |
|
152 | IF current_cmd = PROG_END_I THEN | |
|
153 | IF current_channel = 5 THEN | |
|
154 | current_channel <= 0; | |
|
155 | IF nb_data_receipt MOD 16 = 0 THEN | |
|
156 | STATE_CIC_LFR <= RUN_PROG_C16; | |
|
157 | current_cmd <= PROG_START_C16; | |
|
158 | sample_16_odd <= NOT sample_16_odd; | |
|
159 | ELSE | |
|
160 | STATE_CIC_LFR <= IDLE; | |
|
161 | END IF; | |
|
162 | ELSE | |
|
163 | current_channel <= current_channel +1; | |
|
164 | current_cmd <= PROG_START_I; | |
|
165 | END IF; | |
|
166 | ELSE | |
|
167 | current_cmd <= current_cmd +1; | |
|
168 | END IF; | |
|
208 | 169 | |
|
209 |
|
|
|
210 | sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3)); | |
|
211 |
|
|
|
212 | nb_cycle_wait <= 3; | |
|
213 | op_ADD_SUBn <= '1'; | |
|
214 | op_valid <= '1'; | |
|
215 | STATE_CIC_LFR <= INT_2; | |
|
170 | WHEN RUN_PROG_C16 => | |
|
171 | IF current_cmd = PROG_END_C16 THEN | |
|
172 | data_out_16_valid <= '1'; | |
|
173 | IF current_channel = 5 THEN | |
|
174 | current_channel <= 0; | |
|
175 | IF nb_data_receipt MOD 256 = 0 THEN | |
|
176 | sample_256_odd <= NOT sample_256_odd; | |
|
177 | STATE_CIC_LFR <= RUN_PROG_C256; | |
|
178 | current_cmd <= PROG_START_C256; | |
|
179 | ELSE | |
|
180 | STATE_CIC_LFR <= IDLE; | |
|
181 | END IF; | |
|
182 | ELSE | |
|
183 | current_channel <= current_channel +1; | |
|
184 | current_cmd <= PROG_START_C16; | |
|
185 | END IF; | |
|
186 | ELSE | |
|
187 | current_cmd <= current_cmd +1; | |
|
188 | END IF; | |
|
216 | 189 |
|
|
217 |
|
|
|
218 | sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3)); | |
|
219 |
|
|
|
220 | nb_cycle_wait <= 3; | |
|
221 | op_ADD_SUBn <= '1'; | |
|
222 | op_valid <= '1'; | |
|
223 | IF nb_data_receipt = 256 THEN | |
|
224 | STATE_CIC_LFR <= COMB_0_256_d0; | |
|
225 | ELSIF (nb_data_receipt mod 16) = 0 THEN | |
|
226 | STATE_CIC_LFR <= WAIT_INT_to_COMB_16; | |
|
227 | ELSE | |
|
190 | WHEN RUN_PROG_C256 => | |
|
191 | IF current_cmd = PROG_END_C256 THEN | |
|
192 | data_out_256_valid <= '1'; | |
|
228 | 193 |
|
|
194 | nb_data_receipt <= 0; | |
|
195 | current_channel <= 0; | |
|
229 | 196 |
|
|
230 | 197 |
|
|
231 | 198 |
|
|
232 | STATE_CIC_LFR <= INT_0; | |
|
233 | END IF; | |
|
234 | END IF; | |
|
235 | ||
|
236 | ------------------------------------------------------------------- | |
|
237 | WHEN WAIT_INT_to_COMB_16 => | |
|
238 | STATE_CIC_LFR <= COMB_0_16_d0; | |
|
239 | ||
|
240 | WHEN COMB_0_16_d0 => STATE_CIC_LFR <= COMB_0_16_d1; | |
|
241 | WHEN COMB_0_16_d1 => STATE_CIC_LFR <= COMB_1_16_d0; | |
|
242 | ||
|
243 | WHEN COMB_1_16_d0 => STATE_CIC_LFR <= COMB_1_16_d1; | |
|
244 | WHEN COMB_1_16_d1 => STATE_CIC_LFR <= COMB_2_16_d0; | |
|
245 | ||
|
246 | WHEN COMB_2_16_d0 => STATE_CIC_LFR <= COMB_2_16_d1; | |
|
247 | WHEN COMB_2_16_d1 => | |
|
248 | IF current_channel = 5 THEN | |
|
249 | STATE_CIC_LFR <= IDLE; | |
|
250 | IF nb_data_receipt = 256 THEN | |
|
251 | nb_data_receipt <= 0; | |
|
199 | current_cmd <= PROG_START_C256; | |
|
252 | 200 |
|
|
253 | 201 |
|
|
254 |
|
|
|
255 | STATE_CIC_LFR <= INT_0_d0; | |
|
202 | current_cmd <= current_cmd +1; | |
|
256 | 203 |
|
|
257 | 204 | |
|
258 | ------------------------------------------------------------------- | |
|
259 | WHEN COMB_0_256_d0 => STATE_CIC_LFR <= COMB_0_256_d1; | |
|
260 | WHEN COMB_0_256_d1 => STATE_CIC_LFR <= COMB_0_256_d2; | |
|
261 | WHEN COMB_0_256_d2 => STATE_CIC_LFR <= COMB_1_256_d0; | |
|
262 | ||
|
263 | WHEN COMB_1_256_d0 => STATE_CIC_LFR <= COMB_1_256_d1; | |
|
264 | WHEN COMB_1_256_d1 => STATE_CIC_LFR <= COMB_1_256_d2; | |
|
265 | WHEN COMB_1_256_d2 => STATE_CIC_LFR <= COMB_2_256_d0; | |
|
266 | ||
|
267 | WHEN COMB_2_256_d0 => STATE_CIC_LFR <= COMB_2_256_d1; | |
|
268 | WHEN COMB_2_256_d1 => STATE_CIC_LFR <= COMB_2_256_d2; | |
|
269 | WHEN COMB_2_256_d2 => STATE_CIC_LFR <= READ_INT_2_d0; | |
|
270 | ||
|
271 | ------------------------------------------------------------------- | |
|
272 | WHEN READ_INT_2_d0 => STATE_CIC_LFR <= READ_INT_2_d1; | |
|
273 | WHEN READ_INT_2_d1 => STATE_CIC_LFR <= COMB_0_16_d0; | |
|
274 | ||
|
275 | 205 |
|
|
276 | 206 |
|
|
277 | 207 |
|
|
278 | END IF; | |
|
279 | 208 | END PROCESS; |
|
280 | 209 | |
|
281 | 210 | END beh; |
@@ -24,6 +24,9 | |||
|
24 | 24 | LIBRARY ieee; |
|
25 | 25 | USE ieee.std_logic_1164.ALL; |
|
26 | 26 | |
|
27 | LIBRARY lpp; | |
|
28 | USE lpp.data_type_pkg.ALL; | |
|
29 | ||
|
27 | 30 | PACKAGE cic_pkg IS |
|
28 | 31 | |
|
29 | 32 | ----------------------------------------------------------------------------- |
@@ -88,6 +91,22 PACKAGE cic_pkg IS | |||
|
88 | 91 | |
|
89 | 92 | |
|
90 | 93 | ----------------------------------------------------------------------------- |
|
94 | COMPONENT cic_lfr | |
|
95 | GENERIC ( | |
|
96 | tech : INTEGER; | |
|
97 | use_RAM_nCEL : INTEGER); | |
|
98 | PORT ( | |
|
99 | clk : IN STD_LOGIC; | |
|
100 | rstn : IN STD_LOGIC; | |
|
101 | run : IN STD_LOGIC; | |
|
102 | data_in : IN sample_vector(5 DOWNTO 0, 15 DOWNTO 0); | |
|
103 | data_in_valid : IN STD_LOGIC; | |
|
104 | data_out_16 : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0); | |
|
105 | data_out_16_valid : OUT STD_LOGIC; | |
|
106 | data_out_256 : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0); | |
|
107 | data_out_256_valid : OUT STD_LOGIC); | |
|
108 | END COMPONENT; | |
|
109 | ||
|
91 | 110 | COMPONENT cic_lfr_control |
|
92 | 111 | PORT ( |
|
93 | 112 | clk : IN STD_LOGIC; |
@@ -96,16 +115,33 PACKAGE cic_pkg IS | |||
|
96 | 115 | data_in_valid : IN STD_LOGIC; |
|
97 | 116 | data_out_16_valid : OUT STD_LOGIC; |
|
98 | 117 | data_out_256_valid : OUT STD_LOGIC; |
|
99 |
|
|
|
100 | op_valid : OUT STD_LOGIC; | |
|
101 | op_ADD_SUBn : OUT STD_LOGIC; | |
|
102 | r_addr_init : OUT STD_LOGIC; | |
|
103 | r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
104 | r_addr_add1 : OUT STD_LOGIC; | |
|
105 | w_en : OUT STD_LOGIC; | |
|
106 | w_addr_init : OUT STD_LOGIC; | |
|
107 | w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
108 | w_addr_add1 : OUT STD_LOGIC); | |
|
118 | OPERATION : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)); | |
|
109 | 119 | END COMPONENT; |
|
120 | ||
|
121 | COMPONENT cic_lfr_add_sub | |
|
122 | PORT ( | |
|
123 | clk : IN STD_LOGIC; | |
|
124 | rstn : IN STD_LOGIC; | |
|
125 | run : IN STD_LOGIC; | |
|
126 | OP : IN STD_LOGIC_VECTOR( 1 DOWNTO 0); | |
|
127 | data_in_A : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
128 | data_in_B : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
129 | data_in_Carry : IN STD_LOGIC; | |
|
130 | data_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
131 | data_out_Carry : OUT STD_LOGIC); | |
|
132 | END COMPONENT; | |
|
133 | ||
|
134 | COMPONENT cic_lfr_address_gen | |
|
135 | PORT ( | |
|
136 | clk : IN STD_LOGIC; | |
|
137 | rstn : IN STD_LOGIC; | |
|
138 | run : IN STD_LOGIC; | |
|
139 | addr_base : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
140 | addr_init : IN STD_LOGIC; | |
|
141 | addr_add_1 : IN STD_LOGIC; | |
|
142 | addr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); | |
|
143 | END COMPONENT; | |
|
144 | ||
|
145 | ||
|
110 | 146 |
|
|
111 | 147 | END cic_pkg; |
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