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CIC-LFR temp
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r454:53d8882e7950 JC
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@@ -23,10 +23,15
23
23
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.all;
26
27
27 LIBRARY lpp;
28 LIBRARY lpp;
28 USE lpp.cic_pkg.ALL;
29 USE lpp.cic_pkg.ALL;
29 USE lpp.data_type_pkg.ALL;
30 USE lpp.data_type_pkg.ALL;
31 USE lpp.iir_filter.ALL;
32
33 LIBRARY techmap;
34 USE techmap.gencomp.ALL;
30
35
31 ENTITY cic_lfr IS
36 ENTITY cic_lfr IS
32 GENERIC(
37 GENERIC(
@@ -50,21 +55,225 ENTITY cic_lfr IS
50 END cic_lfr;
55 END cic_lfr;
51
56
52 ARCHITECTURE beh OF cic_lfr IS
57 ARCHITECTURE beh OF cic_lfr IS
58 --
59 CONSTANT S_parameter : INTEGER := 2;
60 --
53 SIGNAL sel_sample : STD_LOGIC_VECTOR(2 DOWNTO 0);
61 SIGNAL sel_sample : STD_LOGIC_VECTOR(2 DOWNTO 0);
54 SIGNAL sample_temp : sample_vector(3 DOWNTO 0,15 DOWNTO 0);
62 SIGNAL sample_temp : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
55 SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0);
63 SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0);
64
65 SIGNAL OPERATION : STD_LOGIC_VECTOR(14 DOWNTO 0);
66
67 -- ALU
68 SIGNAL data_in_A : STD_LOGIC_VECTOR(15 DOWNTO 0);
69 SIGNAL data_in_B : STD_LOGIC_VECTOR(15 DOWNTO 0);
70 SIGNAL data_in_Carry : STD_LOGIC;
71 SIGNAL data_out_Carry : STD_LOGIC;
72
73 SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter DOWNTO 0);
74
75 -----------------------------------------------------------------------------
76 TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
77 SIGNAL base_addr_INT : ARRAY_OF_ADDR;
78 CONSTANT base_addr_delta : INTEGER := 40;
79 SIGNAL addr_base_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
80 SIGNAL addr_gen: STD_LOGIC_VECTOR(7 DOWNTO 0);
81 SIGNAL addr_read: STD_LOGIC_VECTOR(7 DOWNTO 0);
82 SIGNAL addr_write: STD_LOGIC_VECTOR(7 DOWNTO 0);
83 SIGNAL data_we: STD_LOGIC;
84 SIGNAL data_wen : STD_LOGIC;
85 SIGNAL data_write : STD_LOGIC_VECTOR(15 DOWNTO 0);
86 SIGNAL data_read : STD_LOGIC_VECTOR(15 DOWNTO 0);
87 -----------------------------------------------------------------------------
88 SIGNAL sample_out_reg16 : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
89 SIGNAL sample_out_reg256 : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
90 SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(6 DOWNTO 0);
91 SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6 DOWNTO 0);
92 SIGNAL data_out_16_valid_s : STD_LOGIC;
93 SIGNAL data_out_256_valid_s : STD_LOGIC;
94
56 BEGIN
95 BEGIN
57
96
58 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
59 -- SEL_SAMPLE
98 -- SEL_SAMPLE
60 -----------------------------------------------------------------------------
99 -----------------------------------------------------------------------------
100 sel_sample <= OPERATION(5 DOWNTO 3);
61 all_bit: FOR I IN 15 DOWNTO 0 GENERATE
101 all_bit: FOR I IN 15 DOWNTO 0 GENERATE
62 sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I);
102 sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I);
63 sample_temp(1,I) <= data_in(3,I) WHEN sel_sample(0) = '0' ELSE data_in(4,I);
103 sample_temp(1,I) <= data_in(2,I) WHEN sel_sample(0) = '0' ELSE data_in(3,I);
64 sample_temp(2,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE data_in(2,I);
104 sample_temp(2,I) <= data_in(4,I) WHEN sel_sample(0) = '0' ELSE data_in(5,I);
65 sample_temp(3,I) <= sample_temp(1,I) WHEN sel_sample(1) = '0' ELSE data_in(5,I);
105 sample_temp(3,I) <= data_write(I) WHEN sel_sample(0) = '0' ELSE '0';
66 sample(I) <= sample_temp(2,I) WHEN sel_sample(2) = '0' ELSE sample_temp(3,I);
106
67 END GENERATE all_bit;
107 sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I);
108 sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE sample_temp(3,I);
109
110 sample(I) <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I);
111 END GENERATE all_bit;
112
113 data_in_A <= sample;
114
115 -----------------------------------------------------------------------------
116 -- ALU
117 -----------------------------------------------------------------------------
118 ALU: cic_lfr_add_sub
119 PORT MAP (
120 clk => clk,
121 rstn => rstn,
122 run => run,
123
124 OP => OPERATION(1 DOWNTO 0),
125
126 data_in_A => sample,
127 data_in_B => data_read,
128 data_in_Carry => data_in_Carry,
129
130 data_out => data_write,
131 data_out_Carry => data_out_Carry);
132
133 PROCESS (clk, rstn)
134 BEGIN -- PROCESS
135 IF rstn = '0' THEN -- asynchronous reset (active low)
136 carry_reg <= (OTHERS => '0');
137 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
138 carry_reg(0) <= data_out_Carry;
139 all_carry: FOR I IN S_parameter DOWNTO 1 LOOP
140 carry_reg(I) <= carry_reg(I-1);
141 END LOOP all_carry;
142 END IF;
143 END PROCESS;
144
145 data_in_Carry <= carry_reg(S_parameter-1) WHEN OPERATION(2) = '0' ELSE carry_reg(S_parameter);
146
147 -----------------------------------------------------------------------------
148 -- MEMORY
149 -----------------------------------------------------------------------------
150 all_channel: FOR I IN 5 DOWNTO 0 GENERATE
151 all_bit: FOR J IN 7 DOWNTO 0 GENERATE
152 base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
153 END GENERATE all_bit;
154 END GENERATE all_channel;
155
156 addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(11 DOWNTO 9))));
157
158
159 cic_lfr_address_gen_1: cic_lfr_address_gen
160 PORT MAP (
161 clk => clk,
162 rstn => rstn,
163 run => run,
164
165 addr_base => addr_base_sel,
166 addr_init => OPERATION(7),
167 addr_add_1 => OPERATION(8),
168 addr => addr_gen);
169
170
171 addr_read <= addr_gen WHEN OPERATION(14 DOWNTO 12) = "000" ELSE
172 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+2,8)) WHEN OPERATION(14 DOWNTO 12) = "001" ELSE
173 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+5,8)) WHEN OPERATION(14 DOWNTO 12) = "010" ELSE
174 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+8,8)) WHEN OPERATION(14 DOWNTO 12) = "011" ELSE
175 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+6,8));
176
177 PROCESS (clk, rstn)
178 BEGIN -- PROCESS
179 IF rstn = '0' THEN -- asynchronous reset (active low)
180 addr_write <= (OTHERS => '0');
181 data_we <= '0';
182 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
183 addr_write <= addr_read;
184 data_we <= OPERATION(6);
185 END IF;
186 END PROCESS;
187
188 memCEL : IF use_RAM_nCEL = 0 GENERATE
189 data_wen <= NOT data_we;
190 RAMblk : RAM_CEL
191 GENERIC MAP(16, 8)
192 PORT MAP(
193 WD => data_write,
194 RD => data_read,
195 WEN => data_wen,
196 REN => '0',
197 WADDR => addr_write,
198 RADDR => addr_read,
199 RWCLK => clk,
200 RESET => rstn
201 ) ;
202 END GENERATE;
203
204 memRAM : IF use_RAM_nCEL = 1 GENERATE
205 SRAM : syncram_2p
206 GENERIC MAP(tech, 8, 16)
207 PORT MAP(clk, '1', addr_read, data_read,
208 clk, data_we, addr_write, data_write);
209 END GENERATE;
210
211 -----------------------------------------------------------------------------
212 -- CONTROL
213 -----------------------------------------------------------------------------
214 cic_lfr_control_1: cic_lfr_control
215 PORT MAP (
216 clk => clk,
217 rstn => rstn,
218 run => run,
219 data_in_valid => data_in_valid,
220 data_out_16_valid => data_out_16_valid_s,
221 data_out_256_valid => data_out_256_valid_s,
222 OPERATION => OPERATION);
223
224 PROCESS (clk, rstn)
225 BEGIN -- PROCESS
226 IF rstn = '0' THEN -- asynchronous reset (active low)
227 sample_valid_reg16 <= "0000001";
228 sample_valid_reg256 <= "0000001";
229 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
230 IF run = '0' THEN
231 sample_valid_reg16 <= "0000001";
232 sample_valid_reg256 <= "0000001";
233 ELSE
234 IF data_out_16_valid_s = '1' OR sample_valid_reg16(6) = '1' THEN
235 sample_valid_reg16 <= sample_valid_reg16(5 DOWNTO 0) & sample_valid_reg16(6);
236 END IF;
237 IF data_out_256_valid_s = '1' OR sample_valid_reg256(6) = '1' THEN
238 sample_valid_reg256 <= sample_valid_reg256(5 DOWNTO 0) & sample_valid_reg256(6);
239 END IF;
240 END IF;
241 END IF;
242 END PROCESS;
243
244 data_out_16_valid <= sample_valid_reg16(6);
245 data_out_256_valid <= sample_valid_reg256(6);
246
247 -----------------------------------------------------------------------------
248 data_out_256 <= sample_out_reg256;
249 data_out_16 <= sample_out_reg16;
250
251 all_channel_out: FOR I IN 5 DOWNTO 0 GENERATE
252 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
253
254 PROCESS (clk, rstn)
255 BEGIN -- PROCESS
256 IF rstn = '0' THEN -- asynchronous reset (active low)
257 sample_out_reg16(I,J) <= '0';
258 sample_out_reg256(I,J) <= '0';
259 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
260 IF run = '0' THEN
261 sample_out_reg16(I,J) <= '0';
262 sample_out_reg256(I,J) <= '0';
263 ELSE
264 IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s = '1' THEN
265 sample_out_reg16(I,J) <= data_write(J);
266 END IF;
267 IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s = '1' THEN
268 sample_out_reg256(I,J) <= data_write(J);
269 END IF;
270 END IF;
271 END IF;
272 END PROCESS;
273
274 END GENERATE all_bits;
275 END GENERATE all_channel_out;
276
68
277
69 END beh;
278 END beh;
70
279
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@@ -39,20 +39,8 ENTITY cic_lfr_control IS
39 data_in_valid : IN STD_LOGIC;
39 data_in_valid : IN STD_LOGIC;
40 data_out_16_valid : OUT STD_LOGIC;
40 data_out_16_valid : OUT STD_LOGIC;
41 data_out_256_valid : OUT STD_LOGIC;
41 data_out_256_valid : OUT STD_LOGIC;
42 -- dataflow
43 sel_sample : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
44 --
42 --
45 op_valid : OUT STD_LOGIC;
43 OPERATION : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
46 op_ADD_SUBn : OUT STD_LOGIC;
47 --
48 r_addr_init : OUT STD_LOGIC;
49 r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
50 r_addr_add1 : OUT STD_LOGIC;
51 --
52 w_en : OUT STD_LOGIC;
53 w_addr_init : OUT STD_LOGIC;
54 w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
55 w_addr_add1 : OUT STD_LOGIC
56 );
44 );
57
45
58 END cic_lfr_control;
46 END cic_lfr_control;
@@ -60,222 +48,163 END cic_lfr_control;
60 ARCHITECTURE beh OF cic_lfr_control IS
48 ARCHITECTURE beh OF cic_lfr_control IS
61
49
62 TYPE STATE_CIC_LFR_TYPE IS (IDLE,
50 TYPE STATE_CIC_LFR_TYPE IS (IDLE,
63
51 RUN_PROG_I,
64 INT_0_d0, INT_1_d0, INT_2_d0,
52 RUN_PROG_C16,
65 INT_0_d1, INT_1_d1, INT_2_d1,
53 RUN_PROG_C256
66 INT_0_d2, INT_1_d2, INT_2_d2,
67
68 WAIT_INT_to_COMB_16,
69
70 COMB_0_16_d0, COMB_1_16_d0, COMB_2_16_d0,
71 COMB_0_16_d1, COMB_1_16_d1, COMB_2_16_d1,
72
73 COMB_0_256_d0, COMB_1_256_d0, COMB_2_256_d0,
74 COMB_0_256_d1, COMB_1_256_d1, COMB_2_256_d1,
75 COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2,
76
77 READ_INT_2_d0,
78 READ_INT_2_d1,
79
80 Wait_step,
81 INT_0, INT_1, INT_2
82 );
54 );
83
55
84 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
56 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
85 SIGNAL STATE_CIC_LFR_pre : STATE_CIC_LFR_TYPE;
57
58 SIGNAL nb_data_receipt : INTEGER := 0;
59 SIGNAL current_cmd : INTEGER := 0;
60 SIGNAL current_channel : INTEGER := 0;
61 SIGNAL sample_16_odd : STD_LOGIC;
62 SIGNAL sample_256_odd : STD_LOGIC;
86
63
87 SIGNAL nb_data_receipt : INTEGER;
64 TYPE PROGRAM_ARRAY IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(11 DOWNTO 0);
88 SIGNAL current_channel : INTEGER;
65 --OPERATION( 8 DOWNTO 0) <= PROGRAM_ARRAY( 8 DOWNTO 0) sauf pour PROG_I(0)
66 --OPERATION(13 DOWNTO 12) <= PROGRAM_ARRAY(10 DOWNTO 9)
67 --OPERATION(11 DOWNTO 9) <= current_channel
68 --OPERATION(14) <= PROGRAM_ARRAY(11) selon sample_X_odd et l'etat
69 CONSTANT PROG : PROGRAM_ARRAY(0 TO 28) :=
70 (
71 --PROG I
72 "0001"&X"C0", --0
73 "0001"&X"70", --1
74 "0001"&X"70", --2
75 "0001"&X"7A", --3
76 "0001"&X"7A", --4
77 "0001"&X"7A", --5
78 "0001"&X"7A", --6
79 "0001"&X"7A", --7
80 "0001"&X"7A", --8
81 --PROG_C16
82 "0010"&X"38", --9
83 "1001"&X"71", --10
84 "1001"&X"71", --11
85 "1001"&X"71", --12
86 "0100"&X"38", --13
87 "1001"&X"77", --14
88 "1001"&X"77", --15
89 "1001"&X"77", --16
90 --PROG_C256
91 "0010"&X"38", --17
92 "1001"&X"71", --18
93 "1001"&X"71", --19
94 "1001"&X"71", --20
95 "0100"&X"38", --21
96 "1001"&X"77", --22
97 "1001"&X"77", --23
98 "1001"&X"77", --24
99 "0110"&X"38", --25
100 "1001"&X"77", --26
101 "1001"&X"77", --27
102 "1001"&X"77" --28
103 );
89
104
90 TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
91
105
92 SIGNAL base_addr_INT : ARRAY_OF_ADDR;
106 CONSTANT PROG_START_I : INTEGER := 0;
93 CONSTANT base_addr_delta : INTEGER := 40;
107 CONSTANT PROG_END_I : INTEGER := 8;
94
108 CONSTANT PROG_START_C16 : INTEGER := 9;
95 CONSTANT SEL_OUT : INTEGER := 6;
109 CONSTANT PROG_END_C16 : INTEGER := 16;
110 CONSTANT PROG_START_C256 : INTEGER := 17;
111 CONSTANT PROG_END_C256 : INTEGER := 28;
96
112
97 signal nb_cycle_wait : integer;
98 BEGIN
113 BEGIN
99
114
100 all_channel: FOR I IN 5 DOWNTO 0 GENERATE
115 OPERATION( 1 DOWNTO 0) <= PROG(current_cmd)( 1 DOWNTO 0);
101 all_bit: FOR J IN 7 DOWNTO 0 GENERATE
116 OPERATION( 2 ) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE
102 base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
117 PROG(current_cmd)( 2 );
103 END GENERATE all_bit;
118 OPERATION( 5 DOWNTO 3) <= STD_LOGIC_VECTOR(to_unsigned(current_channel,3)) WHEN STATE_CIC_LFR = RUN_PROG_I AND current_cmd = 0 ELSE
104 END GENERATE all_channel;
119 PROG(current_cmd)(5 DOWNTO 3);
120 OPERATION( 8 DOWNTO 6) <= "000" WHEN STATE_CIC_LFR = IDLE ELSE
121 PROG(current_cmd)( 8 DOWNTO 6);
122 OPERATION(11 DOWNTO 9) <= STD_LOGIC_VECTOR(to_unsigned(current_channel,3));
123 OPERATION(13 DOWNTO 12) <= PROG(current_cmd)(10 DOWNTO 9);
124 OPERATION(14) <= PROG(current_cmd)(11) AND sample_16_odd WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE
125 PROG(current_cmd)(11) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
105
126
106 PROCESS (clk, rstn)
127 PROCESS (clk, rstn)
107 BEGIN -- PROCESS
128 BEGIN
108 IF rstn = '0' THEN -- asynchronous reset (active low)
129 IF rstn = '0' THEN
109 STATE_CIC_LFR <= IDLE;
130 STATE_CIC_LFR <= IDLE;
110 --
131 nb_data_receipt <= 0;
132 current_channel <= 0;
133 current_cmd <= 0;
134 sample_16_odd <= '0';
135 sample_256_odd <= '0';
111 data_out_16_valid <= '0';
136 data_out_16_valid <= '0';
112 data_out_256_valid <= '0';
137 data_out_256_valid <= '0';
113 --
138
114 sel_sample <= (OTHERS => '0');
139 ELSIF clk'event AND clk = '1' THEN
115 --
116 op_valid <= '0';
117 op_ADD_SUBn <= '0';
118 --
119 r_addr_init <= '0';
120 r_addr_base <= (OTHERS => '0');
121 r_addr_add1 <= '0';
122 --
123 w_en <= '1';
124 w_addr_init <= '0';
125 w_addr_base <= (OTHERS => '0');
126 w_addr_add1 <= '0';
127 --
128 nb_data_receipt <= 0;
129 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
130 data_out_16_valid <= '0';
140 data_out_16_valid <= '0';
131 data_out_256_valid <= '0';
141 data_out_256_valid <= '0';
132 op_valid <= '0';
142 CASE STATE_CIC_LFR IS
133 op_ADD_SUBn <= '0';
143 WHEN IDLE =>
134 r_addr_init <= '0';
144 IF data_in_valid = '1' THEN
135 r_addr_base <= (OTHERS => '0');
145 STATE_CIC_LFR <= RUN_PROG_I;
136 r_addr_add1 <= '0';
146 current_cmd <= PROG_START_I;
137 w_en <= '1';
147 current_channel <= 0;
138 w_addr_init <= '0';
148 nb_data_receipt <= nb_data_receipt + 1;
139 w_addr_base <= (OTHERS => '0');
149 END IF;
140 w_addr_add1 <= '0';
141
142 IF run = '0' THEN
143 STATE_CIC_LFR <= IDLE;
144 --
145 data_out_16_valid <= '0';
146 data_out_256_valid <= '0';
147 --
148 sel_sample <= (OTHERS => '0');
149 --
150 op_valid <= '0';
151 op_ADD_SUBn <= '0';
152 --
153 r_addr_init <= '0';
154 r_addr_base <= (OTHERS => '0');
155 r_addr_add1 <= '0';
156 --
157 w_en <= '1';
158 w_addr_init <= '0';
159 w_addr_base <= (OTHERS => '0');
160 w_addr_add1 <= '0';
161 --
162 nb_data_receipt <= 0;
163 current_channel <= 0;
164 ELSE
165 CASE STATE_CIC_LFR IS
166 WHEN IDLE =>
167 data_out_16_valid <= '0';
168 data_out_256_valid <= '0';
169 --
170 sel_sample <= (OTHERS => '0');
171 --
172 op_valid <= '0';
173 op_ADD_SUBn <= '0';
174 --
175 r_addr_init <= '0';
176 r_addr_base <= (OTHERS => '0');
177 r_addr_add1 <= '0';
178 --
179 w_en <= '1';
180 w_addr_init <= '0';
181 w_addr_base <= (OTHERS => '0');
182 w_addr_add1 <= '0';
183 --
184 IF data_in_valid = '1' THEN
185 nb_data_receipt <= nb_data_receipt+1;
186 current_channel <= 0;
187 STATE_CIC_LFR <= INT_0_d0;
188 END IF;
189
190
150
191 WHEN WAIT_step => ---------------------------------------------------
151 WHEN RUN_PROG_I =>
192 IF nb_cycle_wait > 0 THEN
152 IF current_cmd = PROG_END_I THEN
193 nb_cycle_wait <= nb_cycle_wait -1;
153 IF current_channel = 5 THEN
194 ELSE
154 current_channel <= 0;
195 STATE_CIC_LFR <= STATE_CIC_LFR_pre;
155 IF nb_data_receipt MOD 16 = 0 THEN
196 END IF;
156 STATE_CIC_LFR <= RUN_PROG_C16;
197
157 current_cmd <= PROG_START_C16;
198
158 sample_16_odd <= NOT sample_16_odd;
199 WHEN INT_0 => -------------------------------------------------------
159 ELSE
200 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));
201 r_addr_init <= '1';
202 r_addr_base <= base_addr_INT(current_channel);
203 nb_cycle_wait <= 1;
204 op_ADD_SUBn <= '1';
205 op_valid <= '1';
206 STATE_CIC_LFR <= WAIT_step;
207 STATE_CIC_LFR_pre <= INT_1;
208
209 WHEN INT_1 =>
210 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3));
211 r_addr_add1 <= '1';
212 nb_cycle_wait <= 3;
213 op_ADD_SUBn <= '1';
214 op_valid <= '1';
215 STATE_CIC_LFR <= INT_2;
216
217 WHEN INT_2 =>
218 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3));
219 r_addr_add1 <= '1';
220 nb_cycle_wait <= 3;
221 op_ADD_SUBn <= '1';
222 op_valid <= '1';
223 IF nb_data_receipt = 256 THEN
224 STATE_CIC_LFR <= COMB_0_256_d0;
225 ELSIF (nb_data_receipt mod 16) = 0 THEN
226 STATE_CIC_LFR <= WAIT_INT_to_COMB_16;
227 ELSE
228 IF current_channel = 5 THEN
229 STATE_CIC_LFR <= IDLE;
160 STATE_CIC_LFR <= IDLE;
230 ELSE
161 END IF;
231 current_channel <= current_channel +1;
232 STATE_CIC_LFR <= INT_0;
233 END IF;
234 END IF;
235
236 -------------------------------------------------------------------
237 WHEN WAIT_INT_to_COMB_16 =>
238 STATE_CIC_LFR <= COMB_0_16_d0;
239
240 WHEN COMB_0_16_d0 => STATE_CIC_LFR <= COMB_0_16_d1;
241 WHEN COMB_0_16_d1 => STATE_CIC_LFR <= COMB_1_16_d0;
242
243 WHEN COMB_1_16_d0 => STATE_CIC_LFR <= COMB_1_16_d1;
244 WHEN COMB_1_16_d1 => STATE_CIC_LFR <= COMB_2_16_d0;
245
246 WHEN COMB_2_16_d0 => STATE_CIC_LFR <= COMB_2_16_d1;
247 WHEN COMB_2_16_d1 =>
248 IF current_channel = 5 THEN
249 STATE_CIC_LFR <= IDLE;
250 IF nb_data_receipt = 256 THEN
251 nb_data_receipt <= 0;
252 END IF;
253 ELSE
162 ELSE
254 current_channel <= current_channel +1;
163 current_channel <= current_channel +1;
255 STATE_CIC_LFR <= INT_0_d0;
164 current_cmd <= PROG_START_I;
165 END IF;
166 ELSE
167 current_cmd <= current_cmd +1;
168 END IF;
169
170 WHEN RUN_PROG_C16 =>
171 IF current_cmd = PROG_END_C16 THEN
172 data_out_16_valid <= '1';
173 IF current_channel = 5 THEN
174 current_channel <= 0;
175 IF nb_data_receipt MOD 256 = 0 THEN
176 sample_256_odd <= NOT sample_256_odd;
177 STATE_CIC_LFR <= RUN_PROG_C256;
178 current_cmd <= PROG_START_C256;
179 ELSE
180 STATE_CIC_LFR <= IDLE;
181 END IF;
182 ELSE
183 current_channel <= current_channel +1;
184 current_cmd <= PROG_START_C16;
256 END IF;
185 END IF;
257
186 ELSE
258 -------------------------------------------------------------------
187 current_cmd <= current_cmd +1;
259 WHEN COMB_0_256_d0 => STATE_CIC_LFR <= COMB_0_256_d1;
188 END IF;
260 WHEN COMB_0_256_d1 => STATE_CIC_LFR <= COMB_0_256_d2;
189
261 WHEN COMB_0_256_d2 => STATE_CIC_LFR <= COMB_1_256_d0;
190 WHEN RUN_PROG_C256 =>
262
191 IF current_cmd = PROG_END_C256 THEN
263 WHEN COMB_1_256_d0 => STATE_CIC_LFR <= COMB_1_256_d1;
192 data_out_256_valid <= '1';
264 WHEN COMB_1_256_d1 => STATE_CIC_LFR <= COMB_1_256_d2;
193 IF current_channel = 5 THEN
265 WHEN COMB_1_256_d2 => STATE_CIC_LFR <= COMB_2_256_d0;
194 nb_data_receipt <= 0;
266
195 current_channel <= 0;
267 WHEN COMB_2_256_d0 => STATE_CIC_LFR <= COMB_2_256_d1;
196 STATE_CIC_LFR <= IDLE;
268 WHEN COMB_2_256_d1 => STATE_CIC_LFR <= COMB_2_256_d2;
197 ELSE
269 WHEN COMB_2_256_d2 => STATE_CIC_LFR <= READ_INT_2_d0;
198 current_channel <= current_channel +1;
270
199 current_cmd <= PROG_START_C256;
271 -------------------------------------------------------------------
200 END IF;
272 WHEN READ_INT_2_d0 => STATE_CIC_LFR <= READ_INT_2_d1;
201 ELSE
273 WHEN READ_INT_2_d1 => STATE_CIC_LFR <= COMB_0_16_d0;
202 current_cmd <= current_cmd +1;
274
203 END IF;
275 WHEN OTHERS => NULL;
204
276 END CASE;
205 WHEN OTHERS => NULL;
277 END IF;
206 END CASE;
278 END IF;
207 END IF;
279 END PROCESS;
208 END PROCESS;
280
209
281 END beh;
210 END beh;
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@@ -24,6 +24,9
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26
26
27 LIBRARY lpp;
28 USE lpp.data_type_pkg.ALL;
29
27 PACKAGE cic_pkg IS
30 PACKAGE cic_pkg IS
28
31
29 -----------------------------------------------------------------------------
32 -----------------------------------------------------------------------------
@@ -88,6 +91,22 PACKAGE cic_pkg IS
88
91
89
92
90 -----------------------------------------------------------------------------
93 -----------------------------------------------------------------------------
94 COMPONENT cic_lfr
95 GENERIC (
96 tech : INTEGER;
97 use_RAM_nCEL : INTEGER);
98 PORT (
99 clk : IN STD_LOGIC;
100 rstn : IN STD_LOGIC;
101 run : IN STD_LOGIC;
102 data_in : IN sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
103 data_in_valid : IN STD_LOGIC;
104 data_out_16 : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
105 data_out_16_valid : OUT STD_LOGIC;
106 data_out_256 : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
107 data_out_256_valid : OUT STD_LOGIC);
108 END COMPONENT;
109
91 COMPONENT cic_lfr_control
110 COMPONENT cic_lfr_control
92 PORT (
111 PORT (
93 clk : IN STD_LOGIC;
112 clk : IN STD_LOGIC;
@@ -96,16 +115,33 PACKAGE cic_pkg IS
96 data_in_valid : IN STD_LOGIC;
115 data_in_valid : IN STD_LOGIC;
97 data_out_16_valid : OUT STD_LOGIC;
116 data_out_16_valid : OUT STD_LOGIC;
98 data_out_256_valid : OUT STD_LOGIC;
117 data_out_256_valid : OUT STD_LOGIC;
99 sel_sample : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
118 OPERATION : OUT STD_LOGIC_VECTOR(14 DOWNTO 0));
100 op_valid : OUT STD_LOGIC;
101 op_ADD_SUBn : OUT STD_LOGIC;
102 r_addr_init : OUT STD_LOGIC;
103 r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
104 r_addr_add1 : OUT STD_LOGIC;
105 w_en : OUT STD_LOGIC;
106 w_addr_init : OUT STD_LOGIC;
107 w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
108 w_addr_add1 : OUT STD_LOGIC);
109 END COMPONENT;
119 END COMPONENT;
120
121 COMPONENT cic_lfr_add_sub
122 PORT (
123 clk : IN STD_LOGIC;
124 rstn : IN STD_LOGIC;
125 run : IN STD_LOGIC;
126 OP : IN STD_LOGIC_VECTOR( 1 DOWNTO 0);
127 data_in_A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
128 data_in_B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
129 data_in_Carry : IN STD_LOGIC;
130 data_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
131 data_out_Carry : OUT STD_LOGIC);
132 END COMPONENT;
133
134 COMPONENT cic_lfr_address_gen
135 PORT (
136 clk : IN STD_LOGIC;
137 rstn : IN STD_LOGIC;
138 run : IN STD_LOGIC;
139 addr_base : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
140 addr_init : IN STD_LOGIC;
141 addr_add_1 : IN STD_LOGIC;
142 addr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
143 END COMPONENT;
144
145
110 -----------------------------------------------------------------------------
146 -----------------------------------------------------------------------------
111 END cic_pkg;
147 END cic_pkg;
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@@ -5,3 +5,5 cic_downsampler.vhd
5 cic_comb.vhd
5 cic_comb.vhd
6 cic_lfr.vhd
6 cic_lfr.vhd
7 cic_lfr_control.vhd
7 cic_lfr_control.vhd
8 cic_lfr_add_sub.vhd
9 cic_lfr_address_gen.vhd
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