# HG changeset patch
# User pellion
# Date 2014-11-25 12:53:42
# Node ID 53d8882e79501fe5aa1df1fbb96cf43b7a9224c4
# Parent  8e0c2cb85822b28012440747102afe6bc224c1df

CIC-LFR temp

diff --git a/designs/Validation_CIC/from_Paul/cic_with_RAM.ods b/designs/Validation_CIC/from_Paul/cic_with_RAM.ods
index 00c8fcbc23f5dbaf1f8cfdbedcc7d31d1b2d58df..e09b15fe744088d54fbb29ebee5113d8b3c6aef0
GIT binary patch
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diff --git a/lib/lpp/dsp/cic/cic_lfr.vhd b/lib/lpp/dsp/cic/cic_lfr.vhd
--- a/lib/lpp/dsp/cic/cic_lfr.vhd
+++ b/lib/lpp/dsp/cic/cic_lfr.vhd
@@ -23,10 +23,15 @@
 
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.all;
 
 LIBRARY lpp;
 USE lpp.cic_pkg.ALL;
 USE lpp.data_type_pkg.ALL;
+USE lpp.iir_filter.ALL;
+
+LIBRARY techmap;
+USE techmap.gencomp.ALL;
 
 ENTITY cic_lfr IS
   GENERIC(
@@ -50,21 +55,225 @@ ENTITY cic_lfr IS
 END cic_lfr;
 
 ARCHITECTURE beh OF cic_lfr IS
+  --
+  CONSTANT S_parameter : INTEGER := 2;
+  --
   SIGNAL sel_sample  : STD_LOGIC_VECTOR(2 DOWNTO 0);
-  SIGNAL sample_temp : sample_vector(3 DOWNTO 0,15 DOWNTO 0);
+  SIGNAL sample_temp : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
   SIGNAL sample      : STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+  SIGNAL OPERATION    : STD_LOGIC_VECTOR(14 DOWNTO 0);
+  
+  -- ALU
+  SIGNAL data_in_A      : STD_LOGIC_VECTOR(15 DOWNTO 0);
+  SIGNAL data_in_B      : STD_LOGIC_VECTOR(15 DOWNTO 0);
+  SIGNAL data_in_Carry  : STD_LOGIC;
+  SIGNAL data_out_Carry : STD_LOGIC;
+
+  SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter DOWNTO 0);
+
+  -----------------------------------------------------------------------------
+  TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
+  SIGNAL   base_addr_INT   : ARRAY_OF_ADDR;
+  CONSTANT base_addr_delta : INTEGER := 40;
+  SIGNAL addr_base_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  SIGNAL addr_gen: STD_LOGIC_VECTOR(7 DOWNTO 0);
+  SIGNAL addr_read: STD_LOGIC_VECTOR(7 DOWNTO 0);
+  SIGNAL addr_write: STD_LOGIC_VECTOR(7 DOWNTO 0);
+  SIGNAL data_we: STD_LOGIC;
+  SIGNAL data_wen       : STD_LOGIC;
+  SIGNAL data_write     : STD_LOGIC_VECTOR(15 DOWNTO 0);
+  SIGNAL data_read      : STD_LOGIC_VECTOR(15 DOWNTO 0);
+  -----------------------------------------------------------------------------
+  SIGNAL sample_out_reg16   : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
+  SIGNAL sample_out_reg256  : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
+  SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(6 DOWNTO 0);
+  SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6 DOWNTO 0);
+  SIGNAL  data_out_16_valid_s  : STD_LOGIC;
+  SIGNAL  data_out_256_valid_s : STD_LOGIC;
+    
 BEGIN
 
   -----------------------------------------------------------------------------
   -- SEL_SAMPLE
   -----------------------------------------------------------------------------
+  sel_sample <= OPERATION(5 DOWNTO 3);
   all_bit: FOR I IN 15 DOWNTO 0 GENERATE
     sample_temp(0,I) <= data_in(0,I)     WHEN sel_sample(0) = '0' ELSE data_in(1,I);
-    sample_temp(1,I) <= data_in(3,I)     WHEN sel_sample(0) = '0' ELSE data_in(4,I);
-    sample_temp(2,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE data_in(2,I);
-    sample_temp(3,I) <= sample_temp(1,I) WHEN sel_sample(1) = '0' ELSE data_in(5,I);
-    sample(I)        <= sample_temp(2,I) WHEN sel_sample(2) = '0' ELSE sample_temp(3,I);
-  END GENERATE all_bit;
+    sample_temp(1,I) <= data_in(2,I)     WHEN sel_sample(0) = '0' ELSE data_in(3,I);
+    sample_temp(2,I) <= data_in(4,I)     WHEN sel_sample(0) = '0' ELSE data_in(5,I);
+    sample_temp(3,I) <= data_write(I)    WHEN sel_sample(0) = '0' ELSE '0';
+
+    sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I);
+    sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE sample_temp(3,I);
+    
+    sample(I)        <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I);
+  END GENERATE all_bit;  
+
+  data_in_A <= sample;
+  
+  -----------------------------------------------------------------------------
+  -- ALU
+  -----------------------------------------------------------------------------
+  ALU: cic_lfr_add_sub
+    PORT MAP (
+      clk            => clk,
+      rstn           => rstn,
+      run            => run,
+
+      OP             => OPERATION(1 DOWNTO 0),
+
+      data_in_A      => sample,
+      data_in_B      => data_read,
+      data_in_Carry  => data_in_Carry,
+      
+      data_out       => data_write,
+      data_out_Carry => data_out_Carry);
+
+  PROCESS (clk, rstn)
+  BEGIN  -- PROCESS
+    IF rstn = '0' THEN                  -- asynchronous reset (active low)
+      carry_reg <= (OTHERS => '0');
+    ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+      carry_reg(0) <= data_out_Carry;
+      all_carry: FOR I IN S_parameter DOWNTO 1 LOOP
+        carry_reg(I) <= carry_reg(I-1);
+      END LOOP all_carry;
+    END IF;
+  END PROCESS;
+
+  data_in_Carry <= carry_reg(S_parameter-1) WHEN OPERATION(2) = '0' ELSE carry_reg(S_parameter);
+
+  -----------------------------------------------------------------------------
+  -- MEMORY
+  -----------------------------------------------------------------------------
+  all_channel: FOR I IN 5 DOWNTO 0 GENERATE
+    all_bit: FOR J IN 7 DOWNTO 0 GENERATE
+      base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
+    END GENERATE all_bit;
+  END GENERATE all_channel;
+  
+  addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(11 DOWNTO 9))));
+  
+
+  cic_lfr_address_gen_1: cic_lfr_address_gen
+    PORT MAP (
+      clk               => clk,
+      rstn              => rstn,
+      run               => run,
+      
+      addr_base         => addr_base_sel,
+      addr_init         => OPERATION(7),
+      addr_add_1        => OPERATION(8),
+      addr              => addr_gen);
+
+    
+  addr_read <= addr_gen                                                               WHEN OPERATION(14 DOWNTO 12) = "000" ELSE
+               STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+2,8)) WHEN OPERATION(14 DOWNTO 12) = "001" ELSE
+               STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+5,8)) WHEN OPERATION(14 DOWNTO 12) = "010" ELSE
+               STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+8,8)) WHEN OPERATION(14 DOWNTO 12) = "011" ELSE
+               STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen     ))+6,8));
+  
+  PROCESS (clk, rstn)
+  BEGIN  -- PROCESS
+    IF rstn = '0' THEN                  -- asynchronous reset (active low)
+      addr_write <= (OTHERS => '0');
+      data_we    <= '0';
+    ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+      addr_write <= addr_read;
+      data_we    <= OPERATION(6);
+    END IF;
+  END PROCESS;
+  
+  memCEL : IF use_RAM_nCEL = 0 GENERATE
+    data_wen <= NOT data_we;
+    RAMblk : RAM_CEL
+      GENERIC MAP(16, 8)
+      PORT MAP(
+        WD    => data_write,
+        RD    => data_read,
+        WEN   => data_wen,
+        REN   => '0',
+        WADDR => addr_write,
+        RADDR => addr_read,
+        RWCLK => clk,
+        RESET => rstn
+        ) ;
+  END GENERATE;
+
+  memRAM : IF use_RAM_nCEL = 1 GENERATE
+    SRAM : syncram_2p
+      GENERIC MAP(tech, 8, 16)
+      PORT MAP(clk, '1', addr_read,  data_read,
+               clk, data_we, addr_write, data_write);
+  END GENERATE;
+
+  -----------------------------------------------------------------------------
+  -- CONTROL
+  -----------------------------------------------------------------------------
+  cic_lfr_control_1: cic_lfr_control
+    PORT MAP (
+      clk                => clk,
+      rstn               => rstn,
+      run                => run,
+      data_in_valid      => data_in_valid,
+      data_out_16_valid  => data_out_16_valid_s,
+      data_out_256_valid => data_out_256_valid_s,
+      OPERATION          => OPERATION);
+
+  PROCESS (clk, rstn)
+  BEGIN  -- PROCESS
+    IF rstn = '0' THEN                  -- asynchronous reset (active low)
+      sample_valid_reg16  <= "0000001";
+      sample_valid_reg256 <= "0000001";
+    ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+      IF run = '0' THEN
+        sample_valid_reg16  <= "0000001";
+        sample_valid_reg256 <= "0000001";
+      ELSE
+        IF data_out_16_valid_s = '1' OR sample_valid_reg16(6) = '1' THEN
+          sample_valid_reg16  <= sample_valid_reg16(5 DOWNTO 0)  & sample_valid_reg16(6);
+        END IF;
+        IF data_out_256_valid_s = '1' OR sample_valid_reg256(6) = '1' THEN
+          sample_valid_reg256 <= sample_valid_reg256(5 DOWNTO 0) & sample_valid_reg256(6);
+        END IF;
+      END IF;      
+    END IF;
+  END PROCESS;
+
+  data_out_16_valid  <= sample_valid_reg16(6);
+  data_out_256_valid <= sample_valid_reg256(6);
+
+  -----------------------------------------------------------------------------
+  data_out_256 <= sample_out_reg256;
+  data_out_16  <= sample_out_reg16;
+  
+  all_channel_out: FOR I IN 5 DOWNTO 0 GENERATE
+    all_bits: FOR J IN 15 DOWNTO 0 GENERATE
+
+      PROCESS (clk, rstn)
+      BEGIN  -- PROCESS
+        IF rstn = '0' THEN              -- asynchronous reset (active low)
+          sample_out_reg16(I,J)  <= '0';
+          sample_out_reg256(I,J) <= '0';
+        ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+          IF run = '0' THEN
+            sample_out_reg16(I,J)  <= '0';
+            sample_out_reg256(I,J) <= '0';
+          ELSE
+            IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s = '1' THEN
+              sample_out_reg16(I,J) <= data_write(J);
+            END IF;
+            IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s = '1' THEN
+              sample_out_reg256(I,J) <= data_write(J);
+            END IF;
+          END IF;
+        END IF;
+      END PROCESS;
+      
+    END GENERATE all_bits;
+  END GENERATE all_channel_out;  
+  
   
 END beh;
 
diff --git a/lib/lpp/dsp/cic/cic_lfr_control.vhd b/lib/lpp/dsp/cic/cic_lfr_control.vhd
--- a/lib/lpp/dsp/cic/cic_lfr_control.vhd
+++ b/lib/lpp/dsp/cic/cic_lfr_control.vhd
@@ -39,20 +39,8 @@ ENTITY cic_lfr_control IS
     data_in_valid      : IN  STD_LOGIC;
     data_out_16_valid  : OUT STD_LOGIC;
     data_out_256_valid : OUT STD_LOGIC;
-    -- dataflow
-    sel_sample  : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
     --
-    op_valid    : OUT STD_LOGIC;
-    op_ADD_SUBn : OUT STD_LOGIC;
-    --
-    r_addr_init : OUT STD_LOGIC;
-    r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-    r_addr_add1 : OUT STD_LOGIC;
-    --
-    w_en        : OUT STD_LOGIC;
-    w_addr_init : OUT STD_LOGIC;
-    w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-    w_addr_add1 : OUT STD_LOGIC
+    OPERATION          : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
     );
 
 END cic_lfr_control;
@@ -60,222 +48,163 @@ END cic_lfr_control;
 ARCHITECTURE beh OF cic_lfr_control IS
 
   TYPE STATE_CIC_LFR_TYPE IS (IDLE,
-                              
-                              INT_0_d0,      INT_1_d0,      INT_2_d0,
-                              INT_0_d1,      INT_1_d1,      INT_2_d1,
-                              INT_0_d2,      INT_1_d2,      INT_2_d2,
-                              
-                              WAIT_INT_to_COMB_16,
-                              
-                              COMB_0_16_d0,  COMB_1_16_d0,  COMB_2_16_d0,
-                              COMB_0_16_d1,  COMB_1_16_d1,  COMB_2_16_d1,
-                              
-                              COMB_0_256_d0, COMB_1_256_d0, COMB_2_256_d0,
-                              COMB_0_256_d1, COMB_1_256_d1, COMB_2_256_d1,
-                              COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2,
-                              
-                              READ_INT_2_d0,
-                              READ_INT_2_d1,
-                              
-                              Wait_step,
-                              INT_0,      INT_1,      INT_2
+                              RUN_PROG_I,
+                              RUN_PROG_C16,
+                              RUN_PROG_C256
                               );
   
   SIGNAL STATE_CIC_LFR     : STATE_CIC_LFR_TYPE;
-  SIGNAL STATE_CIC_LFR_pre : STATE_CIC_LFR_TYPE;
+
+  SIGNAL nb_data_receipt : INTEGER := 0;
+  SIGNAL current_cmd : INTEGER := 0;
+  SIGNAL current_channel : INTEGER := 0;
+  SIGNAL sample_16_odd : STD_LOGIC;
+  SIGNAL sample_256_odd : STD_LOGIC;
 
-  SIGNAL nb_data_receipt : INTEGER;
-  SIGNAL current_channel : INTEGER;
+  TYPE PROGRAM_ARRAY IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(11 DOWNTO 0);
+  --OPERATION( 8 DOWNTO  0) <= PROGRAM_ARRAY( 8 DOWNTO 0) sauf pour PROG_I(0)
+  --OPERATION(13 DOWNTO 12) <= PROGRAM_ARRAY(10 DOWNTO 9)
+  --OPERATION(11 DOWNTO  9) <= current_channel
+  --OPERATION(14)           <= PROGRAM_ARRAY(11) selon sample_X_odd et l'etat
+  CONSTANT PROG : PROGRAM_ARRAY(0 TO 28) :=
+    (
+      --PROG I
+      "0001"&X"C0",                        --0
+      "0001"&X"70",                        --1
+      "0001"&X"70",                        --2
+      "0001"&X"7A",                        --3
+      "0001"&X"7A",                        --4
+      "0001"&X"7A",                        --5
+      "0001"&X"7A",                        --6
+      "0001"&X"7A",                        --7
+      "0001"&X"7A",                        --8
+      --PROG_C16
+      "0010"&X"38",                        --9
+      "1001"&X"71",                        --10
+      "1001"&X"71",                        --11
+      "1001"&X"71",                        --12
+      "0100"&X"38",                        --13
+      "1001"&X"77",                        --14
+      "1001"&X"77",                        --15
+      "1001"&X"77",                        --16
+      --PROG_C256
+      "0010"&X"38",                        --17
+      "1001"&X"71",                        --18
+      "1001"&X"71",                        --19
+      "1001"&X"71",                        --20
+      "0100"&X"38",                        --21
+      "1001"&X"77",                        --22
+      "1001"&X"77",                        --23
+      "1001"&X"77",                        --24
+      "0110"&X"38",                        --25
+      "1001"&X"77",                        --26
+      "1001"&X"77",                        --27
+      "1001"&X"77"                         --28
+     );
 
-  TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
   
-  SIGNAL   base_addr_INT   : ARRAY_OF_ADDR;
-  CONSTANT base_addr_delta : INTEGER := 40;
-
-  CONSTANT SEL_OUT : INTEGER := 6;
+  CONSTANT PROG_START_I    : INTEGER := 0;
+  CONSTANT PROG_END_I      : INTEGER := 8;
+  CONSTANT PROG_START_C16  : INTEGER := 9;
+  CONSTANT PROG_END_C16    : INTEGER := 16;
+  CONSTANT PROG_START_C256 : INTEGER := 17;
+  CONSTANT PROG_END_C256   : INTEGER := 28;
   
-  signal nb_cycle_wait : integer;
 BEGIN
 
-  all_channel: FOR I IN 5 DOWNTO 0 GENERATE
-    all_bit: FOR J IN 7 DOWNTO 0 GENERATE
-      base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
-    END GENERATE all_bit;
-  END GENERATE all_channel;
+  OPERATION( 1 DOWNTO  0) <= PROG(current_cmd)( 1 DOWNTO 0);
+  OPERATION( 2 )          <= '0' WHEN STATE_CIC_LFR = IDLE ELSE
+                             PROG(current_cmd)( 2 );
+  OPERATION( 5 DOWNTO  3) <= STD_LOGIC_VECTOR(to_unsigned(current_channel,3)) WHEN STATE_CIC_LFR = RUN_PROG_I AND current_cmd = 0 ELSE
+                             PROG(current_cmd)(5 DOWNTO  3);
+  OPERATION( 8 DOWNTO  6) <= "000" WHEN STATE_CIC_LFR = IDLE ELSE
+                             PROG(current_cmd)( 8 DOWNTO 6);
+  OPERATION(11 DOWNTO  9) <= STD_LOGIC_VECTOR(to_unsigned(current_channel,3));
+  OPERATION(13 DOWNTO 12) <= PROG(current_cmd)(10 DOWNTO 9);  
+  OPERATION(14)           <= PROG(current_cmd)(11) AND sample_16_odd  WHEN STATE_CIC_LFR = RUN_PROG_C16  ELSE
+                             PROG(current_cmd)(11) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
 
   PROCESS (clk, rstn)
-  BEGIN  -- PROCESS
-    IF rstn = '0' THEN                  -- asynchronous reset (active low)
-      STATE_CIC_LFR      <= IDLE;
-      --
+  BEGIN
+    IF rstn = '0' THEN
+      STATE_CIC_LFR <= IDLE;
+      nb_data_receipt <= 0;
+      current_channel <= 0;
+      current_cmd     <= 0;
+      sample_16_odd <= '0';
+      sample_256_odd <= '0';
       data_out_16_valid  <= '0';
-      data_out_256_valid <= '0';
-      --
-      sel_sample  <= (OTHERS => '0');
-      --
-      op_valid    <= '0';
-      op_ADD_SUBn <= '0';
-      --
-      r_addr_init <= '0';
-      r_addr_base <= (OTHERS => '0');
-      r_addr_add1 <= '0';
-      --
-      w_en        <= '1';
-      w_addr_init <= '0';
-      w_addr_base <= (OTHERS => '0');
-      w_addr_add1 <= '0';
-      --
-      nb_data_receipt <= 0;
-    ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+      data_out_256_valid  <= '0';
+      
+    ELSIF clk'event AND clk = '1' THEN
       data_out_16_valid  <= '0';
-      data_out_256_valid <= '0';
-      op_valid    <= '0';
-      op_ADD_SUBn <= '0';
-      r_addr_init <= '0';
-      r_addr_base <= (OTHERS => '0');
-      r_addr_add1 <= '0';
-      w_en        <= '1';
-      w_addr_init <= '0';
-      w_addr_base <= (OTHERS => '0');
-      w_addr_add1 <= '0';
-
-      IF run = '0' THEN
-        STATE_CIC_LFR      <= IDLE;
-        --
-        data_out_16_valid  <= '0';
-        data_out_256_valid <= '0';
-        --
-        sel_sample  <= (OTHERS => '0');
-        --
-        op_valid    <= '0';
-        op_ADD_SUBn <= '0';
-        --
-        r_addr_init <= '0';
-        r_addr_base <= (OTHERS => '0');
-        r_addr_add1 <= '0';
-        --
-        w_en        <= '1';
-        w_addr_init <= '0';
-        w_addr_base <= (OTHERS => '0');
-        w_addr_add1 <= '0';
-        --
-        nb_data_receipt <= 0;
-        current_channel   <= 0;
-      ELSE
-        CASE STATE_CIC_LFR IS
-          WHEN IDLE => 
-            data_out_16_valid  <= '0';
-            data_out_256_valid <= '0';
-            --
-            sel_sample  <= (OTHERS => '0');
-            --
-            op_valid    <= '0';
-            op_ADD_SUBn <= '0';
-            --
-            r_addr_init <= '0';
-            r_addr_base <= (OTHERS => '0');
-            r_addr_add1 <= '0';
-            --
-            w_en        <= '1';
-            w_addr_init <= '0';
-            w_addr_base <= (OTHERS => '0');
-            w_addr_add1 <= '0';
-            --
-            IF data_in_valid = '1' THEN
-              nb_data_receipt   <= nb_data_receipt+1;
-              current_channel   <= 0;
-              STATE_CIC_LFR     <= INT_0_d0;
-            END IF;
-
+      data_out_256_valid  <= '0';
+      CASE STATE_CIC_LFR IS
+        WHEN IDLE =>
+          IF data_in_valid = '1' THEN
+            STATE_CIC_LFR   <= RUN_PROG_I;
+            current_cmd     <= PROG_START_I;
+            current_channel <= 0;
+            nb_data_receipt <= nb_data_receipt + 1;
+          END IF;
           
-          WHEN WAIT_step => ---------------------------------------------------
-            IF nb_cycle_wait > 0 THEN
-              nb_cycle_wait <= nb_cycle_wait -1;
-            ELSE
-              STATE_CIC_LFR <= STATE_CIC_LFR_pre;
-            END IF;
-            
-            
-          WHEN INT_0 => -------------------------------------------------------
-            sel_sample        <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));
-            r_addr_init       <= '1';
-            r_addr_base       <= base_addr_INT(current_channel);
-            nb_cycle_wait     <= 1;
-            op_ADD_SUBn       <= '1';
-            op_valid          <= '1';
-            STATE_CIC_LFR     <= WAIT_step;
-            STATE_CIC_LFR_pre <= INT_1;
-                        
-          WHEN INT_1 => 
-            sel_sample    <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3)); 
-            r_addr_add1   <= '1';
-            nb_cycle_wait <= 3;
-            op_ADD_SUBn   <= '1';
-            op_valid      <= '1';
-            STATE_CIC_LFR <= INT_2;
-                        
-          WHEN INT_2 => 
-            sel_sample    <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3)); 
-            r_addr_add1   <= '1';
-            nb_cycle_wait <= 3;
-            op_ADD_SUBn   <= '1';
-            op_valid      <= '1';
-            IF nb_data_receipt = 256 THEN
-              STATE_CIC_LFR <= COMB_0_256_d0;
-            ELSIF (nb_data_receipt mod 16) = 0 THEN
-              STATE_CIC_LFR   <= WAIT_INT_to_COMB_16;
-            ELSE
-              IF current_channel = 5 THEN
+        WHEN RUN_PROG_I =>
+          IF current_cmd = PROG_END_I THEN
+            IF current_channel = 5 THEN
+              current_channel <= 0;
+              IF nb_data_receipt MOD 16 = 0 THEN
+                STATE_CIC_LFR   <= RUN_PROG_C16;
+                current_cmd     <= PROG_START_C16;     
+                sample_16_odd   <= NOT sample_16_odd;
+              ELSE
                 STATE_CIC_LFR   <= IDLE;
-              ELSE
-                current_channel <= current_channel +1;
-                STATE_CIC_LFR   <= INT_0;
-              END IF;
-            END IF;
-
-            -------------------------------------------------------------------
-          WHEN WAIT_INT_to_COMB_16 =>
-            STATE_CIC_LFR   <= COMB_0_16_d0;
-
-          WHEN COMB_0_16_d0 => STATE_CIC_LFR <= COMB_0_16_d1;
-          WHEN COMB_0_16_d1 => STATE_CIC_LFR <= COMB_1_16_d0;
-                               
-          WHEN COMB_1_16_d0 => STATE_CIC_LFR <= COMB_1_16_d1;
-          WHEN COMB_1_16_d1 => STATE_CIC_LFR <= COMB_2_16_d0;
-
-          WHEN COMB_2_16_d0 => STATE_CIC_LFR <= COMB_2_16_d1;
-          WHEN COMB_2_16_d1 =>
-            IF current_channel = 5 THEN
-              STATE_CIC_LFR <= IDLE;
-              IF nb_data_receipt = 256 THEN
-                nb_data_receipt   <= 0;
-              END IF;
+              END IF;              
             ELSE
               current_channel <= current_channel +1;
-              STATE_CIC_LFR   <= INT_0_d0;
+              current_cmd     <= PROG_START_I;
+            END IF;
+          ELSE
+            current_cmd <= current_cmd +1;
+          END IF;
+          
+        WHEN RUN_PROG_C16 =>
+          IF current_cmd = PROG_END_C16 THEN
+            data_out_16_valid <= '1';
+            IF current_channel = 5 THEN
+              current_channel <= 0;
+              IF nb_data_receipt MOD 256 = 0 THEN 
+                sample_256_odd  <= NOT sample_256_odd;
+                STATE_CIC_LFR   <= RUN_PROG_C256;
+                current_cmd     <= PROG_START_C256;     
+              ELSE
+                STATE_CIC_LFR   <= IDLE;
+              END IF;              
+            ELSE
+              current_channel <= current_channel +1;
+              current_cmd     <= PROG_START_C16;
             END IF;
-
-            -------------------------------------------------------------------
-          WHEN COMB_0_256_d0 => STATE_CIC_LFR <= COMB_0_256_d1;
-          WHEN COMB_0_256_d1 => STATE_CIC_LFR <= COMB_0_256_d2;
-          WHEN COMB_0_256_d2 => STATE_CIC_LFR <= COMB_1_256_d0;
-                             
-          WHEN COMB_1_256_d0 => STATE_CIC_LFR <= COMB_1_256_d1;
-          WHEN COMB_1_256_d1 => STATE_CIC_LFR <= COMB_1_256_d2;
-          WHEN COMB_1_256_d2 => STATE_CIC_LFR <= COMB_2_256_d0;
-                             
-          WHEN COMB_2_256_d0 => STATE_CIC_LFR <= COMB_2_256_d1;
-          WHEN COMB_2_256_d1 => STATE_CIC_LFR <= COMB_2_256_d2;
-          WHEN COMB_2_256_d2 => STATE_CIC_LFR <= READ_INT_2_d0;
-
-            -------------------------------------------------------------------
-          WHEN READ_INT_2_d0 => STATE_CIC_LFR <= READ_INT_2_d1;
-          WHEN READ_INT_2_d1 => STATE_CIC_LFR <= COMB_0_16_d0;
-            
-          WHEN OTHERS => NULL;
-        END CASE;
-      END IF;
+          ELSE
+            current_cmd <= current_cmd +1;
+          END IF;
+                    
+        WHEN RUN_PROG_C256 =>
+          IF current_cmd = PROG_END_C256 THEN
+            data_out_256_valid <= '1';
+            IF current_channel = 5 THEN
+              nb_data_receipt <= 0;
+              current_channel <= 0;
+              STATE_CIC_LFR   <= IDLE;
+            ELSE
+              current_channel <= current_channel +1;
+              current_cmd     <= PROG_START_C256;
+            END IF;
+          ELSE
+            current_cmd <= current_cmd +1;
+          END IF;
+          
+        WHEN OTHERS => NULL;
+      END CASE;
     END IF;
   END PROCESS;
-  
+
 END beh;
diff --git a/lib/lpp/dsp/cic/cic_pkg.vhd b/lib/lpp/dsp/cic/cic_pkg.vhd
--- a/lib/lpp/dsp/cic/cic_pkg.vhd
+++ b/lib/lpp/dsp/cic/cic_pkg.vhd
@@ -24,6 +24,9 @@
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
 
+LIBRARY lpp;
+USE lpp.data_type_pkg.ALL;
+
 PACKAGE cic_pkg IS
 
   -----------------------------------------------------------------------------
@@ -88,6 +91,22 @@ PACKAGE cic_pkg IS
 
 
   -----------------------------------------------------------------------------
+  COMPONENT cic_lfr
+    GENERIC (
+      tech         : INTEGER;
+      use_RAM_nCEL : INTEGER);
+    PORT (
+      clk                : IN  STD_LOGIC;
+      rstn               : IN  STD_LOGIC;
+      run                : IN  STD_LOGIC;
+      data_in            : IN  sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
+      data_in_valid      : IN  STD_LOGIC;
+      data_out_16        : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
+      data_out_16_valid  : OUT STD_LOGIC;
+      data_out_256       : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
+      data_out_256_valid : OUT STD_LOGIC);
+  END COMPONENT;
+
   COMPONENT cic_lfr_control
     PORT (
       clk                : IN  STD_LOGIC;
@@ -96,16 +115,33 @@ PACKAGE cic_pkg IS
       data_in_valid      : IN  STD_LOGIC;
       data_out_16_valid  : OUT STD_LOGIC;
       data_out_256_valid : OUT STD_LOGIC;
-      sel_sample         : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
-      op_valid           : OUT STD_LOGIC;
-      op_ADD_SUBn        : OUT STD_LOGIC;
-      r_addr_init        : OUT STD_LOGIC;
-      r_addr_base        : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-      r_addr_add1        : OUT STD_LOGIC;
-      w_en               : OUT STD_LOGIC;
-      w_addr_init        : OUT STD_LOGIC;
-      w_addr_base        : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-      w_addr_add1        : OUT STD_LOGIC);
+      OPERATION          : OUT STD_LOGIC_VECTOR(14 DOWNTO 0));
   END COMPONENT;
+
+  COMPONENT cic_lfr_add_sub
+    PORT (
+      clk            : IN  STD_LOGIC;
+      rstn           : IN  STD_LOGIC;
+      run            : IN  STD_LOGIC;
+      OP             : IN  STD_LOGIC_VECTOR( 1 DOWNTO 0);
+      data_in_A      : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+      data_in_B      : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+      data_in_Carry  : IN  STD_LOGIC;
+      data_out       : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+      data_out_Carry : OUT STD_LOGIC);
+  END COMPONENT;
+
+  COMPONENT cic_lfr_address_gen
+    PORT (
+      clk        : IN  STD_LOGIC;
+      rstn       : IN  STD_LOGIC;
+      run        : IN  STD_LOGIC;
+      addr_base  : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      addr_init  : IN STD_LOGIC;
+      addr_add_1 : IN STD_LOGIC;
+      addr       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
+  END COMPONENT;
+
+  
   -----------------------------------------------------------------------------
 END cic_pkg;
diff --git a/lib/lpp/dsp/cic/vhdlsyn.txt b/lib/lpp/dsp/cic/vhdlsyn.txt
--- a/lib/lpp/dsp/cic/vhdlsyn.txt
+++ b/lib/lpp/dsp/cic/vhdlsyn.txt
@@ -5,3 +5,5 @@ cic_downsampler.vhd
 cic_comb.vhd
 cic_lfr.vhd
 cic_lfr_control.vhd
+cic_lfr_add_sub.vhd
+cic_lfr_address_gen.vhd