HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r291:53b6541de175

(MINI_LFR) WaveFormPicker.0.0.0B : Update to correctly soft reset the Waveform_FIFO

pellion -

r291:53b6541de175 WaveFormPicker-0-0-0B (MINI-LFR) JC

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r291:53b6541de175

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designs/LFR_simu/tb_waveform.do +15 -15

             quietly WaveActivateNextPane {} 0
             add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot
             add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run
-            add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out
+            add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out
-            add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out
+            add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out
-            add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out
+            add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out
             add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid
             add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid
             add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid
-            add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd
+            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd
             add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address
             add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in
             add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out
             add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst
             add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin
             add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout
-            add wave -noupdate -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.address {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain
+            add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain
             add wave -noupdate -label data -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data
             add wave -noupdate -label grant /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout.grant
             add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout
-            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_0(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_0
+            add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_0
-            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_0(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_0
+            add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_0
-            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_1(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_1
+            add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_1
-            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_1(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_1
+            add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_1
-            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_2
+            add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_2
-            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2
+            add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/async_1mx16_1/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2
-            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_3
+            add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/async_1mx16_0/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_3
-            add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_3
+            add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_3
             TreeUpdate [SetDefaultTree]
-            WaveRestoreCursors {{Cursor 1} {12913873180 ps} 0}
+            WaveRestoreCursors {{Cursor 1} {340947831721 ps} 0}
             configure wave -namecolwidth 540
             configure wave -valuecolwidth 316
             configure wave -justifyvalue left
             configure wave -timeline 0
             configure wave -timelineunits ns
             update
-            WaveRestoreZoom {0 ps} {63240778126 ps}
+            WaveRestoreZoom {0 ps} {628873035 ns}

designs/MINI-LFR-WFRM-GPIO/MINI_LFR_top.vhd +209 -225

@@ -39,7 +39,7 LIBRARY lpp;
39	USE lpp.lpp_memory.ALL;	39	USE lpp.lpp_memory.ALL;
40	USE lpp.lpp_ad_conv.ALL;	40	USE lpp.lpp_ad_conv.ALL;
41	--USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib	41	--USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42	USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker	42	USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43	USE lpp.iir_filter.ALL;	43	USE lpp.iir_filter.ALL;
44	USE lpp.general_purpose.ALL;	44	USE lpp.general_purpose.ALL;
45	USE lpp.lpp_lfr_time_management.ALL;	45	USE lpp.lpp_lfr_time_management.ALL;
@@ -61,15 +61,15 ENTITY MINI_LFR_top IS
61	--UARTs	61	--UARTs
62	TXD1 : IN STD_LOGIC;	62	TXD1 : IN STD_LOGIC;
63	RXD1 : OUT STD_LOGIC;	63	RXD1 : OUT STD_LOGIC;
64	nCTS1 : OUT STD_LOGIC;	64	nCTS1 : OUT STD_LOGIC;
65	nRTS1 : IN STD_LOGIC;	65	nRTS1 : IN STD_LOGIC;
66		66
67	TXD2 : IN STD_LOGIC;	67	TXD2 : IN STD_LOGIC;
68	RXD2 : OUT STD_LOGIC;	68	RXD2 : OUT STD_LOGIC;
69	nCTS2 : OUT STD_LOGIC;	69	nCTS2 : OUT STD_LOGIC;
70	nDTR2 : IN STD_LOGIC;	70	nDTR2 : IN STD_LOGIC;
71	nRTS2 : IN STD_LOGIC;	71	nRTS2 : IN STD_LOGIC;
72	nDCD2 : OUT STD_LOGIC;	72	nDCD2 : OUT STD_LOGIC;
73		73
74	--EXT CONNECTOR	74	--EXT CONNECTOR
75	IO0 : INOUT STD_LOGIC;	75	IO0 : INOUT STD_LOGIC;
@@ -86,19 +86,19 ENTITY MINI_LFR_top IS
86	IO11 : INOUT STD_LOGIC;	86	IO11 : INOUT STD_LOGIC;
87		87
88	--SPACE WIRE	88	--SPACE WIRE
89	SPW_EN : OUT STD_LOGIC; -- 0 => off	89	SPW_EN : OUT STD_LOGIC; -- 0 => off
90	SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK	90	SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91	SPW_NOM_SIN : IN STD_LOGIC;	91	SPW_NOM_SIN : IN STD_LOGIC;
92	SPW_NOM_DOUT : OUT STD_LOGIC;	92	SPW_NOM_DOUT : OUT STD_LOGIC;
93	SPW_NOM_SOUT : OUT STD_LOGIC;	93	SPW_NOM_SOUT : OUT STD_LOGIC;
94	SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK	94	SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95	SPW_RED_SIN : IN STD_LOGIC;	95	SPW_RED_SIN : IN STD_LOGIC;
96	SPW_RED_DOUT : OUT STD_LOGIC;	96	SPW_RED_DOUT : OUT STD_LOGIC;
97	SPW_RED_SOUT : OUT STD_LOGIC;	97	SPW_RED_SOUT : OUT STD_LOGIC;
98	-- MINI LFR ADC INPUTS	98	-- MINI LFR ADC INPUTS
99	ADC_nCS : OUT STD_LOGIC;	99	ADC_nCS : OUT STD_LOGIC;
100	ADC_CLK : OUT STD_LOGIC;	100	ADC_CLK : OUT STD_LOGIC;
101	ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);	101	ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102		102
103	-- SRAM	103	-- SRAM
104	SRAM_nWE : OUT STD_LOGIC;	104	SRAM_nWE : OUT STD_LOGIC;
@@ -113,61 +113,61 END MINI_LFR_top;
113		113
114		114
115	ARCHITECTURE beh OF MINI_LFR_top IS	115	ARCHITECTURE beh OF MINI_LFR_top IS
116	SIGNAL clk_50_s : STD_LOGIC := '0';	116	SIGNAL clk_50_s : STD_LOGIC := '0';
117	SIGNAL clk_25 : STD_LOGIC := '0';	117	SIGNAL clk_25 : STD_LOGIC := '0';
118	-----------------------------------------------------------------------------	118	-----------------------------------------------------------------------------
119	SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);	119	SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120	SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);	120	SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121	--	121	--
122	SIGNAL errorn : STD_LOGIC;	122	SIGNAL errorn : STD_LOGIC;
123	-- UART AHB ---------------------------------------------------------------	123	-- UART AHB ---------------------------------------------------------------
124	SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data	124	SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125	SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data	125	SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126		126
127	-- UART APB ---------------------------------------------------------------	127	-- UART APB ---------------------------------------------------------------
128	SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data	128	SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129	SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data	129	SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130	--	130	--
131	SIGNAL I00_s : STD_LOGIC;	131	SIGNAL I00_s : STD_LOGIC;
132		132
133	-- CONSTANTS	133	-- CONSTANTS
134	~~constant~~ CFG_PADTECH : ~~integer~~ := inferred;	134	CONSTANT CFG_PADTECH : INTEGER := inferred;
135	--	135	--
136	CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f	136	CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137	CONSTANT NB_AHB_SLAVE : INTEGER := 1;	137	CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138	CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker	138	CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139		139
140	SIGNAL apbi_ext : apb_slv_in_type;	140	SIGNAL apbi_ext : apb_slv_in_type;
141	SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none);	141	SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142	SIGNAL ahbi_s_ext : ahb_slv_in_type;	142	SIGNAL ahbi_s_ext : ahb_slv_in_type;
143	SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none);	143	SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144	SIGNAL ahbi_m_ext : AHB_Mst_In_Type;	144	SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145	SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none);	145	SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146		146
147	-- Spacewire signals	147	-- Spacewire signals
148	SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);	148	SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149	SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);	149	SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150	SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);	150	SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151	SIGNAL spw_rxtxclk : ~~std_ulogic~~;	151	SIGNAL spw_rxtxclk : STD_ULOGIC;
152	SIGNAL spw_rxclkn : ~~std_ulogic~~;	152	SIGNAL spw_rxclkn : STD_ULOGIC;
153	SIGNAL spw_clk : ~~std_logic~~;	153	SIGNAL spw_clk : STD_LOGIC;
154	SIGNAL swni : grspw_in_type;	154	SIGNAL swni : grspw_in_type;
155	SIGNAL swno : grspw_out_type;	155	SIGNAL swno : grspw_out_type;
156	-- SIGNAL clkmn : STD_ULOGIC;	156	-- SIGNAL clkmn : STD_ULOGIC;
157	-- SIGNAL txclk : STD_ULOGIC;	157	-- SIGNAL txclk : STD_ULOGIC;
158		158
159	--GPIO	159	--GPIO
160	SIGNAL gpioi : gpio_in_type;	160	SIGNAL gpioi : gpio_in_type;
161	SIGNAL gpioo : gpio_out_type;	161	SIGNAL gpioo : gpio_out_type;
162		162
163	-- AD Converter ADS7886	163	-- AD Converter ADS7886
164	SIGNAL sample : Samples14v(7 DOWNTO 0);	164	SIGNAL sample : Samples14v(7 DOWNTO 0);
165	SIGNAL sample_val : STD_LOGIC;	165	SIGNAL sample_val : STD_LOGIC;
166	SIGNAL ADC_nCS_sig : STD_LOGIC;	166	SIGNAL ADC_nCS_sig : STD_LOGIC;
167	SIGNAL ADC_CLK_sig : STD_LOGIC;	167	SIGNAL ADC_CLK_sig : STD_LOGIC;
168	SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);	168	SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
169		169
170	SIGNAL bias_fail_sw_sig : STD_LOGIC;	170	SIGNAL bias_fail_sw_sig : STD_LOGIC;
171		171
172	BEGIN -- beh	172	BEGIN -- beh
173		173
@@ -181,7 +181,7 BEGIN -- beh
181	clk_50_s <= NOT clk_50_s;	181	clk_50_s <= NOT clk_50_s;
182	END IF;	182	END IF;
183	END PROCESS;	183	END PROCESS;
184		184
185	PROCESS(clk_50_s)	185	PROCESS(clk_50_s)
186	BEGIN	186	BEGIN
187	IF clk_50_s'EVENT AND clk_50_s = '1' THEN	187	IF clk_50_s'EVENT AND clk_50_s = '1' THEN
@@ -190,7 +190,7 BEGIN -- beh
190	END PROCESS;	190	END PROCESS;
191		191
192	-----------------------------------------------------------------------------	192	-----------------------------------------------------------------------------
193		193
194	PROCESS (clk_25, reset)	194	PROCESS (clk_25, reset)
195	BEGIN -- PROCESS	195	BEGIN -- PROCESS
196	IF reset = '0' THEN -- asynchronous reset (active low)	196	IF reset = '0' THEN -- asynchronous reset (active low)
@@ -208,7 +208,7 BEGIN -- beh
208	--IO9 <= '0';	208	--IO9 <= '0';
209	--IO10 <= '0';	209	--IO10 <= '0';
210	--IO11 <= '0';	210	--IO11 <= '0';
211	ELSIF clk_25'~~event~~ AND clk_25 = '1' THEN -- rising clock edge	211	ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
212	LED0 <= '0';	212	LED0 <= '0';
213	LED1 <= '1';	213	LED1 <= '1';
214	LED2 <= BP0;	214	LED2 <= BP0;
@@ -222,30 +222,30 BEGIN -- beh
222	--IO8 <= ADC_SDO(5);	222	--IO8 <= ADC_SDO(5);
223	--IO9 <= ADC_SDO(6);	223	--IO9 <= ADC_SDO(6);
224	--IO10 <= ADC_SDO(7);	224	--IO10 <= ADC_SDO(7);
225	IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;	225	IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226	END IF;	226	END IF;
227	END PROCESS;	227	END PROCESS;
228		228
229	PROCESS (clk_49, reset)	229	PROCESS (clk_49, reset)
230	BEGIN -- PROCESS	230	BEGIN -- PROCESS
231	IF reset = '0' THEN -- asynchronous reset (active low)	231	IF reset = '0' THEN -- asynchronous reset (active low)
232	I00_s <= '0';	232	I00_s <= '0';
233	ELSIF clk_49'~~event~~ AND clk_49 = '1' THEN -- rising clock edge	233	ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
234	I00_s <= NOT I00_s;	234	I00_s <= NOT I00_s;
235	END IF;	235	END IF;
236	END PROCESS;	236	END PROCESS;
237	-- IO0 <= I00_s;	237	-- IO0 <= I00_s;
238		238
239	--UARTs	239	--UARTs
240	nCTS1 <= '1';	240	nCTS1 <= '1';
241	nCTS2 <= '1';	241	nCTS2 <= '1';
242	nDCD2 <= '1';	242	nDCD2 <= '1';
243		243
244	--EXT CONNECTOR	244	--EXT CONNECTOR
245		245
246	--SPACE WIRE	246	--SPACE WIRE
247		247
248	leon3_soc_1: leon3_soc	248	leon3_soc_1 : leon3_soc
249	GENERIC MAP (	249	GENERIC MAP (
250	fabtech => apa3e,	250	fabtech => apa3e,
251	memtech => apa3e,	251	memtech => apa3e,
@@ -267,34 +267,34 BEGIN -- beh
267	NB_AHB_SLAVE => NB_AHB_SLAVE,	267	NB_AHB_SLAVE => NB_AHB_SLAVE,
268	NB_APB_SLAVE => NB_APB_SLAVE)	268	NB_APB_SLAVE => NB_APB_SLAVE)
269	PORT MAP (	269	PORT MAP (
270	clk => clk_25,	270	clk => clk_25,
271	reset => reset,	271	reset => reset,
272	errorn => errorn,	272	errorn => errorn,
273	ahbrxd => TXD1,	273	ahbrxd => TXD1,
274	ahbtxd => RXD1,	274	ahbtxd => RXD1,
275	urxd1 => TXD2,	275	urxd1 => TXD2,
276	utxd1 => RXD2,	276	utxd1 => RXD2,
277	address => SRAM_A,	277	address => SRAM_A,
278	data => SRAM_DQ,	278	data => SRAM_DQ,
279	nSRAM_BE0 => SRAM_nBE(0),	279	nSRAM_BE0 => SRAM_nBE(0),
280	nSRAM_BE1 => SRAM_nBE(1),	280	nSRAM_BE1 => SRAM_nBE(1),
281	nSRAM_BE2 => SRAM_nBE(2),	281	nSRAM_BE2 => SRAM_nBE(2),
282	nSRAM_BE3 => SRAM_nBE(3),	282	nSRAM_BE3 => SRAM_nBE(3),
283	nSRAM_WE => SRAM_nWE,	283	nSRAM_WE => SRAM_nWE,
284	nSRAM_CE => SRAM_CE,	284	nSRAM_CE => SRAM_CE,
285	nSRAM_OE => SRAM_nOE,	285	nSRAM_OE => SRAM_nOE,
286		286
287	apbi_ext => apbi_ext,	287	apbi_ext => apbi_ext,
288	apbo_ext => apbo_ext,	288	apbo_ext => apbo_ext,
289	ahbi_s_ext => ahbi_s_ext,	289	ahbi_s_ext => ahbi_s_ext,
290	ahbo_s_ext => ahbo_s_ext,	290	ahbo_s_ext => ahbo_s_ext,
291	ahbi_m_ext => ahbi_m_ext,	291	ahbi_m_ext => ahbi_m_ext,
292	ahbo_m_ext => ahbo_m_ext);	292	ahbo_m_ext => ahbo_m_ext);
293		293
294	-------------------------------------------------------------------------------	294	-------------------------------------------------------------------------------
295	-- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------	295	-- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
296	-------------------------------------------------------------------------------	296	-------------------------------------------------------------------------------
297	apb_lfr_time_management_1: apb_lfr_time_management	297	apb_lfr_time_management_1 : apb_lfr_time_management
298	GENERIC MAP (	298	GENERIC MAP (
299	pindex => 6,	299	pindex => 6,
300	paddr => 6,	300	paddr => 6,
@@ -309,93 +309,93 BEGIN -- beh
309	apbo => apbo_ext(6),	309	apbo => apbo_ext(6),
310	coarse_time => coarse_time,	310	coarse_time => coarse_time,
311	fine_time => fine_time);	311	fine_time => fine_time);
312		312
313	-----------------------------------------------------------------------	313	-----------------------------------------------------------------------
314	--- SpaceWire --------------------------------------------------------	314	--- SpaceWire --------------------------------------------------------
315	-----------------------------------------------------------------------	315	-----------------------------------------------------------------------
316		316
317	SPW_EN <= '1';	317	SPW_EN <= '1';
318		318
319	spw_clk <= clk_50_s;	319	spw_clk <= clk_50_s;
320	spw_rxtxclk <= spw_clk;	320	spw_rxtxclk <= spw_clk;
321	spw_rxclkn <= ~~not~~ spw_rxtxclk;	321	spw_rxclkn <= NOT spw_rxtxclk;
322		322
323	-- PADS for SPW1	323	-- PADS for SPW1
324	spw1_rxd_pad : inpad ~~generic~~ ~~map~~ (tech => inferred)	324	spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
325	~~port~~ ~~map~~ (SPW_NOM_DIN, dtmp(0));	325	PORT MAP (SPW_NOM_DIN, dtmp(0));
326	spw1_rxs_pad : inpad ~~generic~~ ~~map~~ (tech => inferred)	326	spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
327	~~port~~ ~~map~~ (SPW_NOM_SIN, stmp(0));	327	PORT MAP (SPW_NOM_SIN, stmp(0));
328	spw1_txd_pad : outpad ~~generic~~ ~~map~~ (tech => inferred)	328	spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
329	~~port~~ ~~map~~ (SPW_NOM_DOUT, swno.d(0));	329	PORT MAP (SPW_NOM_DOUT, swno.d(0));
330	spw1_txs_pad : outpad ~~generic~~ ~~map~~ (tech => inferred)	330	spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
331	~~port~~ ~~map~~ (SPW_NOM_SOUT, swno.s(0));	331	PORT MAP (SPW_NOM_SOUT, swno.s(0));
332	-- PADS FOR SPW2	332	-- PADS FOR SPW2
333	spw2_rxd_pad : inpad ~~generic~~ ~~map~~ (tech => inferred) -- bad naming of the MINI-LFR /!\	333	spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
334	~~port~~ ~~map~~ (SPW_RED_SIN, dtmp(1));	334	PORT MAP (SPW_RED_SIN, dtmp(1));
335	spw2_rxs_pad : inpad ~~generic~~ ~~map~~ (tech => inferred) -- bad naming of the MINI-LFR /!\	335	spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
336	~~port~~ ~~map~~ (SPW_RED_DIN, stmp(1));	336	PORT MAP (SPW_RED_DIN, stmp(1));
337	spw2_txd_pad : outpad ~~generic~~ ~~map~~ (tech => inferred)	337	spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
338	~~port~~ ~~map~~ (SPW_RED_DOUT, swno.d(1));	338	PORT MAP (SPW_RED_DOUT, swno.d(1));
339	spw2_txs_pad : outpad ~~generic~~ ~~map~~ (tech => inferred)	339	spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
340	~~port~~ ~~map~~ (SPW_RED_SOUT, swno.s(1));	340	PORT MAP (SPW_RED_SOUT, swno.s(1));
341		341
342	-- GRSPW PHY	342	-- GRSPW PHY
343	--spw1_input: if CFG_SPW_GRSPW = 1 generate	343	--spw1_input: if CFG_SPW_GRSPW = 1 generate
344	spw_inputloop: for j in 0 to 1 generate	344	spw_inputloop : FOR j IN 0 TO 1 GENERATE
345	spw_phy0 : grspw_phy	345	spw_phy0 : grspw_phy
346	generic map(	346	GENERIC MAP(
347	tech => apa3e,	347	tech => apa3e,
348	rxclkbuftype => 1,	348	rxclkbuftype => 1,
349	scantest => 0)	349	scantest => 0)
350	port map(	350	PORT MAP(
351	rxrst => swno.rxrst,	351	rxrst => swno.rxrst,
352	di => dtmp(j),	352	di => dtmp(j),
353	si => stmp(j),	353	si => stmp(j),
354	rxclko => spw_rxclk(j),	354	rxclko => spw_rxclk(j),
355	do => swni.d(j),	355	do => swni.d(j),
356	ndo => swni.nd(j5+4 ~~downto~~ j5),	356	ndo => swni.nd(j5+4 DOWNTO j5),
357	dconnect => swni.dconnect(j2+1 ~~downto~~ j2));	357	dconnect => swni.dconnect(j2+1 DOWNTO j2));
358	end generate spw_inputloop;	358	END GENERATE spw_inputloop;
359		359
360	-- SPW core	360	-- SPW core
361	sw0 : grspwm generic map(	361	sw0 : grspwm GENERIC MAP(
362	tech => apa3e,	362	tech => apa3e,
363	hindex => 1,	363	hindex => 1,
364	pindex => 5,	364	pindex => 5,
365	~~paddr~~ => 5,	365	paddr => 5,
366	pirq => 11,	366	pirq => 11,
367	sysfreq => 25000, -- CPU_FREQ	367	sysfreq => 25000, -- CPU_FREQ
368	rmap => 1,	368	rmap => 1,
369	rmapcrc => 1,	369	rmapcrc => 1,
370	fifosize1 => 16,	370	fifosize1 => 16,
371	fifosize2 => 16,	371	fifosize2 => 16,
372	rxclkbuftype => 1,	372	rxclkbuftype => 1,
373	rxunaligned => 0,	373	rxunaligned => 0,
374	rmapbufs => 4,	374	rmapbufs => 4,
375	ft => 0,	375	ft => 0,
376	netlist => 0,	376	netlist => 0,
377	ports => 2,	377	ports => 2,
378	--dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1	378	--dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
379	memtech => apa3e,	379	memtech => apa3e,
380	destkey => 2,	380	destkey => 2,
381	spwcore => 1	381	spwcore => 1
382	--input_type => CFG_SPW_INPUT, -- not used byt the spw core 1	382	--input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
383	--output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1	383	--output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
384	--rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1	384	--rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
385	)	385	)
386	~~port~~ ~~map~~(reset, clk_25, spw_rxclk(0),	386	PORT MAP(reset, clk_25, spw_rxclk(0),
387	spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,	387	spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
388	ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),	388	ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
389	swni, swno);	389	swni, swno);
390		390
391	swni.tickin <= '0';	391	swni.tickin <= '0';
392	swni.rmapen <= '1';	392	swni.rmapen <= '1';
393	swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz	393	swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
394	swni.tickinraw <= '0';	394	swni.tickinraw <= '0';
395	swni.timein <= (~~others~~ => '0');	395	swni.timein <= (OTHERS => '0');
396	swni.dcrstval <= (~~others~~ => '0');	396	swni.dcrstval <= (OTHERS => '0');
397	swni.timerrstval <= (~~others~~ => '0');	397	swni.timerrstval <= (OTHERS => '0');
398		398
399	-------------------------------------------------------------------------------	399	-------------------------------------------------------------------------------
400	-- LFR ------------------------------------------------------------------------	400	-- LFR ------------------------------------------------------------------------
401	-------------------------------------------------------------------------------	401	-------------------------------------------------------------------------------
@@ -428,7 +428,7 BEGIN -- beh
428	-- fine_time => fine_time,	428	-- fine_time => fine_time,
429	-- data_shaping_BW => bias_fail_sw_sig);	429	-- data_shaping_BW => bias_fail_sw_sig);
430		430
431	waveform_picker0 : top_wf_picker	431	waveform_picker0 : top_wf_picker
432	GENERIC MAP(	432	GENERIC MAP(
433	hindex => 2,	433	hindex => 2,
434	pindex => 15,	434	pindex => 15,
@@ -438,7 +438,7 BEGIN -- beh
438	tech => apa3e,	438	tech => apa3e,
439	nb_burst_available_size => 12, -- size of the register holding the nb of burst	439	nb_burst_available_size => 12, -- size of the register holding the nb of burst
440	nb_snapshot_param_size => 12, -- size of the register holding the snapshots size	440	nb_snapshot_param_size => 12, -- size of the register holding the snapshots size
441	delta_snapshot_size => 16, -- snapshots period	441	delta_snapshot_size => 16, -- snapshots period
442	delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts	442	delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts
443	delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot	443	delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot
444	ENABLE_FILTER => '1'	444	ENABLE_FILTER => '1'
@@ -447,9 +447,9 BEGIN -- beh
447	cnv_clk => clk_25,	447	cnv_clk => clk_25,
448	cnv_rstn => reset,	448	cnv_rstn => reset,
449	-- SAMPLES	449	-- SAMPLES
450	sample_B => sample(2 DOWNTO 0),	450	sample_B => sample(2 DOWNTO 0),
451	sample_E => sample(7 DOWNTO 3),	451	sample_E => sample(7 DOWNTO 3),
452	sample_val => sample_val,	452	sample_val => sample_val,
453	-- AMBA AHB system signals	453	-- AMBA AHB system signals
454	HCLK => clk_25,	454	HCLK => clk_25,
455	HRESETn => reset,	455	HRESETn => reset,
@@ -462,68 +462,52 BEGIN -- beh
462	--	462	--
463	coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time	463	coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time
464	--	464	--
465	data_shaping_BW => bias_fail_sw_sig	465	data_shaping_BW => bias_fail_sw_sig
466	);	466	);
467		467
468	top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2	468	top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
469	GENERIC MAP(	469	GENERIC MAP(
470	~~ChannelCount~~ => 8,	470	ChannelCount => 8,
471	SampleNbBits => 14,	471	SampleNbBits => 14,
472	ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63	472	ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63
473	ncycle_cnv => 500) -- 49 152 000 / 98304	473	ncycle_cnv => 500) -- 49 152 000 / 98304
474	PORT MAP (	474	PORT MAP (
475	-- CONV	475	-- CONV
476	cnv_clk => clk_49,	476	cnv_clk => clk_49,
477	cnv_rstn => reset,	477	cnv_rstn => reset,
478	~~cnv~~ => ADC_nCS_sig,	478	cnv => ADC_nCS_sig,
479	-- DATA	479	-- DATA
480	~~clk~~ => clk_25,	480	clk => clk_25,
481	rstn => reset,	481	rstn => reset,
482	sck => ADC_CLK_sig,	482	sck => ADC_CLK_sig,
483	sdo => ADC_SDO_sig,	483	sdo => ADC_SDO_sig,
484	-- SAMPLE	484	-- SAMPLE
485	sample => sample,	485	sample => sample,
486	sample_val => sample_val);	486	sample_val => sample_val);
487
488	IO10 <= ADC_SDO_sig(5);
489	IO9 <= ADC_SDO_sig(4);
490	IO8 <= ADC_SDO_sig(3);
491		487
492	~~ADC_nCS~~ <= ADC_nCS_sig;	488	IO10 <= ADC_SDO_sig(5);
493	~~ADC_CLK~~ <= ADC_~~CLK_sig~~;	489	IO9 <= ADC_SDO_sig(4);
494	~~ADC_SDO_sig~~ <= ADC_SDO;	490	IO8 <= ADC_SDO_sig(3);
495		491
		492	ADC_nCS <= ADC_nCS_sig;
		493	ADC_CLK <= ADC_CLK_sig;
		494	ADC_SDO_sig <= ADC_SDO;
		495
496	----------------------------------------------------------------------	496	----------------------------------------------------------------------
497	--- GPIO -----------------------------------------------------------	497	--- GPIO -----------------------------------------------------------
498	----------------------------------------------------------------------	498	----------------------------------------------------------------------
499		499
500	grgpio0: grgpio	500	grgpio0 : grgpio
501	~~generic~~ ~~map~~( pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)	501	GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
502	~~port~~ ~~map~~( reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);	502	PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
503		503
504	pio_pad_0 : iopad	504	pio_pad_0 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
505	generic map (tech => CFG_PADTECH)	505	pio_pad_1 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
506	port map (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));	506	pio_pad_2 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
507	pio_pad_1 : iopad	507	pio_pad_3 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
508	generic map (tech => CFG_PADTECH)	508	pio_pad_4 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
509	port map (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));	509	pio_pad_5 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
510	pio_pad_2 : iopad	510	pio_pad_6 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
511	generic map (tech => CFG_PADTECH)	511	pio_pad_7 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
512	port map (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
513	pio_pad_3 : iopad
514	generic map (tech => CFG_PADTECH)
515	port map (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
516	pio_pad_4 : iopad
517	generic map (tech => CFG_PADTECH)
518	port map (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
519	pio_pad_5 : iopad
520	generic map (tech => CFG_PADTECH)
521	port map (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
522	pio_pad_6 : iopad
523	generic map (tech => CFG_PADTECH)
524	port map (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
525	pio_pad_7 : iopad
526	generic map (tech => CFG_PADTECH)
527	port map (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
528		512
529	END beh; No newline at end of file	513	END beh;

designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd +1 -1

                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"0000000A")
+                  top_lfr_version        => X"0000000B")
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => reset,

lib/lpp/lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd +59 -62

@@ -8,21 +8,21 USE lpp.general_purpose.SYNC_FF;
8		8
9	ENTITY top_ad_conv_ADS7886_v2 IS	9	ENTITY top_ad_conv_ADS7886_v2 IS
10	GENERIC(	10	GENERIC(
11	ChannelCount : INTEGER := 8;	11	ChannelCount : INTEGER := 8;
12	SampleNbBits : INTEGER := 14;	12	SampleNbBits : INTEGER := 14;
13	ncycle_cnv_high : INTEGER := 40; -- at least 32 cycles	13	ncycle_cnv_high : INTEGER := 40; -- at least 32 cycles
14	ncycle_cnv : INTEGER := 500);	14	ncycle_cnv : INTEGER := 500);
15	PORT (	15	PORT (
16	-- CONV	16	-- CONV
17	cnv_clk : IN STD_LOGIC;	17	cnv_clk : IN STD_LOGIC;
18	cnv_rstn : IN STD_LOGIC;	18	cnv_rstn : IN STD_LOGIC;
19	cnv : OUT STD_LOGIC;	19	cnv : OUT STD_LOGIC;
20	-- DATA	20	-- DATA
21	clk : IN STD_LOGIC;	21	clk : IN STD_LOGIC;
22	rstn : IN STD_LOGIC;	22	rstn : IN STD_LOGIC;
23	sck : OUT STD_LOGIC;	23	sck : OUT STD_LOGIC;
24	sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);	24	sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
25	-- SAMPLE	25	-- SAMPLE
26	sample : OUT Samples14v(ChannelCount-1 DOWNTO 0);	26	sample : OUT Samples14v(ChannelCount-1 DOWNTO 0);
27	sample_val : OUT STD_LOGIC	27	sample_val : OUT STD_LOGIC
28	);	28	);
@@ -33,10 +33,10 ARCHITECTURE ar_top_ad_conv_ADS7886_v2 O
33	SIGNAL cnv_cycle_counter : INTEGER;	33	SIGNAL cnv_cycle_counter : INTEGER;
34	SIGNAL cnv_s : STD_LOGIC;	34	SIGNAL cnv_s : STD_LOGIC;
35	SIGNAL cnv_sync : STD_LOGIC;	35	SIGNAL cnv_sync : STD_LOGIC;
36	SIGNAL cnv_sync_not : STD_LOGIC;	36	SIGNAL cnv_sync_not : STD_LOGIC;
37		37
38	SIGNAL sample_adc : Samples(ChannelCount-1 DOWNTO 0);	38	SIGNAL sample_adc : Samples(ChannelCount-1 DOWNTO 0);
39	SIGNAL sample_val_adc : STD_LOGIC;	39	SIGNAL sample_val_adc : STD_LOGIC;
40		40
41	BEGIN	41	BEGIN
42		42
@@ -69,68 +69,65 BEGIN
69	END IF;	69	END IF;
70	END PROCESS;	70	END PROCESS;
71		71
72	cnv <= ~~not~~(cnv_s);	72	cnv <= NOT(cnv_s);
73		73
74	-----------------------------------------------------------------------------	74	-----------------------------------------------------------------------------
75	-- SYNC CNV	75	-- SYNC CNV
76	-----------------------------------------------------------------------------	76	-----------------------------------------------------------------------------
77		77
78	SYNC_FF_cnv : SYNC_FF	78	SYNC_FF_cnv : SYNC_FF
79	GENERIC MAP (	79	GENERIC MAP (
80	NB_FF_OF_SYNC => 2)	80	NB_FF_OF_SYNC => 2)
81	PORT MAP (	81	PORT MAP (
82	clk => clk,	82	clk => clk,
83	rstn => rstn,	83	rstn => rstn,
84	A => cnv_s, -- the data fetching begins immediately	84	A => cnv_s, -- the data fetching begins immediately
85	A_sync => cnv_sync);	85	A_sync => cnv_sync);
86		86
87	-----------------------------------------------------------------------------	87	-----------------------------------------------------------------------------
88		88
89	cnv_sync_not <= ~~not~~(cnv_sync);	89	cnv_sync_not <= NOT(cnv_sync);
90		90
91	ADS7886_drvr_v2_1 : ADS7886_drvr_v2	91	ADS7886_drvr_v2_1 : ADS7886_drvr_v2
92	GENERIC MAP(	92	GENERIC MAP(
93	ChannelCount => 8,	93	ChannelCount => 8,
94	NbBitsSamples => 16)	94	NbBitsSamples => 16)
95	PORT MAP(	95	PORT MAP(
96	-- CONV --	96	-- CONV --
97	cnv_clk => cnv_sync_not,	97	cnv_clk => cnv_sync_not,
98	cnv_rstn => rstn,	98	cnv_rstn => rstn,
99	-- DATA --	99	-- DATA --
100	clk => clk, -- master clock, 25 MHz	100	clk => clk, -- master clock, 25 MHz
101	rstn => rstn,	101	rstn => rstn,
102	sck => sck,	102	sck => sck,
103	sdo => sdo,	103	sdo => sdo,
104	-- SAMPLE --	104	-- SAMPLE --
105	sample => sample_adc,	105	sample => sample_adc,
106	sample_val => sample_val_adc);	106	sample_val => sample_val_adc);
107		107
108	PROCESS (clk, rstn)	108	PROCESS (clk, rstn)
109	BEGIN -- PROCESS	109	BEGIN -- PROCESS
110	IF rstn = '0' THEN -- asynchronous reset (active low)	110	IF rstn = '0' THEN -- asynchronous reset (active low)
111	FOR k IN 0 TO ChannelCount-1 LOOP	111	FOR k IN 0 TO ChannelCount-1 LOOP
112	sample(k)(13 ~~downto~~ 0) <= (OTHERS => '0');	112	sample(k)(13 DOWNTO 0) <= (OTHERS => '0');
113	END LOOP;	113	END LOOP;
114	sample_val <= '0';	114	sample_val <= '0';
115	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge	115	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
116	IF sample_val_adc ='1' THEN	116	IF sample_val_adc = '1' THEN
117	FOR k IN 0 TO ChannelCount-1 LOOP	117	FOR k IN 0 TO ChannelCount-1 LOOP
118	IF ( ~~unsigned~~(sample_adc(k)(11 ~~downto~~ 0)) >= 2048) THEN	118	IF (UNSIGNED(sample_adc(k)(11 DOWNTO 0)) >= 2048) THEN
119	sample(k)(13 ~~downto~~ 0) <= "00" &	119	sample(k)(13 DOWNTO 0) <= "00" &
120	~~std_logic_vector~~( ~~unsigned~~(sample_adc(k)(11 ~~downto~~ 0)) - 2048 );	120	STD_LOGIC_VECTOR(UNSIGNED(sample_adc(k)(11 DOWNTO 0)) - 2048);
121	ELSE	121	ELSE
122	sample(k)(13 ~~downto~~ 0) <= "11" &	122	sample(k)(13 DOWNTO 0) <= "11" &
123	~~std_logic_vector~~( ~~unsigned~~(sample_adc(k)(11 ~~downto~~ 0)) - 2048 );	123	STD_LOGIC_VECTOR(UNSIGNED(sample_adc(k)(11 DOWNTO 0)) - 2048);
124	END IF;	124	END IF;
125	END LOOP;	125	END LOOP;
126	-- FOR k IN 0 TO ChannelCount-1 LOOP	126	sample_val <= sample_val_adc;
127	-- sample(k) <= sample_adc(k)(13 downto 0);	127	ELSE
128	-- END LOOP;	128	sample_val <= '0';
129	sample_val <= sample_val_adc;	129	END IF;
130	ELSE
131	sample_val <= '0';
132	END IF;
133	END IF;	130	END IF;
134	END PROCESS;	131	END PROCESS;
135		132
136	END ar_top_ad_conv_ADS7886_v2; No newline at end of file	133	END ar_top_ad_conv_ADS7886_v2;

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +32 -26

                 debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
                 debug_f3_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
                 --debug DMA IN
                 debug_f0_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 debug_f0_data_dma_in_valid : OUT STD_LOGIC;
                   dma_send        <= '0';
                   dma_valid_burst <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
+                  IF run = '1' THEN
             --      IF dma_sel = "0000" OR dma_send = '1' THEN
-                  IF dma_sel = "0000" OR dma_done = '1' THEN
+                    IF dma_sel = "0000" OR dma_done = '1' THEN
-                    dma_sel <= dma_rr_grant;
+                      dma_sel <= dma_rr_grant;
-                    IF dma_rr_grant(0) = '1' THEN
+                      IF dma_rr_grant(0) = '1' THEN
-                      dma_send        <= '1';
+                        dma_send        <= '1';
-                      dma_valid_burst <= data_f0_data_out_valid_burst;
+                        dma_valid_burst <= data_f0_data_out_valid_burst;
-                      dma_sel_valid   <= data_f0_data_out_valid;
+                        dma_sel_valid   <= data_f0_data_out_valid;
-                    ELSIF dma_rr_grant(1) = '1' THEN
+                      ELSIF dma_rr_grant(1) = '1' THEN
-                      dma_send        <= '1';
+                        dma_send        <= '1';
-                      dma_valid_burst <= data_f1_data_out_valid_burst;
+                        dma_valid_burst <= data_f1_data_out_valid_burst;
-                      dma_sel_valid   <= data_f1_data_out_valid;
+                        dma_sel_valid   <= data_f1_data_out_valid;
-                    ELSIF dma_rr_grant(2) = '1' THEN
+                      ELSIF dma_rr_grant(2) = '1' THEN
-                      dma_send        <= '1';
+                        dma_send        <= '1';
-                      dma_valid_burst <= data_f2_data_out_valid_burst;
+                        dma_valid_burst <= data_f2_data_out_valid_burst;
-                      dma_sel_valid   <= data_f2_data_out_valid;
+                        dma_sel_valid   <= data_f2_data_out_valid;
-                    ELSIF dma_rr_grant(3) = '1' THEN
+                      ELSIF dma_rr_grant(3) = '1' THEN
-                      dma_send        <= '1';
+                        dma_send        <= '1';
-                      dma_valid_burst <= data_f3_data_out_valid_burst;
+                        dma_valid_burst <= data_f3_data_out_valid_burst;
-                      dma_sel_valid   <= data_f3_data_out_valid;
+                        dma_sel_valid   <= data_f3_data_out_valid;
+                      END IF;
+                    ELSE
+                      dma_sel  <= dma_sel;
+                      dma_send <= '0';
                     END IF;
                   ELSE
-                    dma_sel  <= dma_sel;
+                    dma_sel         <= (OTHERS => '0');
-                    dma_send <= '0';
+                    dma_send        <= '0';
+                    dma_valid_burst <= '0';
                   END IF;
                 END IF;
               END PROCESS;
               dma_data_2 <= dma_data;
               -----------------------------------------------------------------------------
               debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
               debug_f3_data_dma_in       <= dma_data;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- DMA
               -----------------------------------------------------------------------------
                   AHB_Master_In  => ahbi,
                   AHB_Master_Out => ahbo,
                   send        => dma_send,
                   valid_burst => dma_valid_burst,
                   done        => dma_done,
                   ren         => dma_ren,
                   address     => dma_address,
                   data        => dma_data_2);
               -----------------------------------------------------------------------------

lib/lpp/lpp_waveform/lpp_waveform_fifo_headreg.vhd +34 -16

@@ -78,7 +78,11 BEGIN
78	IF rstn = '0' THEN	78	IF rstn = '0' THEN
79	s_ren_reg <= (OTHERS => '1');	79	s_ren_reg <= (OTHERS => '1');
80	ELSIF clk'EVENT AND clk = '1' THEN	80	ELSIF clk'EVENT AND clk = '1' THEN
81	s_ren_reg <= s_ren;	81	IF run = '1' THEN
		82	s_ren_reg <= s_ren;
		83	ELSE
		84	s_ren_reg <= (OTHERS => '1');
		85	END IF;
82	END IF;	86	END IF;
83	END PROCESS;	87	END PROCESS;
84		88
@@ -118,10 +122,17 BEGIN
118	s_rdata_2 <= (OTHERS => '0');	122	s_rdata_2 <= (OTHERS => '0');
119	s_rdata_3 <= (OTHERS => '0');	123	s_rdata_3 <= (OTHERS => '0');
120	ELSIF clk'EVENT AND clk = '1' THEN	124	ELSIF clk'EVENT AND clk = '1' THEN
121	IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF;	125	IF run = '1' THEN
122	IF s_ren_reg(1) = '0' THEN s_rdata_1 <= i_rdata; END IF;	126	IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF;
123	IF s_ren_reg(2) = '0' THEN s_rdata_2 <= i_rdata; END IF;	127	IF s_ren_reg(1) = '0' THEN s_rdata_1 <= i_rdata; END IF;
124	IF s_ren_reg(3) = '0' THEN s_rdata_3 <= i_rdata; END IF;	128	IF s_ren_reg(2) = '0' THEN s_rdata_2 <= i_rdata; END IF;
		129	IF s_ren_reg(3) = '0' THEN s_rdata_3 <= i_rdata; END IF;
		130	ELSE
		131	s_rdata_0 <= (OTHERS => '0');
		132	s_rdata_1 <= (OTHERS => '0');
		133	s_rdata_2 <= (OTHERS => '0');
		134	s_rdata_3 <= (OTHERS => '0');
		135	END IF;
125	END IF;	136	END IF;
126	END PROCESS;	137	END PROCESS;
127		138
@@ -132,9 +143,13 BEGIN
132	reg_full(I) <= '0';	143	reg_full(I) <= '0';
133	ELSIF clk'EVENT AND clk = '1' THEN	144	ELSIF clk'EVENT AND clk = '1' THEN
134	-- IF s_ren_reg(I) = '0' THEN	145	-- IF s_ren_reg(I) = '0' THEN
135	IF ~~s_ren~~(I) = '0' THEN	146	IF run = '1' THEN
136	~~reg_full~~(I) <= '1';	147	IF s_ren(I) = '0' THEN
137	ELSIF o_data_ren(I) = '0' THEN	148	reg_full(I) <= '1';
		149	ELSIF o_data_ren(I) = '0' THEN
		150	reg_full(I) <= '0';
		151	END IF;
		152	ELSE
138	reg_full(I) <= '0';	153	reg_full(I) <= '0';
139	END IF;	154	END IF;
140	END IF;	155	END IF;
@@ -157,15 +172,18 BEGIN
157	IF rstn = '0' THEN -- asynchronous reset (active low)	172	IF rstn = '0' THEN -- asynchronous reset (active low)
158	s_empty_almost(I) <= '1';	173	s_empty_almost(I) <= '1';
159	ELSIF clk'event AND clk = '1' THEN -- rising clock edge	174	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
160	-- IF ~~s_ren_reg(I) = '0~~' THEN	175	IF run = '1' THEN
161	IF s_ren(I) = '0' THEN	176	IF s_ren(I) = '0' THEN
162	s_empty_almost(I) <= i_empty_almost(I);	177	s_empty_almost(I) <= i_empty_almost(I);
163	ELSIF o_data_ren(I) = '0' THEN	178	ELSIF o_data_ren(I) = '0' THEN
		179	s_empty_almost(I) <= '1';
		180	ELSE
		181	IF i_empty_almost(I) = '0' THEN
		182	s_empty_almost(I) <= '0';
		183	END IF;
		184	END IF;
		185	ELSE
164	s_empty_almost(I) <= '1';	186	s_empty_almost(I) <= '1';
165	ELSE
166	IF i_empty_almost(I) = '0' THEN
167	s_empty_almost(I) <= '0';
168	END IF;
169	END IF;	187	END IF;
170	END IF;	188	END IF;
171	END PROCESS;	189	END PROCESS;

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