| @@ -1,54 +1,54 | |||||
| 1 | onerror {resume} |
|
1 | onerror {resume} | |
| 2 | quietly WaveActivateNextPane {} 0 |
|
2 | quietly WaveActivateNextPane {} 0 | |
| 3 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot |
|
3 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot | |
| 4 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run |
|
4 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run | |
| 5 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out |
|
5 | add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out | |
| 6 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out |
|
6 | add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out | |
| 7 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out |
|
7 | add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out | |
| 8 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid |
|
8 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid | |
| 9 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid |
|
9 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid | |
| 10 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid |
|
10 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid | |
| 11 |
add wave -noupdate -radix hexadecimal |
|
11 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd | |
| 12 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address |
|
12 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address | |
| 13 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in |
|
13 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in | |
| 14 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out |
|
14 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out | |
| 15 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/data |
|
15 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/data | |
| 16 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay |
|
16 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay | |
| 17 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/done |
|
17 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/done | |
| 18 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hindex |
|
18 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hindex | |
| 19 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hresetn |
|
19 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hresetn | |
| 20 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ren |
|
20 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ren | |
| 21 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/run |
|
21 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/run | |
| 22 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/send |
|
22 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/send | |
| 23 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst |
|
23 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst | |
| 24 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin |
|
24 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin | |
| 25 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout |
|
25 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout | |
| 26 | add wave -noupdate -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.address {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain |
|
26 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain | |
| 27 | add wave -noupdate -label data -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data |
|
27 | add wave -noupdate -label data -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data | |
| 28 | add wave -noupdate -label grant /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout.grant |
|
28 | add wave -noupdate -label grant /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout.grant | |
| 29 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout |
|
29 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout | |
| 30 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_0(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_0 |
|
30 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_0 | |
| 31 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_0(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_0 |
|
31 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_0 | |
| 32 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_1(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_1 |
|
32 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_1 | |
| 33 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_1(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_1 |
|
33 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_1 | |
| 34 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_2 |
|
34 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_2 | |
| 35 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2 |
|
35 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/async_1mx16_1/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2 | |
| 36 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_3 |
|
36 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/async_1mx16_0/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_3 | |
| 37 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_3 |
|
37 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_3 | |
| 38 | TreeUpdate [SetDefaultTree] |
|
38 | TreeUpdate [SetDefaultTree] | |
| 39 |
WaveRestoreCursors {{Cursor 1} { |
|
39 | WaveRestoreCursors {{Cursor 1} {340947831721 ps} 0} | |
| 40 | configure wave -namecolwidth 540 |
|
40 | configure wave -namecolwidth 540 | |
| 41 | configure wave -valuecolwidth 316 |
|
41 | configure wave -valuecolwidth 316 | |
| 42 | configure wave -justifyvalue left |
|
42 | configure wave -justifyvalue left | |
| 43 | configure wave -signalnamewidth 0 |
|
43 | configure wave -signalnamewidth 0 | |
| 44 | configure wave -snapdistance 10 |
|
44 | configure wave -snapdistance 10 | |
| 45 | configure wave -datasetprefix 0 |
|
45 | configure wave -datasetprefix 0 | |
| 46 | configure wave -rowmargin 4 |
|
46 | configure wave -rowmargin 4 | |
| 47 | configure wave -childrowmargin 2 |
|
47 | configure wave -childrowmargin 2 | |
| 48 | configure wave -gridoffset 0 |
|
48 | configure wave -gridoffset 0 | |
| 49 | configure wave -gridperiod 1 |
|
49 | configure wave -gridperiod 1 | |
| 50 | configure wave -griddelta 40 |
|
50 | configure wave -griddelta 40 | |
| 51 | configure wave -timeline 0 |
|
51 | configure wave -timeline 0 | |
| 52 | configure wave -timelineunits ns |
|
52 | configure wave -timelineunits ns | |
| 53 | update |
|
53 | update | |
| 54 |
WaveRestoreZoom {0 ps} {6 |
|
54 | WaveRestoreZoom {0 ps} {628873035 ns} | |
| @@ -1,529 +1,513 | |||||
| 1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
| 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
| 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
| 4 | -- |
|
4 | -- | |
| 5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
| 6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
| 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
| 8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
| 9 | -- |
|
9 | -- | |
| 10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
| 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
| 14 | -- |
|
14 | -- | |
| 15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
| 16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
| 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
| 19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
| 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
| 21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
| 22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
| 23 | USE IEEE.numeric_std.ALL; |
|
23 | USE IEEE.numeric_std.ALL; | |
| 24 | USE IEEE.std_logic_1164.ALL; |
|
24 | USE IEEE.std_logic_1164.ALL; | |
| 25 | LIBRARY grlib; |
|
25 | LIBRARY grlib; | |
| 26 | USE grlib.amba.ALL; |
|
26 | USE grlib.amba.ALL; | |
| 27 | USE grlib.stdlib.ALL; |
|
27 | USE grlib.stdlib.ALL; | |
| 28 | LIBRARY techmap; |
|
28 | LIBRARY techmap; | |
| 29 | USE techmap.gencomp.ALL; |
|
29 | USE techmap.gencomp.ALL; | |
| 30 | LIBRARY gaisler; |
|
30 | LIBRARY gaisler; | |
| 31 | USE gaisler.memctrl.ALL; |
|
31 | USE gaisler.memctrl.ALL; | |
| 32 | USE gaisler.leon3.ALL; |
|
32 | USE gaisler.leon3.ALL; | |
| 33 | USE gaisler.uart.ALL; |
|
33 | USE gaisler.uart.ALL; | |
| 34 | USE gaisler.misc.ALL; |
|
34 | USE gaisler.misc.ALL; | |
| 35 | USE gaisler.spacewire.ALL; |
|
35 | USE gaisler.spacewire.ALL; | |
| 36 | LIBRARY esa; |
|
36 | LIBRARY esa; | |
| 37 | USE esa.memoryctrl.ALL; |
|
37 | USE esa.memoryctrl.ALL; | |
| 38 | LIBRARY lpp; |
|
38 | LIBRARY lpp; | |
| 39 | USE lpp.lpp_memory.ALL; |
|
39 | USE lpp.lpp_memory.ALL; | |
| 40 | USE lpp.lpp_ad_conv.ALL; |
|
40 | USE lpp.lpp_ad_conv.ALL; | |
| 41 | --USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
|
41 | --USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |
| 42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
|
42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
| 43 | USE lpp.iir_filter.ALL; |
|
43 | USE lpp.iir_filter.ALL; | |
| 44 | USE lpp.general_purpose.ALL; |
|
44 | USE lpp.general_purpose.ALL; | |
| 45 | USE lpp.lpp_lfr_time_management.ALL; |
|
45 | USE lpp.lpp_lfr_time_management.ALL; | |
| 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
46 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
| 47 |
|
47 | |||
| 48 | ENTITY MINI_LFR_top IS |
|
48 | ENTITY MINI_LFR_top IS | |
| 49 |
|
49 | |||
| 50 | PORT ( |
|
50 | PORT ( | |
| 51 | clk_50 : IN STD_LOGIC; |
|
51 | clk_50 : IN STD_LOGIC; | |
| 52 | clk_49 : IN STD_LOGIC; |
|
52 | clk_49 : IN STD_LOGIC; | |
| 53 | reset : IN STD_LOGIC; |
|
53 | reset : IN STD_LOGIC; | |
| 54 | --BPs |
|
54 | --BPs | |
| 55 | BP0 : IN STD_LOGIC; |
|
55 | BP0 : IN STD_LOGIC; | |
| 56 | BP1 : IN STD_LOGIC; |
|
56 | BP1 : IN STD_LOGIC; | |
| 57 | --LEDs |
|
57 | --LEDs | |
| 58 | LED0 : OUT STD_LOGIC; |
|
58 | LED0 : OUT STD_LOGIC; | |
| 59 | LED1 : OUT STD_LOGIC; |
|
59 | LED1 : OUT STD_LOGIC; | |
| 60 | LED2 : OUT STD_LOGIC; |
|
60 | LED2 : OUT STD_LOGIC; | |
| 61 | --UARTs |
|
61 | --UARTs | |
| 62 | TXD1 : IN STD_LOGIC; |
|
62 | TXD1 : IN STD_LOGIC; | |
| 63 | RXD1 : OUT STD_LOGIC; |
|
63 | RXD1 : OUT STD_LOGIC; | |
| 64 |
nCTS1 : OUT STD_LOGIC; |
|
64 | nCTS1 : OUT STD_LOGIC; | |
| 65 |
nRTS1 : IN STD_LOGIC; |
|
65 | nRTS1 : IN STD_LOGIC; | |
| 66 |
|
66 | |||
| 67 | TXD2 : IN STD_LOGIC; |
|
67 | TXD2 : IN STD_LOGIC; | |
| 68 | RXD2 : OUT STD_LOGIC; |
|
68 | RXD2 : OUT STD_LOGIC; | |
| 69 |
nCTS2 : OUT STD_LOGIC; |
|
69 | nCTS2 : OUT STD_LOGIC; | |
| 70 |
nDTR2 : IN STD_LOGIC; |
|
70 | nDTR2 : IN STD_LOGIC; | |
| 71 |
nRTS2 : IN STD_LOGIC; |
|
71 | nRTS2 : IN STD_LOGIC; | |
| 72 |
nDCD2 : OUT STD_LOGIC; |
|
72 | nDCD2 : OUT STD_LOGIC; | |
| 73 |
|
73 | |||
| 74 | --EXT CONNECTOR |
|
74 | --EXT CONNECTOR | |
| 75 | IO0 : INOUT STD_LOGIC; |
|
75 | IO0 : INOUT STD_LOGIC; | |
| 76 | IO1 : INOUT STD_LOGIC; |
|
76 | IO1 : INOUT STD_LOGIC; | |
| 77 | IO2 : INOUT STD_LOGIC; |
|
77 | IO2 : INOUT STD_LOGIC; | |
| 78 | IO3 : INOUT STD_LOGIC; |
|
78 | IO3 : INOUT STD_LOGIC; | |
| 79 | IO4 : INOUT STD_LOGIC; |
|
79 | IO4 : INOUT STD_LOGIC; | |
| 80 | IO5 : INOUT STD_LOGIC; |
|
80 | IO5 : INOUT STD_LOGIC; | |
| 81 | IO6 : INOUT STD_LOGIC; |
|
81 | IO6 : INOUT STD_LOGIC; | |
| 82 | IO7 : INOUT STD_LOGIC; |
|
82 | IO7 : INOUT STD_LOGIC; | |
| 83 | IO8 : INOUT STD_LOGIC; |
|
83 | IO8 : INOUT STD_LOGIC; | |
| 84 | IO9 : INOUT STD_LOGIC; |
|
84 | IO9 : INOUT STD_LOGIC; | |
| 85 | IO10 : INOUT STD_LOGIC; |
|
85 | IO10 : INOUT STD_LOGIC; | |
| 86 | IO11 : INOUT STD_LOGIC; |
|
86 | IO11 : INOUT STD_LOGIC; | |
| 87 |
|
87 | |||
| 88 | --SPACE WIRE |
|
88 | --SPACE WIRE | |
| 89 |
SPW_EN : OUT STD_LOGIC; |
|
89 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |
| 90 |
SPW_NOM_DIN : IN STD_LOGIC; |
|
90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |
| 91 | SPW_NOM_SIN : IN STD_LOGIC; |
|
91 | SPW_NOM_SIN : IN STD_LOGIC; | |
| 92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
|
92 | SPW_NOM_DOUT : OUT STD_LOGIC; | |
| 93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
|
93 | SPW_NOM_SOUT : OUT STD_LOGIC; | |
| 94 |
SPW_RED_DIN : IN STD_LOGIC; |
|
94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |
| 95 | SPW_RED_SIN : IN STD_LOGIC; |
|
95 | SPW_RED_SIN : IN STD_LOGIC; | |
| 96 | SPW_RED_DOUT : OUT STD_LOGIC; |
|
96 | SPW_RED_DOUT : OUT STD_LOGIC; | |
| 97 | SPW_RED_SOUT : OUT STD_LOGIC; |
|
97 | SPW_RED_SOUT : OUT STD_LOGIC; | |
| 98 | -- MINI LFR ADC INPUTS |
|
98 | -- MINI LFR ADC INPUTS | |
| 99 | ADC_nCS : OUT STD_LOGIC; |
|
99 | ADC_nCS : OUT STD_LOGIC; | |
| 100 | ADC_CLK : OUT STD_LOGIC; |
|
100 | ADC_CLK : OUT STD_LOGIC; | |
| 101 |
ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
| 102 |
|
102 | |||
| 103 | -- SRAM |
|
103 | -- SRAM | |
| 104 | SRAM_nWE : OUT STD_LOGIC; |
|
104 | SRAM_nWE : OUT STD_LOGIC; | |
| 105 | SRAM_CE : OUT STD_LOGIC; |
|
105 | SRAM_CE : OUT STD_LOGIC; | |
| 106 | SRAM_nOE : OUT STD_LOGIC; |
|
106 | SRAM_nOE : OUT STD_LOGIC; | |
| 107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
| 109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
| 110 | ); |
|
110 | ); | |
| 111 |
|
111 | |||
| 112 | END MINI_LFR_top; |
|
112 | END MINI_LFR_top; | |
| 113 |
|
113 | |||
| 114 |
|
114 | |||
| 115 | ARCHITECTURE beh OF MINI_LFR_top IS |
|
115 | ARCHITECTURE beh OF MINI_LFR_top IS | |
| 116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
|
116 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
| 117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
|
117 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
| 118 | ----------------------------------------------------------------------------- |
|
118 | ----------------------------------------------------------------------------- | |
| 119 |
SIGNAL coarse_time |
|
119 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 120 |
SIGNAL fine_time |
|
120 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
| 121 | -- |
|
121 | -- | |
| 122 | SIGNAL errorn : STD_LOGIC; |
|
122 | SIGNAL errorn : STD_LOGIC; | |
| 123 | -- UART AHB --------------------------------------------------------------- |
|
123 | -- UART AHB --------------------------------------------------------------- | |
| 124 |
SIGNAL |
|
124 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |
| 125 |
SIGNAL |
|
125 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |
| 126 |
|
126 | |||
| 127 | -- UART APB --------------------------------------------------------------- |
|
127 | -- UART APB --------------------------------------------------------------- | |
| 128 |
SIGNAL |
|
128 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |
| 129 |
SIGNAL |
|
129 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |
| 130 |
|
|
130 | -- | |
| 131 | SIGNAL I00_s : STD_LOGIC; |
|
131 | SIGNAL I00_s : STD_LOGIC; | |
| 132 |
|
132 | |||
| 133 | -- CONSTANTS |
|
133 | -- CONSTANTS | |
| 134 |
|
|
134 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
| 135 | -- |
|
135 | -- | |
| 136 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
|
136 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
| 137 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
|
137 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |
| 138 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
|
138 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
| 139 |
|
139 | |||
| 140 |
SIGNAL |
|
140 | SIGNAL apbi_ext : apb_slv_in_type; | |
| 141 |
SIGNAL |
|
141 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); | |
| 142 |
SIGNAL |
|
142 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
| 143 |
SIGNAL |
|
143 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); | |
| 144 |
SIGNAL |
|
144 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
| 145 |
SIGNAL |
|
145 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); | |
| 146 |
|
146 | |||
| 147 | -- Spacewire signals |
|
147 | -- Spacewire signals | |
| 148 |
SIGNAL dtmp |
|
148 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 149 |
SIGNAL stmp |
|
149 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 150 |
SIGNAL spw_rxclk |
|
150 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 151 |
SIGNAL spw_rxtxclk |
|
151 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
| 152 |
SIGNAL spw_rxclkn |
|
152 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
| 153 |
SIGNAL spw_clk |
|
153 | SIGNAL spw_clk : STD_LOGIC; | |
| 154 |
SIGNAL swni |
|
154 | SIGNAL swni : grspw_in_type; | |
| 155 |
SIGNAL swno |
|
155 | SIGNAL swno : grspw_out_type; | |
| 156 |
-- SIGNAL clkmn |
|
156 | -- SIGNAL clkmn : STD_ULOGIC; | |
| 157 |
-- SIGNAL txclk |
|
157 | -- SIGNAL txclk : STD_ULOGIC; | |
| 158 |
|
158 | |||
| 159 | --GPIO |
|
159 | --GPIO | |
| 160 |
SIGNAL gpioi |
|
160 | SIGNAL gpioi : gpio_in_type; | |
| 161 |
SIGNAL gpioo |
|
161 | SIGNAL gpioo : gpio_out_type; | |
| 162 |
|
162 | |||
| 163 | -- AD Converter ADS7886 |
|
163 | -- AD Converter ADS7886 | |
| 164 |
SIGNAL sample |
|
164 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
| 165 |
SIGNAL sample_val |
|
165 | SIGNAL sample_val : STD_LOGIC; | |
| 166 |
SIGNAL ADC_nCS_sig |
|
166 | SIGNAL ADC_nCS_sig : STD_LOGIC; | |
| 167 |
SIGNAL ADC_CLK_sig |
|
167 | SIGNAL ADC_CLK_sig : STD_LOGIC; | |
| 168 |
SIGNAL ADC_SDO_sig |
|
168 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
| 169 |
|
169 | |||
| 170 |
SIGNAL |
|
170 | SIGNAL bias_fail_sw_sig : STD_LOGIC; | |
| 171 |
|
171 | |||
| 172 | BEGIN -- beh |
|
172 | BEGIN -- beh | |
| 173 |
|
173 | |||
| 174 | ----------------------------------------------------------------------------- |
|
174 | ----------------------------------------------------------------------------- | |
| 175 | -- CLK |
|
175 | -- CLK | |
| 176 | ----------------------------------------------------------------------------- |
|
176 | ----------------------------------------------------------------------------- | |
| 177 |
|
177 | |||
| 178 | PROCESS(clk_50) |
|
178 | PROCESS(clk_50) | |
| 179 | BEGIN |
|
179 | BEGIN | |
| 180 | IF clk_50'EVENT AND clk_50 = '1' THEN |
|
180 | IF clk_50'EVENT AND clk_50 = '1' THEN | |
| 181 | clk_50_s <= NOT clk_50_s; |
|
181 | clk_50_s <= NOT clk_50_s; | |
| 182 | END IF; |
|
182 | END IF; | |
| 183 | END PROCESS; |
|
183 | END PROCESS; | |
| 184 |
|
184 | |||
| 185 | PROCESS(clk_50_s) |
|
185 | PROCESS(clk_50_s) | |
| 186 | BEGIN |
|
186 | BEGIN | |
| 187 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
|
187 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |
| 188 | clk_25 <= NOT clk_25; |
|
188 | clk_25 <= NOT clk_25; | |
| 189 | END IF; |
|
189 | END IF; | |
| 190 | END PROCESS; |
|
190 | END PROCESS; | |
| 191 |
|
191 | |||
| 192 | ----------------------------------------------------------------------------- |
|
192 | ----------------------------------------------------------------------------- | |
| 193 |
|
193 | |||
| 194 | PROCESS (clk_25, reset) |
|
194 | PROCESS (clk_25, reset) | |
| 195 | BEGIN -- PROCESS |
|
195 | BEGIN -- PROCESS | |
| 196 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
196 | IF reset = '0' THEN -- asynchronous reset (active low) | |
| 197 | LED0 <= '0'; |
|
197 | LED0 <= '0'; | |
| 198 | LED1 <= '0'; |
|
198 | LED1 <= '0'; | |
| 199 | LED2 <= '0'; |
|
199 | LED2 <= '0'; | |
| 200 | --IO1 <= '0'; |
|
200 | --IO1 <= '0'; | |
| 201 | --IO2 <= '1'; |
|
201 | --IO2 <= '1'; | |
| 202 | --IO3 <= '0'; |
|
202 | --IO3 <= '0'; | |
| 203 | --IO4 <= '0'; |
|
203 | --IO4 <= '0'; | |
| 204 | --IO5 <= '0'; |
|
204 | --IO5 <= '0'; | |
| 205 | --IO6 <= '0'; |
|
205 | --IO6 <= '0'; | |
| 206 | --IO7 <= '0'; |
|
206 | --IO7 <= '0'; | |
| 207 | --IO8 <= '0'; |
|
207 | --IO8 <= '0'; | |
| 208 | --IO9 <= '0'; |
|
208 | --IO9 <= '0'; | |
| 209 | --IO10 <= '0'; |
|
209 | --IO10 <= '0'; | |
| 210 | --IO11 <= '0'; |
|
210 | --IO11 <= '0'; | |
| 211 |
ELSIF clk_25' |
|
211 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
| 212 | LED0 <= '0'; |
|
212 | LED0 <= '0'; | |
| 213 | LED1 <= '1'; |
|
213 | LED1 <= '1'; | |
| 214 | LED2 <= BP0; |
|
214 | LED2 <= BP0; | |
| 215 | --IO1 <= '1'; |
|
215 | --IO1 <= '1'; | |
| 216 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
|
216 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; | |
| 217 | --IO3 <= ADC_SDO(0); |
|
217 | --IO3 <= ADC_SDO(0); | |
| 218 | --IO4 <= ADC_SDO(1); |
|
218 | --IO4 <= ADC_SDO(1); | |
| 219 | --IO5 <= ADC_SDO(2); |
|
219 | --IO5 <= ADC_SDO(2); | |
| 220 | --IO6 <= ADC_SDO(3); |
|
220 | --IO6 <= ADC_SDO(3); | |
| 221 | --IO7 <= ADC_SDO(4); |
|
221 | --IO7 <= ADC_SDO(4); | |
| 222 | --IO8 <= ADC_SDO(5); |
|
222 | --IO8 <= ADC_SDO(5); | |
| 223 | --IO9 <= ADC_SDO(6); |
|
223 | --IO9 <= ADC_SDO(6); | |
| 224 | --IO10 <= ADC_SDO(7); |
|
224 | --IO10 <= ADC_SDO(7); | |
| 225 |
IO11 |
|
225 | IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
| 226 | END IF; |
|
226 | END IF; | |
| 227 | END PROCESS; |
|
227 | END PROCESS; | |
| 228 |
|
228 | |||
| 229 | PROCESS (clk_49, reset) |
|
229 | PROCESS (clk_49, reset) | |
| 230 | BEGIN -- PROCESS |
|
230 | BEGIN -- PROCESS | |
| 231 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
231 | IF reset = '0' THEN -- asynchronous reset (active low) | |
| 232 |
I00_s |
|
232 | I00_s <= '0'; | |
| 233 |
ELSIF clk_49' |
|
233 | ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge | |
| 234 |
|
|
234 | I00_s <= NOT I00_s; | |
| 235 |
|
|
235 | END IF; | |
| 236 | END PROCESS; |
|
236 | END PROCESS; | |
| 237 | -- IO0 <= I00_s; |
|
237 | -- IO0 <= I00_s; | |
| 238 |
|
238 | |||
| 239 | --UARTs |
|
239 | --UARTs | |
| 240 |
nCTS1 |
|
240 | nCTS1 <= '1'; | |
| 241 |
nCTS2 |
|
241 | nCTS2 <= '1'; | |
| 242 |
nDCD2 |
|
242 | nDCD2 <= '1'; | |
| 243 |
|
243 | |||
| 244 | --EXT CONNECTOR |
|
244 | --EXT CONNECTOR | |
| 245 |
|
245 | |||
| 246 | --SPACE WIRE |
|
246 | --SPACE WIRE | |
| 247 |
|
247 | |||
| 248 | leon3_soc_1: leon3_soc |
|
248 | leon3_soc_1 : leon3_soc | |
| 249 | GENERIC MAP ( |
|
249 | GENERIC MAP ( | |
| 250 | fabtech => apa3e, |
|
250 | fabtech => apa3e, | |
| 251 | memtech => apa3e, |
|
251 | memtech => apa3e, | |
| 252 | padtech => inferred, |
|
252 | padtech => inferred, | |
| 253 | clktech => inferred, |
|
253 | clktech => inferred, | |
| 254 | disas => 0, |
|
254 | disas => 0, | |
| 255 | dbguart => 0, |
|
255 | dbguart => 0, | |
| 256 | pclow => 2, |
|
256 | pclow => 2, | |
| 257 | clk_freq => 25000, |
|
257 | clk_freq => 25000, | |
| 258 | NB_CPU => 1, |
|
258 | NB_CPU => 1, | |
| 259 | ENABLE_FPU => 1, |
|
259 | ENABLE_FPU => 1, | |
| 260 | FPU_NETLIST => 0, |
|
260 | FPU_NETLIST => 0, | |
| 261 | ENABLE_DSU => 1, |
|
261 | ENABLE_DSU => 1, | |
| 262 | ENABLE_AHB_UART => 1, |
|
262 | ENABLE_AHB_UART => 1, | |
| 263 | ENABLE_APB_UART => 1, |
|
263 | ENABLE_APB_UART => 1, | |
| 264 | ENABLE_IRQMP => 1, |
|
264 | ENABLE_IRQMP => 1, | |
| 265 | ENABLE_GPT => 1, |
|
265 | ENABLE_GPT => 1, | |
| 266 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
266 | NB_AHB_MASTER => NB_AHB_MASTER, | |
| 267 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
267 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |
| 268 | NB_APB_SLAVE => NB_APB_SLAVE) |
|
268 | NB_APB_SLAVE => NB_APB_SLAVE) | |
| 269 | PORT MAP ( |
|
269 | PORT MAP ( | |
| 270 |
clk |
|
270 | clk => clk_25, | |
| 271 |
reset |
|
271 | reset => reset, | |
| 272 |
errorn |
|
272 | errorn => errorn, | |
| 273 |
ahbrxd |
|
273 | ahbrxd => TXD1, | |
| 274 |
ahbtxd |
|
274 | ahbtxd => RXD1, | |
| 275 |
urxd1 |
|
275 | urxd1 => TXD2, | |
| 276 |
utxd1 |
|
276 | utxd1 => RXD2, | |
| 277 |
address |
|
277 | address => SRAM_A, | |
| 278 |
data |
|
278 | data => SRAM_DQ, | |
| 279 |
nSRAM_BE0 |
|
279 | nSRAM_BE0 => SRAM_nBE(0), | |
| 280 |
nSRAM_BE1 |
|
280 | nSRAM_BE1 => SRAM_nBE(1), | |
| 281 |
nSRAM_BE2 |
|
281 | nSRAM_BE2 => SRAM_nBE(2), | |
| 282 |
nSRAM_BE3 |
|
282 | nSRAM_BE3 => SRAM_nBE(3), | |
| 283 |
nSRAM_WE |
|
283 | nSRAM_WE => SRAM_nWE, | |
| 284 |
nSRAM_CE |
|
284 | nSRAM_CE => SRAM_CE, | |
| 285 |
nSRAM_OE |
|
285 | nSRAM_OE => SRAM_nOE, | |
| 286 |
|
286 | |||
| 287 | apbi_ext => apbi_ext, |
|
287 | apbi_ext => apbi_ext, | |
| 288 | apbo_ext => apbo_ext, |
|
288 | apbo_ext => apbo_ext, | |
| 289 | ahbi_s_ext => ahbi_s_ext, |
|
289 | ahbi_s_ext => ahbi_s_ext, | |
| 290 | ahbo_s_ext => ahbo_s_ext, |
|
290 | ahbo_s_ext => ahbo_s_ext, | |
| 291 | ahbi_m_ext => ahbi_m_ext, |
|
291 | ahbi_m_ext => ahbi_m_ext, | |
| 292 | ahbo_m_ext => ahbo_m_ext); |
|
292 | ahbo_m_ext => ahbo_m_ext); | |
| 293 |
|
293 | |||
| 294 | ------------------------------------------------------------------------------- |
|
294 | ------------------------------------------------------------------------------- | |
| 295 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
295 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |
| 296 | ------------------------------------------------------------------------------- |
|
296 | ------------------------------------------------------------------------------- | |
| 297 | apb_lfr_time_management_1: apb_lfr_time_management |
|
297 | apb_lfr_time_management_1 : apb_lfr_time_management | |
| 298 | GENERIC MAP ( |
|
298 | GENERIC MAP ( | |
| 299 | pindex => 6, |
|
299 | pindex => 6, | |
| 300 | paddr => 6, |
|
300 | paddr => 6, | |
| 301 | pmask => 16#fff#, |
|
301 | pmask => 16#fff#, | |
| 302 | pirq => 12) |
|
302 | pirq => 12) | |
| 303 | PORT MAP ( |
|
303 | PORT MAP ( | |
| 304 | clk25MHz => clk_25, |
|
304 | clk25MHz => clk_25, | |
| 305 | clk49_152MHz => clk_49, |
|
305 | clk49_152MHz => clk_49, | |
| 306 | resetn => reset, |
|
306 | resetn => reset, | |
| 307 | grspw_tick => swno.tickout, |
|
307 | grspw_tick => swno.tickout, | |
| 308 | apbi => apbi_ext, |
|
308 | apbi => apbi_ext, | |
| 309 | apbo => apbo_ext(6), |
|
309 | apbo => apbo_ext(6), | |
| 310 | coarse_time => coarse_time, |
|
310 | coarse_time => coarse_time, | |
| 311 | fine_time => fine_time); |
|
311 | fine_time => fine_time); | |
| 312 |
|
312 | |||
| 313 | ----------------------------------------------------------------------- |
|
313 | ----------------------------------------------------------------------- | |
| 314 | --- SpaceWire -------------------------------------------------------- |
|
314 | --- SpaceWire -------------------------------------------------------- | |
| 315 | ----------------------------------------------------------------------- |
|
315 | ----------------------------------------------------------------------- | |
| 316 |
|
316 | |||
| 317 |
|
|
317 | SPW_EN <= '1'; | |
| 318 |
|
318 | |||
| 319 |
|
|
319 | spw_clk <= clk_50_s; | |
| 320 |
|
|
320 | spw_rxtxclk <= spw_clk; | |
| 321 |
|
|
321 | spw_rxclkn <= NOT spw_rxtxclk; | |
| 322 |
|
322 | |||
| 323 |
|
|
323 | -- PADS for SPW1 | |
| 324 |
|
|
324 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |
| 325 |
|
|
325 | PORT MAP (SPW_NOM_DIN, dtmp(0)); | |
| 326 |
|
|
326 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |
| 327 |
|
|
327 | PORT MAP (SPW_NOM_SIN, stmp(0)); | |
| 328 |
|
|
328 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |
| 329 |
|
|
329 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); | |
| 330 |
|
|
330 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |
| 331 |
|
|
331 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); | |
| 332 |
|
|
332 | -- PADS FOR SPW2 | |
| 333 |
|
|
333 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
| 334 |
|
|
334 | PORT MAP (SPW_RED_SIN, dtmp(1)); | |
| 335 |
|
|
335 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
| 336 |
|
|
336 | PORT MAP (SPW_RED_DIN, stmp(1)); | |
| 337 |
|
|
337 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |
| 338 |
|
|
338 | PORT MAP (SPW_RED_DOUT, swno.d(1)); | |
| 339 |
|
|
339 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |
| 340 |
|
|
340 | PORT MAP (SPW_RED_SOUT, swno.s(1)); | |
| 341 |
|
341 | |||
| 342 |
|
|
342 | -- GRSPW PHY | |
| 343 |
|
|
343 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |
| 344 | spw_inputloop: for j in 0 to 1 generate |
|
344 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
| 345 |
|
|
345 | spw_phy0 : grspw_phy | |
| 346 | generic map( |
|
346 | GENERIC MAP( | |
| 347 |
|
|
347 | tech => apa3e, | |
| 348 |
|
|
348 | rxclkbuftype => 1, | |
| 349 |
|
|
349 | scantest => 0) | |
| 350 | port map( |
|
350 | PORT MAP( | |
| 351 |
|
|
351 | rxrst => swno.rxrst, | |
| 352 |
|
|
352 | di => dtmp(j), | |
| 353 |
|
|
353 | si => stmp(j), | |
| 354 |
|
|
354 | rxclko => spw_rxclk(j), | |
| 355 |
|
|
355 | do => swni.d(j), | |
| 356 |
|
|
356 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
| 357 |
|
|
357 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
| 358 | end generate spw_inputloop; |
|
358 | END GENERATE spw_inputloop; | |
| 359 |
|
359 | |||
| 360 |
|
|
360 | -- SPW core | |
| 361 | sw0 : grspwm generic map( |
|
361 | sw0 : grspwm GENERIC MAP( | |
| 362 |
|
|
362 | tech => apa3e, | |
| 363 |
|
|
363 | hindex => 1, | |
| 364 |
|
|
364 | pindex => 5, | |
| 365 |
|
|
365 | paddr => 5, | |
| 366 | pirq => 11, |
|
366 | pirq => 11, | |
| 367 |
|
|
367 | sysfreq => 25000, -- CPU_FREQ | |
| 368 |
|
|
368 | rmap => 1, | |
| 369 |
|
|
369 | rmapcrc => 1, | |
| 370 |
|
|
370 | fifosize1 => 16, | |
| 371 |
|
|
371 | fifosize2 => 16, | |
| 372 |
|
|
372 | rxclkbuftype => 1, | |
| 373 |
|
|
373 | rxunaligned => 0, | |
| 374 |
|
|
374 | rmapbufs => 4, | |
| 375 | ft => 0, |
|
375 | ft => 0, | |
| 376 |
|
|
376 | netlist => 0, | |
| 377 |
|
|
377 | ports => 2, | |
| 378 |
|
|
378 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
| 379 |
|
|
379 | memtech => apa3e, | |
| 380 |
|
|
380 | destkey => 2, | |
| 381 |
|
|
381 | spwcore => 1 | |
| 382 |
|
|
382 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
| 383 |
|
|
383 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
| 384 |
|
|
384 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
| 385 | ) |
|
385 | ) | |
| 386 |
|
|
386 | PORT MAP(reset, clk_25, spw_rxclk(0), | |
| 387 |
|
|
387 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |
| 388 |
|
|
388 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |
| 389 |
|
|
389 | swni, swno); | |
| 390 |
|
390 | |||
| 391 |
|
|
391 | swni.tickin <= '0'; | |
| 392 |
|
|
392 | swni.rmapen <= '1'; | |
| 393 |
|
|
393 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |
| 394 |
|
|
394 | swni.tickinraw <= '0'; | |
| 395 |
|
|
395 | swni.timein <= (OTHERS => '0'); | |
| 396 |
|
|
396 | swni.dcrstval <= (OTHERS => '0'); | |
| 397 |
|
|
397 | swni.timerrstval <= (OTHERS => '0'); | |
| 398 |
|
398 | |||
| 399 | ------------------------------------------------------------------------------- |
|
399 | ------------------------------------------------------------------------------- | |
| 400 | -- LFR ------------------------------------------------------------------------ |
|
400 | -- LFR ------------------------------------------------------------------------ | |
| 401 | ------------------------------------------------------------------------------- |
|
401 | ------------------------------------------------------------------------------- | |
| 402 | -- lpp_lfr_1 : lpp_lfr |
|
402 | -- lpp_lfr_1 : lpp_lfr | |
| 403 | -- GENERIC MAP ( |
|
403 | -- GENERIC MAP ( | |
| 404 | -- Mem_use => use_RAM, |
|
404 | -- Mem_use => use_RAM, | |
| 405 | -- nb_data_by_buffer_size => 32, |
|
405 | -- nb_data_by_buffer_size => 32, | |
| 406 | -- nb_word_by_buffer_size => 30, |
|
406 | -- nb_word_by_buffer_size => 30, | |
| 407 | -- nb_snapshot_param_size => 32, |
|
407 | -- nb_snapshot_param_size => 32, | |
| 408 | -- delta_vector_size => 32, |
|
408 | -- delta_vector_size => 32, | |
| 409 | -- delta_vector_size_f0_2 => 7, -- log2(96) |
|
409 | -- delta_vector_size_f0_2 => 7, -- log2(96) | |
| 410 | -- pindex => 6, |
|
410 | -- pindex => 6, | |
| 411 | -- paddr => 6, |
|
411 | -- paddr => 6, | |
| 412 | -- pmask => 16#fff#, |
|
412 | -- pmask => 16#fff#, | |
| 413 | -- pirq_ms => 6, |
|
413 | -- pirq_ms => 6, | |
| 414 | -- pirq_wfp => 14, |
|
414 | -- pirq_wfp => 14, | |
| 415 | -- hindex => 2, |
|
415 | -- hindex => 2, | |
| 416 | -- top_lfr_version => X"00000005") |
|
416 | -- top_lfr_version => X"00000005") | |
| 417 | -- PORT MAP ( |
|
417 | -- PORT MAP ( | |
| 418 | -- clk => clk_25, |
|
418 | -- clk => clk_25, | |
| 419 | -- rstn => reset, |
|
419 | -- rstn => reset, | |
| 420 | -- sample_B => sample(2 DOWNTO 0), |
|
420 | -- sample_B => sample(2 DOWNTO 0), | |
| 421 | -- sample_E => sample(7 DOWNTO 3), |
|
421 | -- sample_E => sample(7 DOWNTO 3), | |
| 422 | -- sample_val => sample_val, |
|
422 | -- sample_val => sample_val, | |
| 423 | -- apbi => apbi_ext, |
|
423 | -- apbi => apbi_ext, | |
| 424 | -- apbo => apbo_ext(6), |
|
424 | -- apbo => apbo_ext(6), | |
| 425 | -- ahbi => ahbi_m_ext, |
|
425 | -- ahbi => ahbi_m_ext, | |
| 426 | -- ahbo => ahbo_m_ext(2), |
|
426 | -- ahbo => ahbo_m_ext(2), | |
| 427 | -- coarse_time => coarse_time, |
|
427 | -- coarse_time => coarse_time, | |
| 428 | -- fine_time => fine_time, |
|
428 | -- fine_time => fine_time, | |
| 429 | -- data_shaping_BW => bias_fail_sw_sig); |
|
429 | -- data_shaping_BW => bias_fail_sw_sig); | |
| 430 |
|
430 | |||
| 431 |
|
|
431 | waveform_picker0 : top_wf_picker | |
| 432 | GENERIC MAP( |
|
432 | GENERIC MAP( | |
| 433 | hindex => 2, |
|
433 | hindex => 2, | |
| 434 | pindex => 15, |
|
434 | pindex => 15, | |
| 435 | paddr => 15, |
|
435 | paddr => 15, | |
| 436 | pmask => 16#fff#, |
|
436 | pmask => 16#fff#, | |
| 437 | pirq => 14, |
|
437 | pirq => 14, | |
| 438 | tech => apa3e, |
|
438 | tech => apa3e, | |
| 439 | nb_burst_available_size => 12, -- size of the register holding the nb of burst |
|
439 | nb_burst_available_size => 12, -- size of the register holding the nb of burst | |
| 440 | nb_snapshot_param_size => 12, -- size of the register holding the snapshots size |
|
440 | nb_snapshot_param_size => 12, -- size of the register holding the snapshots size | |
| 441 | delta_snapshot_size => 16, -- snapshots period |
|
441 | delta_snapshot_size => 16, -- snapshots period | |
| 442 | delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts |
|
442 | delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts | |
| 443 | delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot |
|
443 | delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot | |
| 444 | ENABLE_FILTER => '1' |
|
444 | ENABLE_FILTER => '1' | |
| 445 | ) |
|
445 | ) | |
| 446 | PORT MAP( |
|
446 | PORT MAP( | |
| 447 | cnv_clk => clk_25, |
|
447 | cnv_clk => clk_25, | |
| 448 | cnv_rstn => reset, |
|
448 | cnv_rstn => reset, | |
| 449 | -- SAMPLES |
|
449 | -- SAMPLES | |
| 450 | sample_B => sample(2 DOWNTO 0), |
|
450 | sample_B => sample(2 DOWNTO 0), | |
| 451 | sample_E => sample(7 DOWNTO 3), |
|
451 | sample_E => sample(7 DOWNTO 3), | |
| 452 |
sample_val => sample_val, |
|
452 | sample_val => sample_val, | |
| 453 | -- AMBA AHB system signals |
|
453 | -- AMBA AHB system signals | |
| 454 | HCLK => clk_25, |
|
454 | HCLK => clk_25, | |
| 455 | HRESETn => reset, |
|
455 | HRESETn => reset, | |
| 456 | -- AMBA APB Slave Interface |
|
456 | -- AMBA APB Slave Interface | |
| 457 | apbi => apbi_ext, |
|
457 | apbi => apbi_ext, | |
| 458 | apbo => apbo_ext(15), |
|
458 | apbo => apbo_ext(15), | |
| 459 | -- AMBA AHB Master Interface |
|
459 | -- AMBA AHB Master Interface | |
| 460 | AHB_Master_In => ahbi_m_ext, |
|
460 | AHB_Master_In => ahbi_m_ext, | |
| 461 | AHB_Master_Out => ahbo_m_ext(2), |
|
461 | AHB_Master_Out => ahbo_m_ext(2), | |
| 462 | -- |
|
462 | -- | |
| 463 | coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time |
|
463 | coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time | |
| 464 | -- |
|
464 | -- | |
| 465 |
data_shaping_BW => bias_fail_sw_sig |
|
465 | data_shaping_BW => bias_fail_sw_sig | |
| 466 | ); |
|
466 | ); | |
| 467 |
|
467 | |||
| 468 |
|
|
468 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 | |
| 469 | GENERIC MAP( |
|
469 | GENERIC MAP( | |
| 470 |
|
|
470 | ChannelCount => 8, | |
| 471 |
|
|
471 | SampleNbBits => 14, | |
| 472 |
ncycle_cnv_high => 80, |
|
472 | ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63 | |
| 473 | ncycle_cnv => 500) -- 49 152 000 / 98304 |
|
473 | ncycle_cnv => 500) -- 49 152 000 / 98304 | |
| 474 | PORT MAP ( |
|
474 | PORT MAP ( | |
| 475 |
|
|
475 | -- CONV | |
| 476 |
|
|
476 | cnv_clk => clk_49, | |
| 477 |
|
|
477 | cnv_rstn => reset, | |
| 478 |
|
|
478 | cnv => ADC_nCS_sig, | |
| 479 |
|
|
479 | -- DATA | |
| 480 |
|
|
480 | clk => clk_25, | |
| 481 |
|
|
481 | rstn => reset, | |
| 482 |
|
|
482 | sck => ADC_CLK_sig, | |
| 483 |
|
|
483 | sdo => ADC_SDO_sig, | |
| 484 |
|
|
484 | -- SAMPLE | |
| 485 |
|
|
485 | sample => sample, | |
| 486 |
|
|
486 | sample_val => sample_val); | |
| 487 |
|
||||
| 488 | IO10 <= ADC_SDO_sig(5); |
|
|||
| 489 | IO9 <= ADC_SDO_sig(4); |
|
|||
| 490 | IO8 <= ADC_SDO_sig(3); |
|
|||
| 491 |
|
487 | |||
| 492 |
|
|
488 | IO10 <= ADC_SDO_sig(5); | |
| 493 |
|
|
489 | IO9 <= ADC_SDO_sig(4); | |
| 494 |
|
|
490 | IO8 <= ADC_SDO_sig(3); | |
| 495 |
|
491 | |||
|
|
492 | ADC_nCS <= ADC_nCS_sig; | |||
|
|
493 | ADC_CLK <= ADC_CLK_sig; | |||
|
|
494 | ADC_SDO_sig <= ADC_SDO; | |||
|
|
495 | ||||
| 496 | ---------------------------------------------------------------------- |
|
496 | ---------------------------------------------------------------------- | |
| 497 | --- GPIO ----------------------------------------------------------- |
|
497 | --- GPIO ----------------------------------------------------------- | |
| 498 | ---------------------------------------------------------------------- |
|
498 | ---------------------------------------------------------------------- | |
| 499 |
|
499 | |||
| 500 | grgpio0: grgpio |
|
500 | grgpio0 : grgpio | |
| 501 |
|
|
501 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) | |
| 502 |
|
|
502 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); | |
| 503 |
|
503 | |||
| 504 | pio_pad_0 : iopad |
|
504 | pio_pad_0 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); | |
| 505 | generic map (tech => CFG_PADTECH) |
|
505 | pio_pad_1 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); | |
| 506 | port map (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
|
506 | pio_pad_2 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); | |
| 507 | pio_pad_1 : iopad |
|
507 | pio_pad_3 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); | |
| 508 | generic map (tech => CFG_PADTECH) |
|
508 | pio_pad_4 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); | |
| 509 | port map (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); |
|
509 | pio_pad_5 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); | |
| 510 | pio_pad_2 : iopad |
|
510 | pio_pad_6 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); | |
| 511 | generic map (tech => CFG_PADTECH) |
|
511 | pio_pad_7 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); | |
| 512 | port map (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); |
|
|||
| 513 | pio_pad_3 : iopad |
|
|||
| 514 | generic map (tech => CFG_PADTECH) |
|
|||
| 515 | port map (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); |
|
|||
| 516 | pio_pad_4 : iopad |
|
|||
| 517 | generic map (tech => CFG_PADTECH) |
|
|||
| 518 | port map (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); |
|
|||
| 519 | pio_pad_5 : iopad |
|
|||
| 520 | generic map (tech => CFG_PADTECH) |
|
|||
| 521 | port map (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); |
|
|||
| 522 | pio_pad_6 : iopad |
|
|||
| 523 | generic map (tech => CFG_PADTECH) |
|
|||
| 524 | port map (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); |
|
|||
| 525 | pio_pad_7 : iopad |
|
|||
| 526 | generic map (tech => CFG_PADTECH) |
|
|||
| 527 | port map (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); |
|
|||
| 528 |
|
512 | |||
| 529 | END beh; No newline at end of file |
|
513 | END beh; | |
| @@ -1,492 +1,492 | |||||
| 1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
| 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
| 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
| 4 | -- |
|
4 | -- | |
| 5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
| 6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
| 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
| 8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
| 9 | -- |
|
9 | -- | |
| 10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
| 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
| 14 | -- |
|
14 | -- | |
| 15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
| 16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
| 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
| 19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
| 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
| 21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
| 22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
| 23 | USE IEEE.numeric_std.ALL; |
|
23 | USE IEEE.numeric_std.ALL; | |
| 24 | USE IEEE.std_logic_1164.ALL; |
|
24 | USE IEEE.std_logic_1164.ALL; | |
| 25 | LIBRARY grlib; |
|
25 | LIBRARY grlib; | |
| 26 | USE grlib.amba.ALL; |
|
26 | USE grlib.amba.ALL; | |
| 27 | USE grlib.stdlib.ALL; |
|
27 | USE grlib.stdlib.ALL; | |
| 28 | LIBRARY techmap; |
|
28 | LIBRARY techmap; | |
| 29 | USE techmap.gencomp.ALL; |
|
29 | USE techmap.gencomp.ALL; | |
| 30 | LIBRARY gaisler; |
|
30 | LIBRARY gaisler; | |
| 31 | USE gaisler.memctrl.ALL; |
|
31 | USE gaisler.memctrl.ALL; | |
| 32 | USE gaisler.leon3.ALL; |
|
32 | USE gaisler.leon3.ALL; | |
| 33 | USE gaisler.uart.ALL; |
|
33 | USE gaisler.uart.ALL; | |
| 34 | USE gaisler.misc.ALL; |
|
34 | USE gaisler.misc.ALL; | |
| 35 | USE gaisler.spacewire.ALL; |
|
35 | USE gaisler.spacewire.ALL; | |
| 36 | LIBRARY esa; |
|
36 | LIBRARY esa; | |
| 37 | USE esa.memoryctrl.ALL; |
|
37 | USE esa.memoryctrl.ALL; | |
| 38 | LIBRARY lpp; |
|
38 | LIBRARY lpp; | |
| 39 | USE lpp.lpp_memory.ALL; |
|
39 | USE lpp.lpp_memory.ALL; | |
| 40 | USE lpp.lpp_ad_conv.ALL; |
|
40 | USE lpp.lpp_ad_conv.ALL; | |
| 41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
|
41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |
| 42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
|
42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
| 43 | USE lpp.iir_filter.ALL; |
|
43 | USE lpp.iir_filter.ALL; | |
| 44 | USE lpp.general_purpose.ALL; |
|
44 | USE lpp.general_purpose.ALL; | |
| 45 | USE lpp.lpp_lfr_time_management.ALL; |
|
45 | USE lpp.lpp_lfr_time_management.ALL; | |
| 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
46 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
| 47 |
|
47 | |||
| 48 | ENTITY MINI_LFR_top IS |
|
48 | ENTITY MINI_LFR_top IS | |
| 49 |
|
49 | |||
| 50 | PORT ( |
|
50 | PORT ( | |
| 51 | clk_50 : IN STD_LOGIC; |
|
51 | clk_50 : IN STD_LOGIC; | |
| 52 | clk_49 : IN STD_LOGIC; |
|
52 | clk_49 : IN STD_LOGIC; | |
| 53 | reset : IN STD_LOGIC; |
|
53 | reset : IN STD_LOGIC; | |
| 54 | --BPs |
|
54 | --BPs | |
| 55 | BP0 : IN STD_LOGIC; |
|
55 | BP0 : IN STD_LOGIC; | |
| 56 | BP1 : IN STD_LOGIC; |
|
56 | BP1 : IN STD_LOGIC; | |
| 57 | --LEDs |
|
57 | --LEDs | |
| 58 | LED0 : OUT STD_LOGIC; |
|
58 | LED0 : OUT STD_LOGIC; | |
| 59 | LED1 : OUT STD_LOGIC; |
|
59 | LED1 : OUT STD_LOGIC; | |
| 60 | LED2 : OUT STD_LOGIC; |
|
60 | LED2 : OUT STD_LOGIC; | |
| 61 | --UARTs |
|
61 | --UARTs | |
| 62 | TXD1 : IN STD_LOGIC; |
|
62 | TXD1 : IN STD_LOGIC; | |
| 63 | RXD1 : OUT STD_LOGIC; |
|
63 | RXD1 : OUT STD_LOGIC; | |
| 64 | nCTS1 : OUT STD_LOGIC; |
|
64 | nCTS1 : OUT STD_LOGIC; | |
| 65 | nRTS1 : IN STD_LOGIC; |
|
65 | nRTS1 : IN STD_LOGIC; | |
| 66 |
|
66 | |||
| 67 | TXD2 : IN STD_LOGIC; |
|
67 | TXD2 : IN STD_LOGIC; | |
| 68 | RXD2 : OUT STD_LOGIC; |
|
68 | RXD2 : OUT STD_LOGIC; | |
| 69 | nCTS2 : OUT STD_LOGIC; |
|
69 | nCTS2 : OUT STD_LOGIC; | |
| 70 | nDTR2 : IN STD_LOGIC; |
|
70 | nDTR2 : IN STD_LOGIC; | |
| 71 | nRTS2 : IN STD_LOGIC; |
|
71 | nRTS2 : IN STD_LOGIC; | |
| 72 | nDCD2 : OUT STD_LOGIC; |
|
72 | nDCD2 : OUT STD_LOGIC; | |
| 73 |
|
73 | |||
| 74 | --EXT CONNECTOR |
|
74 | --EXT CONNECTOR | |
| 75 | IO0 : INOUT STD_LOGIC; |
|
75 | IO0 : INOUT STD_LOGIC; | |
| 76 | IO1 : INOUT STD_LOGIC; |
|
76 | IO1 : INOUT STD_LOGIC; | |
| 77 | IO2 : INOUT STD_LOGIC; |
|
77 | IO2 : INOUT STD_LOGIC; | |
| 78 | IO3 : INOUT STD_LOGIC; |
|
78 | IO3 : INOUT STD_LOGIC; | |
| 79 | IO4 : INOUT STD_LOGIC; |
|
79 | IO4 : INOUT STD_LOGIC; | |
| 80 | IO5 : INOUT STD_LOGIC; |
|
80 | IO5 : INOUT STD_LOGIC; | |
| 81 | IO6 : INOUT STD_LOGIC; |
|
81 | IO6 : INOUT STD_LOGIC; | |
| 82 | IO7 : INOUT STD_LOGIC; |
|
82 | IO7 : INOUT STD_LOGIC; | |
| 83 | IO8 : INOUT STD_LOGIC; |
|
83 | IO8 : INOUT STD_LOGIC; | |
| 84 | IO9 : INOUT STD_LOGIC; |
|
84 | IO9 : INOUT STD_LOGIC; | |
| 85 | IO10 : INOUT STD_LOGIC; |
|
85 | IO10 : INOUT STD_LOGIC; | |
| 86 | IO11 : INOUT STD_LOGIC; |
|
86 | IO11 : INOUT STD_LOGIC; | |
| 87 |
|
87 | |||
| 88 | --SPACE WIRE |
|
88 | --SPACE WIRE | |
| 89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
|
89 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |
| 90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
|
90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |
| 91 | SPW_NOM_SIN : IN STD_LOGIC; |
|
91 | SPW_NOM_SIN : IN STD_LOGIC; | |
| 92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
|
92 | SPW_NOM_DOUT : OUT STD_LOGIC; | |
| 93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
|
93 | SPW_NOM_SOUT : OUT STD_LOGIC; | |
| 94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
|
94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |
| 95 | SPW_RED_SIN : IN STD_LOGIC; |
|
95 | SPW_RED_SIN : IN STD_LOGIC; | |
| 96 | SPW_RED_DOUT : OUT STD_LOGIC; |
|
96 | SPW_RED_DOUT : OUT STD_LOGIC; | |
| 97 | SPW_RED_SOUT : OUT STD_LOGIC; |
|
97 | SPW_RED_SOUT : OUT STD_LOGIC; | |
| 98 | -- MINI LFR ADC INPUTS |
|
98 | -- MINI LFR ADC INPUTS | |
| 99 | ADC_nCS : OUT STD_LOGIC; |
|
99 | ADC_nCS : OUT STD_LOGIC; | |
| 100 | ADC_CLK : OUT STD_LOGIC; |
|
100 | ADC_CLK : OUT STD_LOGIC; | |
| 101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
| 102 |
|
102 | |||
| 103 | -- SRAM |
|
103 | -- SRAM | |
| 104 | SRAM_nWE : OUT STD_LOGIC; |
|
104 | SRAM_nWE : OUT STD_LOGIC; | |
| 105 | SRAM_CE : OUT STD_LOGIC; |
|
105 | SRAM_CE : OUT STD_LOGIC; | |
| 106 | SRAM_nOE : OUT STD_LOGIC; |
|
106 | SRAM_nOE : OUT STD_LOGIC; | |
| 107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
| 109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
| 110 | ); |
|
110 | ); | |
| 111 |
|
111 | |||
| 112 | END MINI_LFR_top; |
|
112 | END MINI_LFR_top; | |
| 113 |
|
113 | |||
| 114 |
|
114 | |||
| 115 | ARCHITECTURE beh OF MINI_LFR_top IS |
|
115 | ARCHITECTURE beh OF MINI_LFR_top IS | |
| 116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
|
116 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
| 117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
|
117 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
| 118 | ----------------------------------------------------------------------------- |
|
118 | ----------------------------------------------------------------------------- | |
| 119 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
119 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 120 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
120 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
| 121 | -- |
|
121 | -- | |
| 122 | SIGNAL errorn : STD_LOGIC; |
|
122 | SIGNAL errorn : STD_LOGIC; | |
| 123 | -- UART AHB --------------------------------------------------------------- |
|
123 | -- UART AHB --------------------------------------------------------------- | |
| 124 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
|
124 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |
| 125 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
|
125 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |
| 126 |
|
126 | |||
| 127 | -- UART APB --------------------------------------------------------------- |
|
127 | -- UART APB --------------------------------------------------------------- | |
| 128 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
|
128 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |
| 129 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
|
129 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |
| 130 | -- |
|
130 | -- | |
| 131 | SIGNAL I00_s : STD_LOGIC; |
|
131 | SIGNAL I00_s : STD_LOGIC; | |
| 132 |
|
132 | |||
| 133 | -- CONSTANTS |
|
133 | -- CONSTANTS | |
| 134 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
|
134 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
| 135 | -- |
|
135 | -- | |
| 136 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
|
136 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
| 137 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
|
137 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |
| 138 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
|
138 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
| 139 |
|
139 | |||
| 140 | SIGNAL apbi_ext : apb_slv_in_type; |
|
140 | SIGNAL apbi_ext : apb_slv_in_type; | |
| 141 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
|
141 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); | |
| 142 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
|
142 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
| 143 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
|
143 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); | |
| 144 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
|
144 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
| 145 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
|
145 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); | |
| 146 |
|
146 | |||
| 147 | -- Spacewire signals |
|
147 | -- Spacewire signals | |
| 148 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
148 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 149 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
149 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 150 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
150 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 151 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
|
151 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
| 152 | SIGNAL spw_rxclkn : STD_ULOGIC; |
|
152 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
| 153 | SIGNAL spw_clk : STD_LOGIC; |
|
153 | SIGNAL spw_clk : STD_LOGIC; | |
| 154 | SIGNAL swni : grspw_in_type; |
|
154 | SIGNAL swni : grspw_in_type; | |
| 155 | SIGNAL swno : grspw_out_type; |
|
155 | SIGNAL swno : grspw_out_type; | |
| 156 | -- SIGNAL clkmn : STD_ULOGIC; |
|
156 | -- SIGNAL clkmn : STD_ULOGIC; | |
| 157 | -- SIGNAL txclk : STD_ULOGIC; |
|
157 | -- SIGNAL txclk : STD_ULOGIC; | |
| 158 |
|
158 | |||
| 159 | --GPIO |
|
159 | --GPIO | |
| 160 | SIGNAL gpioi : gpio_in_type; |
|
160 | SIGNAL gpioi : gpio_in_type; | |
| 161 | SIGNAL gpioo : gpio_out_type; |
|
161 | SIGNAL gpioo : gpio_out_type; | |
| 162 |
|
162 | |||
| 163 | -- AD Converter ADS7886 |
|
163 | -- AD Converter ADS7886 | |
| 164 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
164 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
| 165 | SIGNAL sample_val : STD_LOGIC; |
|
165 | SIGNAL sample_val : STD_LOGIC; | |
| 166 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
|
166 | SIGNAL ADC_nCS_sig : STD_LOGIC; | |
| 167 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
|
167 | SIGNAL ADC_CLK_sig : STD_LOGIC; | |
| 168 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
168 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
| 169 |
|
169 | |||
| 170 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
|
170 | SIGNAL bias_fail_sw_sig : STD_LOGIC; | |
| 171 |
|
171 | |||
| 172 | BEGIN -- beh |
|
172 | BEGIN -- beh | |
| 173 |
|
173 | |||
| 174 | ----------------------------------------------------------------------------- |
|
174 | ----------------------------------------------------------------------------- | |
| 175 | -- CLK |
|
175 | -- CLK | |
| 176 | ----------------------------------------------------------------------------- |
|
176 | ----------------------------------------------------------------------------- | |
| 177 |
|
177 | |||
| 178 | PROCESS(clk_50) |
|
178 | PROCESS(clk_50) | |
| 179 | BEGIN |
|
179 | BEGIN | |
| 180 | IF clk_50'EVENT AND clk_50 = '1' THEN |
|
180 | IF clk_50'EVENT AND clk_50 = '1' THEN | |
| 181 | clk_50_s <= NOT clk_50_s; |
|
181 | clk_50_s <= NOT clk_50_s; | |
| 182 | END IF; |
|
182 | END IF; | |
| 183 | END PROCESS; |
|
183 | END PROCESS; | |
| 184 |
|
184 | |||
| 185 | PROCESS(clk_50_s) |
|
185 | PROCESS(clk_50_s) | |
| 186 | BEGIN |
|
186 | BEGIN | |
| 187 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
|
187 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |
| 188 | clk_25 <= NOT clk_25; |
|
188 | clk_25 <= NOT clk_25; | |
| 189 | END IF; |
|
189 | END IF; | |
| 190 | END PROCESS; |
|
190 | END PROCESS; | |
| 191 |
|
191 | |||
| 192 | ----------------------------------------------------------------------------- |
|
192 | ----------------------------------------------------------------------------- | |
| 193 |
|
193 | |||
| 194 | PROCESS (clk_25, reset) |
|
194 | PROCESS (clk_25, reset) | |
| 195 | BEGIN -- PROCESS |
|
195 | BEGIN -- PROCESS | |
| 196 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
196 | IF reset = '0' THEN -- asynchronous reset (active low) | |
| 197 | LED0 <= '0'; |
|
197 | LED0 <= '0'; | |
| 198 | LED1 <= '0'; |
|
198 | LED1 <= '0'; | |
| 199 | LED2 <= '0'; |
|
199 | LED2 <= '0'; | |
| 200 | --IO1 <= '0'; |
|
200 | --IO1 <= '0'; | |
| 201 | --IO2 <= '1'; |
|
201 | --IO2 <= '1'; | |
| 202 | --IO3 <= '0'; |
|
202 | --IO3 <= '0'; | |
| 203 | --IO4 <= '0'; |
|
203 | --IO4 <= '0'; | |
| 204 | --IO5 <= '0'; |
|
204 | --IO5 <= '0'; | |
| 205 | --IO6 <= '0'; |
|
205 | --IO6 <= '0'; | |
| 206 | --IO7 <= '0'; |
|
206 | --IO7 <= '0'; | |
| 207 | --IO8 <= '0'; |
|
207 | --IO8 <= '0'; | |
| 208 | --IO9 <= '0'; |
|
208 | --IO9 <= '0'; | |
| 209 | --IO10 <= '0'; |
|
209 | --IO10 <= '0'; | |
| 210 | --IO11 <= '0'; |
|
210 | --IO11 <= '0'; | |
| 211 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
211 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
| 212 | LED0 <= '0'; |
|
212 | LED0 <= '0'; | |
| 213 | LED1 <= '1'; |
|
213 | LED1 <= '1'; | |
| 214 | LED2 <= BP0; |
|
214 | LED2 <= BP0; | |
| 215 | --IO1 <= '1'; |
|
215 | --IO1 <= '1'; | |
| 216 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
|
216 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; | |
| 217 | --IO3 <= ADC_SDO(0); |
|
217 | --IO3 <= ADC_SDO(0); | |
| 218 | --IO4 <= ADC_SDO(1); |
|
218 | --IO4 <= ADC_SDO(1); | |
| 219 | --IO5 <= ADC_SDO(2); |
|
219 | --IO5 <= ADC_SDO(2); | |
| 220 | --IO6 <= ADC_SDO(3); |
|
220 | --IO6 <= ADC_SDO(3); | |
| 221 | --IO7 <= ADC_SDO(4); |
|
221 | --IO7 <= ADC_SDO(4); | |
| 222 | --IO8 <= ADC_SDO(5); |
|
222 | --IO8 <= ADC_SDO(5); | |
| 223 | --IO9 <= ADC_SDO(6); |
|
223 | --IO9 <= ADC_SDO(6); | |
| 224 | --IO10 <= ADC_SDO(7); |
|
224 | --IO10 <= ADC_SDO(7); | |
| 225 | IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
225 | IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
| 226 | END IF; |
|
226 | END IF; | |
| 227 | END PROCESS; |
|
227 | END PROCESS; | |
| 228 |
|
228 | |||
| 229 | PROCESS (clk_49, reset) |
|
229 | PROCESS (clk_49, reset) | |
| 230 | BEGIN -- PROCESS |
|
230 | BEGIN -- PROCESS | |
| 231 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
231 | IF reset = '0' THEN -- asynchronous reset (active low) | |
| 232 | I00_s <= '0'; |
|
232 | I00_s <= '0'; | |
| 233 | ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge |
|
233 | ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge | |
| 234 | I00_s <= NOT I00_s; |
|
234 | I00_s <= NOT I00_s; | |
| 235 | END IF; |
|
235 | END IF; | |
| 236 | END PROCESS; |
|
236 | END PROCESS; | |
| 237 | -- IO0 <= I00_s; |
|
237 | -- IO0 <= I00_s; | |
| 238 |
|
238 | |||
| 239 | --UARTs |
|
239 | --UARTs | |
| 240 | nCTS1 <= '1'; |
|
240 | nCTS1 <= '1'; | |
| 241 | nCTS2 <= '1'; |
|
241 | nCTS2 <= '1'; | |
| 242 | nDCD2 <= '1'; |
|
242 | nDCD2 <= '1'; | |
| 243 |
|
243 | |||
| 244 | --EXT CONNECTOR |
|
244 | --EXT CONNECTOR | |
| 245 |
|
245 | |||
| 246 | --SPACE WIRE |
|
246 | --SPACE WIRE | |
| 247 |
|
247 | |||
| 248 | leon3_soc_1 : leon3_soc |
|
248 | leon3_soc_1 : leon3_soc | |
| 249 | GENERIC MAP ( |
|
249 | GENERIC MAP ( | |
| 250 | fabtech => apa3e, |
|
250 | fabtech => apa3e, | |
| 251 | memtech => apa3e, |
|
251 | memtech => apa3e, | |
| 252 | padtech => inferred, |
|
252 | padtech => inferred, | |
| 253 | clktech => inferred, |
|
253 | clktech => inferred, | |
| 254 | disas => 0, |
|
254 | disas => 0, | |
| 255 | dbguart => 0, |
|
255 | dbguart => 0, | |
| 256 | pclow => 2, |
|
256 | pclow => 2, | |
| 257 | clk_freq => 25000, |
|
257 | clk_freq => 25000, | |
| 258 | NB_CPU => 1, |
|
258 | NB_CPU => 1, | |
| 259 | ENABLE_FPU => 1, |
|
259 | ENABLE_FPU => 1, | |
| 260 | FPU_NETLIST => 0, |
|
260 | FPU_NETLIST => 0, | |
| 261 | ENABLE_DSU => 1, |
|
261 | ENABLE_DSU => 1, | |
| 262 | ENABLE_AHB_UART => 1, |
|
262 | ENABLE_AHB_UART => 1, | |
| 263 | ENABLE_APB_UART => 1, |
|
263 | ENABLE_APB_UART => 1, | |
| 264 | ENABLE_IRQMP => 1, |
|
264 | ENABLE_IRQMP => 1, | |
| 265 | ENABLE_GPT => 1, |
|
265 | ENABLE_GPT => 1, | |
| 266 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
266 | NB_AHB_MASTER => NB_AHB_MASTER, | |
| 267 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
267 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |
| 268 | NB_APB_SLAVE => NB_APB_SLAVE) |
|
268 | NB_APB_SLAVE => NB_APB_SLAVE) | |
| 269 | PORT MAP ( |
|
269 | PORT MAP ( | |
| 270 | clk => clk_25, |
|
270 | clk => clk_25, | |
| 271 | reset => reset, |
|
271 | reset => reset, | |
| 272 | errorn => errorn, |
|
272 | errorn => errorn, | |
| 273 | ahbrxd => TXD1, |
|
273 | ahbrxd => TXD1, | |
| 274 | ahbtxd => RXD1, |
|
274 | ahbtxd => RXD1, | |
| 275 | urxd1 => TXD2, |
|
275 | urxd1 => TXD2, | |
| 276 | utxd1 => RXD2, |
|
276 | utxd1 => RXD2, | |
| 277 | address => SRAM_A, |
|
277 | address => SRAM_A, | |
| 278 | data => SRAM_DQ, |
|
278 | data => SRAM_DQ, | |
| 279 | nSRAM_BE0 => SRAM_nBE(0), |
|
279 | nSRAM_BE0 => SRAM_nBE(0), | |
| 280 | nSRAM_BE1 => SRAM_nBE(1), |
|
280 | nSRAM_BE1 => SRAM_nBE(1), | |
| 281 | nSRAM_BE2 => SRAM_nBE(2), |
|
281 | nSRAM_BE2 => SRAM_nBE(2), | |
| 282 | nSRAM_BE3 => SRAM_nBE(3), |
|
282 | nSRAM_BE3 => SRAM_nBE(3), | |
| 283 | nSRAM_WE => SRAM_nWE, |
|
283 | nSRAM_WE => SRAM_nWE, | |
| 284 | nSRAM_CE => SRAM_CE, |
|
284 | nSRAM_CE => SRAM_CE, | |
| 285 | nSRAM_OE => SRAM_nOE, |
|
285 | nSRAM_OE => SRAM_nOE, | |
| 286 |
|
286 | |||
| 287 | apbi_ext => apbi_ext, |
|
287 | apbi_ext => apbi_ext, | |
| 288 | apbo_ext => apbo_ext, |
|
288 | apbo_ext => apbo_ext, | |
| 289 | ahbi_s_ext => ahbi_s_ext, |
|
289 | ahbi_s_ext => ahbi_s_ext, | |
| 290 | ahbo_s_ext => ahbo_s_ext, |
|
290 | ahbo_s_ext => ahbo_s_ext, | |
| 291 | ahbi_m_ext => ahbi_m_ext, |
|
291 | ahbi_m_ext => ahbi_m_ext, | |
| 292 | ahbo_m_ext => ahbo_m_ext); |
|
292 | ahbo_m_ext => ahbo_m_ext); | |
| 293 |
|
293 | |||
| 294 | ------------------------------------------------------------------------------- |
|
294 | ------------------------------------------------------------------------------- | |
| 295 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
295 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |
| 296 | ------------------------------------------------------------------------------- |
|
296 | ------------------------------------------------------------------------------- | |
| 297 | apb_lfr_time_management_1 : apb_lfr_time_management |
|
297 | apb_lfr_time_management_1 : apb_lfr_time_management | |
| 298 | GENERIC MAP ( |
|
298 | GENERIC MAP ( | |
| 299 | pindex => 6, |
|
299 | pindex => 6, | |
| 300 | paddr => 6, |
|
300 | paddr => 6, | |
| 301 | pmask => 16#fff#, |
|
301 | pmask => 16#fff#, | |
| 302 | pirq => 12) |
|
302 | pirq => 12) | |
| 303 | PORT MAP ( |
|
303 | PORT MAP ( | |
| 304 | clk25MHz => clk_25, |
|
304 | clk25MHz => clk_25, | |
| 305 | clk49_152MHz => clk_49, |
|
305 | clk49_152MHz => clk_49, | |
| 306 | resetn => reset, |
|
306 | resetn => reset, | |
| 307 | grspw_tick => swno.tickout, |
|
307 | grspw_tick => swno.tickout, | |
| 308 | apbi => apbi_ext, |
|
308 | apbi => apbi_ext, | |
| 309 | apbo => apbo_ext(6), |
|
309 | apbo => apbo_ext(6), | |
| 310 | coarse_time => coarse_time, |
|
310 | coarse_time => coarse_time, | |
| 311 | fine_time => fine_time); |
|
311 | fine_time => fine_time); | |
| 312 |
|
312 | |||
| 313 | ----------------------------------------------------------------------- |
|
313 | ----------------------------------------------------------------------- | |
| 314 | --- SpaceWire -------------------------------------------------------- |
|
314 | --- SpaceWire -------------------------------------------------------- | |
| 315 | ----------------------------------------------------------------------- |
|
315 | ----------------------------------------------------------------------- | |
| 316 |
|
316 | |||
| 317 | SPW_EN <= '1'; |
|
317 | SPW_EN <= '1'; | |
| 318 |
|
318 | |||
| 319 | spw_clk <= clk_50_s; |
|
319 | spw_clk <= clk_50_s; | |
| 320 | spw_rxtxclk <= spw_clk; |
|
320 | spw_rxtxclk <= spw_clk; | |
| 321 | spw_rxclkn <= NOT spw_rxtxclk; |
|
321 | spw_rxclkn <= NOT spw_rxtxclk; | |
| 322 |
|
322 | |||
| 323 | -- PADS for SPW1 |
|
323 | -- PADS for SPW1 | |
| 324 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
324 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |
| 325 | PORT MAP (SPW_NOM_DIN, dtmp(0)); |
|
325 | PORT MAP (SPW_NOM_DIN, dtmp(0)); | |
| 326 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
326 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |
| 327 | PORT MAP (SPW_NOM_SIN, stmp(0)); |
|
327 | PORT MAP (SPW_NOM_SIN, stmp(0)); | |
| 328 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
328 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |
| 329 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); |
|
329 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); | |
| 330 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
330 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |
| 331 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); |
|
331 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); | |
| 332 | -- PADS FOR SPW2 |
|
332 | -- PADS FOR SPW2 | |
| 333 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
333 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
| 334 | PORT MAP (SPW_RED_SIN, dtmp(1)); |
|
334 | PORT MAP (SPW_RED_SIN, dtmp(1)); | |
| 335 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
335 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
| 336 | PORT MAP (SPW_RED_DIN, stmp(1)); |
|
336 | PORT MAP (SPW_RED_DIN, stmp(1)); | |
| 337 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
337 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |
| 338 | PORT MAP (SPW_RED_DOUT, swno.d(1)); |
|
338 | PORT MAP (SPW_RED_DOUT, swno.d(1)); | |
| 339 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
339 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |
| 340 | PORT MAP (SPW_RED_SOUT, swno.s(1)); |
|
340 | PORT MAP (SPW_RED_SOUT, swno.s(1)); | |
| 341 |
|
341 | |||
| 342 | -- GRSPW PHY |
|
342 | -- GRSPW PHY | |
| 343 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
343 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |
| 344 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
344 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
| 345 | spw_phy0 : grspw_phy |
|
345 | spw_phy0 : grspw_phy | |
| 346 | GENERIC MAP( |
|
346 | GENERIC MAP( | |
| 347 | tech => apa3e, |
|
347 | tech => apa3e, | |
| 348 | rxclkbuftype => 1, |
|
348 | rxclkbuftype => 1, | |
| 349 | scantest => 0) |
|
349 | scantest => 0) | |
| 350 | PORT MAP( |
|
350 | PORT MAP( | |
| 351 | rxrst => swno.rxrst, |
|
351 | rxrst => swno.rxrst, | |
| 352 | di => dtmp(j), |
|
352 | di => dtmp(j), | |
| 353 | si => stmp(j), |
|
353 | si => stmp(j), | |
| 354 | rxclko => spw_rxclk(j), |
|
354 | rxclko => spw_rxclk(j), | |
| 355 | do => swni.d(j), |
|
355 | do => swni.d(j), | |
| 356 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
356 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
| 357 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
357 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
| 358 | END GENERATE spw_inputloop; |
|
358 | END GENERATE spw_inputloop; | |
| 359 |
|
359 | |||
| 360 | -- SPW core |
|
360 | -- SPW core | |
| 361 | sw0 : grspwm GENERIC MAP( |
|
361 | sw0 : grspwm GENERIC MAP( | |
| 362 | tech => apa3e, |
|
362 | tech => apa3e, | |
| 363 | hindex => 1, |
|
363 | hindex => 1, | |
| 364 | pindex => 5, |
|
364 | pindex => 5, | |
| 365 | paddr => 5, |
|
365 | paddr => 5, | |
| 366 | pirq => 11, |
|
366 | pirq => 11, | |
| 367 | sysfreq => 25000, -- CPU_FREQ |
|
367 | sysfreq => 25000, -- CPU_FREQ | |
| 368 | rmap => 1, |
|
368 | rmap => 1, | |
| 369 | rmapcrc => 1, |
|
369 | rmapcrc => 1, | |
| 370 | fifosize1 => 16, |
|
370 | fifosize1 => 16, | |
| 371 | fifosize2 => 16, |
|
371 | fifosize2 => 16, | |
| 372 | rxclkbuftype => 1, |
|
372 | rxclkbuftype => 1, | |
| 373 | rxunaligned => 0, |
|
373 | rxunaligned => 0, | |
| 374 | rmapbufs => 4, |
|
374 | rmapbufs => 4, | |
| 375 | ft => 0, |
|
375 | ft => 0, | |
| 376 | netlist => 0, |
|
376 | netlist => 0, | |
| 377 | ports => 2, |
|
377 | ports => 2, | |
| 378 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
378 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
| 379 | memtech => apa3e, |
|
379 | memtech => apa3e, | |
| 380 | destkey => 2, |
|
380 | destkey => 2, | |
| 381 | spwcore => 1 |
|
381 | spwcore => 1 | |
| 382 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
382 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
| 383 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
383 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
| 384 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
384 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
| 385 | ) |
|
385 | ) | |
| 386 | PORT MAP(reset, clk_25, spw_rxclk(0), |
|
386 | PORT MAP(reset, clk_25, spw_rxclk(0), | |
| 387 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
387 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |
| 388 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
388 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |
| 389 | swni, swno); |
|
389 | swni, swno); | |
| 390 |
|
390 | |||
| 391 | swni.tickin <= '0'; |
|
391 | swni.tickin <= '0'; | |
| 392 | swni.rmapen <= '1'; |
|
392 | swni.rmapen <= '1'; | |
| 393 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
393 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |
| 394 | swni.tickinraw <= '0'; |
|
394 | swni.tickinraw <= '0'; | |
| 395 | swni.timein <= (OTHERS => '0'); |
|
395 | swni.timein <= (OTHERS => '0'); | |
| 396 | swni.dcrstval <= (OTHERS => '0'); |
|
396 | swni.dcrstval <= (OTHERS => '0'); | |
| 397 | swni.timerrstval <= (OTHERS => '0'); |
|
397 | swni.timerrstval <= (OTHERS => '0'); | |
| 398 |
|
398 | |||
| 399 | ------------------------------------------------------------------------------- |
|
399 | ------------------------------------------------------------------------------- | |
| 400 | -- LFR ------------------------------------------------------------------------ |
|
400 | -- LFR ------------------------------------------------------------------------ | |
| 401 | ------------------------------------------------------------------------------- |
|
401 | ------------------------------------------------------------------------------- | |
| 402 | lpp_lfr_1 : lpp_lfr |
|
402 | lpp_lfr_1 : lpp_lfr | |
| 403 | GENERIC MAP ( |
|
403 | GENERIC MAP ( | |
| 404 | Mem_use => use_RAM, |
|
404 | Mem_use => use_RAM, | |
| 405 | nb_data_by_buffer_size => 32, |
|
405 | nb_data_by_buffer_size => 32, | |
| 406 | nb_word_by_buffer_size => 30, |
|
406 | nb_word_by_buffer_size => 30, | |
| 407 | nb_snapshot_param_size => 32, |
|
407 | nb_snapshot_param_size => 32, | |
| 408 | delta_vector_size => 32, |
|
408 | delta_vector_size => 32, | |
| 409 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
409 | delta_vector_size_f0_2 => 7, -- log2(96) | |
| 410 | pindex => 15, |
|
410 | pindex => 15, | |
| 411 | paddr => 15, |
|
411 | paddr => 15, | |
| 412 | pmask => 16#fff#, |
|
412 | pmask => 16#fff#, | |
| 413 | pirq_ms => 6, |
|
413 | pirq_ms => 6, | |
| 414 | pirq_wfp => 14, |
|
414 | pirq_wfp => 14, | |
| 415 | hindex => 2, |
|
415 | hindex => 2, | |
| 416 |
top_lfr_version => X"0000000 |
|
416 | top_lfr_version => X"0000000B") | |
| 417 | PORT MAP ( |
|
417 | PORT MAP ( | |
| 418 | clk => clk_25, |
|
418 | clk => clk_25, | |
| 419 | rstn => reset, |
|
419 | rstn => reset, | |
| 420 | sample_B => sample(2 DOWNTO 0), |
|
420 | sample_B => sample(2 DOWNTO 0), | |
| 421 | sample_E => sample(7 DOWNTO 3), |
|
421 | sample_E => sample(7 DOWNTO 3), | |
| 422 | sample_val => sample_val, |
|
422 | sample_val => sample_val, | |
| 423 | apbi => apbi_ext, |
|
423 | apbi => apbi_ext, | |
| 424 | apbo => apbo_ext(15), |
|
424 | apbo => apbo_ext(15), | |
| 425 | ahbi => ahbi_m_ext, |
|
425 | ahbi => ahbi_m_ext, | |
| 426 | ahbo => ahbo_m_ext(2), |
|
426 | ahbo => ahbo_m_ext(2), | |
| 427 | coarse_time => coarse_time, |
|
427 | coarse_time => coarse_time, | |
| 428 | fine_time => fine_time, |
|
428 | fine_time => fine_time, | |
| 429 | data_shaping_BW => bias_fail_sw_sig); |
|
429 | data_shaping_BW => bias_fail_sw_sig); | |
| 430 |
|
430 | |||
| 431 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
|
431 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 | |
| 432 | GENERIC MAP( |
|
432 | GENERIC MAP( | |
| 433 | ChannelCount => 8, |
|
433 | ChannelCount => 8, | |
| 434 | SampleNbBits => 14, |
|
434 | SampleNbBits => 14, | |
| 435 | ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63 |
|
435 | ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63 | |
| 436 | ncycle_cnv => 500) -- 49 152 000 / 98304 |
|
436 | ncycle_cnv => 500) -- 49 152 000 / 98304 | |
| 437 | PORT MAP ( |
|
437 | PORT MAP ( | |
| 438 | -- CONV |
|
438 | -- CONV | |
| 439 | cnv_clk => clk_49, |
|
439 | cnv_clk => clk_49, | |
| 440 | cnv_rstn => reset, |
|
440 | cnv_rstn => reset, | |
| 441 | cnv => ADC_nCS_sig, |
|
441 | cnv => ADC_nCS_sig, | |
| 442 | -- DATA |
|
442 | -- DATA | |
| 443 | clk => clk_25, |
|
443 | clk => clk_25, | |
| 444 | rstn => reset, |
|
444 | rstn => reset, | |
| 445 | sck => ADC_CLK_sig, |
|
445 | sck => ADC_CLK_sig, | |
| 446 | sdo => ADC_SDO_sig, |
|
446 | sdo => ADC_SDO_sig, | |
| 447 | -- SAMPLE |
|
447 | -- SAMPLE | |
| 448 | sample => sample, |
|
448 | sample => sample, | |
| 449 | sample_val => sample_val); |
|
449 | sample_val => sample_val); | |
| 450 |
|
450 | |||
| 451 | IO10 <= ADC_SDO_sig(5); |
|
451 | IO10 <= ADC_SDO_sig(5); | |
| 452 | IO9 <= ADC_SDO_sig(4); |
|
452 | IO9 <= ADC_SDO_sig(4); | |
| 453 | IO8 <= ADC_SDO_sig(3); |
|
453 | IO8 <= ADC_SDO_sig(3); | |
| 454 |
|
454 | |||
| 455 | ADC_nCS <= ADC_nCS_sig; |
|
455 | ADC_nCS <= ADC_nCS_sig; | |
| 456 | ADC_CLK <= ADC_CLK_sig; |
|
456 | ADC_CLK <= ADC_CLK_sig; | |
| 457 | ADC_SDO_sig <= ADC_SDO; |
|
457 | ADC_SDO_sig <= ADC_SDO; | |
| 458 |
|
458 | |||
| 459 | ---------------------------------------------------------------------- |
|
459 | ---------------------------------------------------------------------- | |
| 460 | --- GPIO ----------------------------------------------------------- |
|
460 | --- GPIO ----------------------------------------------------------- | |
| 461 | ---------------------------------------------------------------------- |
|
461 | ---------------------------------------------------------------------- | |
| 462 |
|
462 | |||
| 463 | grgpio0 : grgpio |
|
463 | grgpio0 : grgpio | |
| 464 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
464 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) | |
| 465 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
465 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); | |
| 466 |
|
466 | |||
| 467 | pio_pad_0 : iopad |
|
467 | pio_pad_0 : iopad | |
| 468 | GENERIC MAP (tech => CFG_PADTECH) |
|
468 | GENERIC MAP (tech => CFG_PADTECH) | |
| 469 | PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
|
469 | PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); | |
| 470 | pio_pad_1 : iopad |
|
470 | pio_pad_1 : iopad | |
| 471 | GENERIC MAP (tech => CFG_PADTECH) |
|
471 | GENERIC MAP (tech => CFG_PADTECH) | |
| 472 | PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); |
|
472 | PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); | |
| 473 | pio_pad_2 : iopad |
|
473 | pio_pad_2 : iopad | |
| 474 | GENERIC MAP (tech => CFG_PADTECH) |
|
474 | GENERIC MAP (tech => CFG_PADTECH) | |
| 475 | PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); |
|
475 | PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); | |
| 476 | pio_pad_3 : iopad |
|
476 | pio_pad_3 : iopad | |
| 477 | GENERIC MAP (tech => CFG_PADTECH) |
|
477 | GENERIC MAP (tech => CFG_PADTECH) | |
| 478 | PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); |
|
478 | PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); | |
| 479 | pio_pad_4 : iopad |
|
479 | pio_pad_4 : iopad | |
| 480 | GENERIC MAP (tech => CFG_PADTECH) |
|
480 | GENERIC MAP (tech => CFG_PADTECH) | |
| 481 | PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); |
|
481 | PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); | |
| 482 | pio_pad_5 : iopad |
|
482 | pio_pad_5 : iopad | |
| 483 | GENERIC MAP (tech => CFG_PADTECH) |
|
483 | GENERIC MAP (tech => CFG_PADTECH) | |
| 484 | PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); |
|
484 | PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); | |
| 485 | pio_pad_6 : iopad |
|
485 | pio_pad_6 : iopad | |
| 486 | GENERIC MAP (tech => CFG_PADTECH) |
|
486 | GENERIC MAP (tech => CFG_PADTECH) | |
| 487 | PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); |
|
487 | PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); | |
| 488 | pio_pad_7 : iopad |
|
488 | pio_pad_7 : iopad | |
| 489 | GENERIC MAP (tech => CFG_PADTECH) |
|
489 | GENERIC MAP (tech => CFG_PADTECH) | |
| 490 | PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); |
|
490 | PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); | |
| 491 |
|
491 | |||
| 492 | END beh; |
|
492 | END beh; | |
| @@ -1,136 +1,133 | |||||
| 1 |
|
1 | |||
| 2 | LIBRARY IEEE; |
|
2 | LIBRARY IEEE; | |
| 3 | USE IEEE.STD_LOGIC_1164.ALL; |
|
3 | USE IEEE.STD_LOGIC_1164.ALL; | |
| 4 | USE IEEE.NUMERIC_STD.ALL; |
|
4 | USE IEEE.NUMERIC_STD.ALL; | |
| 5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
| 6 | USE lpp.lpp_ad_conv.ALL; |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
| 7 | USE lpp.general_purpose.SYNC_FF; |
|
7 | USE lpp.general_purpose.SYNC_FF; | |
| 8 |
|
8 | |||
| 9 | ENTITY top_ad_conv_ADS7886_v2 IS |
|
9 | ENTITY top_ad_conv_ADS7886_v2 IS | |
| 10 | GENERIC( |
|
10 | GENERIC( | |
| 11 |
ChannelCount |
|
11 | ChannelCount : INTEGER := 8; | |
| 12 |
|
|
12 | SampleNbBits : INTEGER := 14; | |
| 13 |
ncycle_cnv_high : INTEGER := 40; |
|
13 | ncycle_cnv_high : INTEGER := 40; -- at least 32 cycles | |
| 14 | ncycle_cnv : INTEGER := 500); |
|
14 | ncycle_cnv : INTEGER := 500); | |
| 15 | PORT ( |
|
15 | PORT ( | |
| 16 |
|
|
16 | -- CONV | |
| 17 |
cnv_clk |
|
17 | cnv_clk : IN STD_LOGIC; | |
| 18 |
cnv_rstn |
|
18 | cnv_rstn : IN STD_LOGIC; | |
| 19 |
cnv |
|
19 | cnv : OUT STD_LOGIC; | |
| 20 |
|
|
20 | -- DATA | |
| 21 |
clk |
|
21 | clk : IN STD_LOGIC; | |
| 22 |
rstn |
|
22 | rstn : IN STD_LOGIC; | |
| 23 |
|
|
23 | sck : OUT STD_LOGIC; | |
| 24 |
|
|
24 | sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0); | |
| 25 |
|
|
25 | -- SAMPLE | |
| 26 | sample : OUT Samples14v(ChannelCount-1 DOWNTO 0); |
|
26 | sample : OUT Samples14v(ChannelCount-1 DOWNTO 0); | |
| 27 | sample_val : OUT STD_LOGIC |
|
27 | sample_val : OUT STD_LOGIC | |
| 28 | ); |
|
28 | ); | |
| 29 | END top_ad_conv_ADS7886_v2; |
|
29 | END top_ad_conv_ADS7886_v2; | |
| 30 |
|
30 | |||
| 31 | ARCHITECTURE ar_top_ad_conv_ADS7886_v2 OF top_ad_conv_ADS7886_v2 IS |
|
31 | ARCHITECTURE ar_top_ad_conv_ADS7886_v2 OF top_ad_conv_ADS7886_v2 IS | |
| 32 |
|
32 | |||
| 33 | SIGNAL cnv_cycle_counter : INTEGER; |
|
33 | SIGNAL cnv_cycle_counter : INTEGER; | |
| 34 | SIGNAL cnv_s : STD_LOGIC; |
|
34 | SIGNAL cnv_s : STD_LOGIC; | |
| 35 | SIGNAL cnv_sync : STD_LOGIC; |
|
35 | SIGNAL cnv_sync : STD_LOGIC; | |
| 36 |
SIGNAL cnv_sync_not |
|
36 | SIGNAL cnv_sync_not : STD_LOGIC; | |
| 37 |
|
37 | |||
| 38 |
SIGNAL sample_adc |
|
38 | SIGNAL sample_adc : Samples(ChannelCount-1 DOWNTO 0); | |
| 39 |
SIGNAL sample_val_adc |
|
39 | SIGNAL sample_val_adc : STD_LOGIC; | |
| 40 |
|
40 | |||
| 41 | BEGIN |
|
41 | BEGIN | |
| 42 |
|
42 | |||
| 43 |
|
43 | |||
| 44 | ----------------------------------------------------------------------------- |
|
44 | ----------------------------------------------------------------------------- | |
| 45 | -- CONV |
|
45 | -- CONV | |
| 46 | ----------------------------------------------------------------------------- |
|
46 | ----------------------------------------------------------------------------- | |
| 47 | PROCESS (cnv_clk, cnv_rstn) |
|
47 | PROCESS (cnv_clk, cnv_rstn) | |
| 48 | BEGIN -- PROCESS |
|
48 | BEGIN -- PROCESS | |
| 49 | IF cnv_rstn = '0' THEN -- asynchronous reset (active low) |
|
49 | IF cnv_rstn = '0' THEN -- asynchronous reset (active low) | |
| 50 | cnv_cycle_counter <= 0; |
|
50 | cnv_cycle_counter <= 0; | |
| 51 | cnv_s <= '0'; |
|
51 | cnv_s <= '0'; | |
| 52 | ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge |
|
52 | ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge | |
| 53 | -- IF cnv_run = '1' THEN |
|
53 | -- IF cnv_run = '1' THEN | |
| 54 | IF cnv_cycle_counter < ncycle_cnv THEN |
|
54 | IF cnv_cycle_counter < ncycle_cnv THEN | |
| 55 | cnv_cycle_counter <= cnv_cycle_counter +1; |
|
55 | cnv_cycle_counter <= cnv_cycle_counter +1; | |
| 56 | IF cnv_cycle_counter < ncycle_cnv_high THEN |
|
56 | IF cnv_cycle_counter < ncycle_cnv_high THEN | |
| 57 | cnv_s <= '1'; |
|
57 | cnv_s <= '1'; | |
| 58 | ELSE |
|
58 | ELSE | |
| 59 | cnv_s <= '0'; |
|
59 | cnv_s <= '0'; | |
| 60 | END IF; |
|
60 | END IF; | |
| 61 | ELSE |
|
61 | ELSE | |
| 62 | cnv_s <= '1'; |
|
62 | cnv_s <= '1'; | |
| 63 | cnv_cycle_counter <= 0; |
|
63 | cnv_cycle_counter <= 0; | |
| 64 | END IF; |
|
64 | END IF; | |
| 65 | --ELSE |
|
65 | --ELSE | |
| 66 | -- cnv_s <= '0'; |
|
66 | -- cnv_s <= '0'; | |
| 67 | -- cnv_cycle_counter <= 0; |
|
67 | -- cnv_cycle_counter <= 0; | |
| 68 | --END IF; |
|
68 | --END IF; | |
| 69 | END IF; |
|
69 | END IF; | |
| 70 | END PROCESS; |
|
70 | END PROCESS; | |
| 71 |
|
71 | |||
| 72 |
cnv |
|
72 | cnv <= NOT(cnv_s); | |
| 73 |
|
73 | |||
| 74 | ----------------------------------------------------------------------------- |
|
74 | ----------------------------------------------------------------------------- | |
| 75 | -- SYNC CNV |
|
75 | -- SYNC CNV | |
| 76 | ----------------------------------------------------------------------------- |
|
76 | ----------------------------------------------------------------------------- | |
| 77 |
|
77 | |||
| 78 | SYNC_FF_cnv : SYNC_FF |
|
78 | SYNC_FF_cnv : SYNC_FF | |
| 79 | GENERIC MAP ( |
|
79 | GENERIC MAP ( | |
| 80 | NB_FF_OF_SYNC => 2) |
|
80 | NB_FF_OF_SYNC => 2) | |
| 81 | PORT MAP ( |
|
81 | PORT MAP ( | |
| 82 | clk => clk, |
|
82 | clk => clk, | |
| 83 | rstn => rstn, |
|
83 | rstn => rstn, | |
| 84 |
A => cnv_s, |
|
84 | A => cnv_s, -- the data fetching begins immediately | |
| 85 | A_sync => cnv_sync); |
|
85 | A_sync => cnv_sync); | |
| 86 |
|
86 | |||
| 87 | ----------------------------------------------------------------------------- |
|
87 | ----------------------------------------------------------------------------- | |
| 88 |
|
88 | |||
| 89 |
cnv_sync_not |
|
89 | cnv_sync_not <= NOT(cnv_sync); | |
| 90 |
|
90 | |||
| 91 |
|
|
91 | ADS7886_drvr_v2_1 : ADS7886_drvr_v2 | |
| 92 |
|
|
92 | GENERIC MAP( | |
| 93 |
|
|
93 | ChannelCount => 8, | |
| 94 |
|
|
94 | NbBitsSamples => 16) | |
| 95 |
|
|
95 | PORT MAP( | |
| 96 |
|
|
96 | -- CONV -- | |
| 97 |
|
|
97 | cnv_clk => cnv_sync_not, | |
| 98 |
|
|
98 | cnv_rstn => rstn, | |
| 99 |
|
|
99 | -- DATA -- | |
| 100 |
|
|
100 | clk => clk, -- master clock, 25 MHz | |
| 101 | rstn => rstn, |
|
101 | rstn => rstn, | |
| 102 | sck => sck, |
|
102 | sck => sck, | |
| 103 | sdo => sdo, |
|
103 | sdo => sdo, | |
| 104 |
|
|
104 | -- SAMPLE -- | |
| 105 |
|
|
105 | sample => sample_adc, | |
| 106 |
|
|
106 | sample_val => sample_val_adc); | |
| 107 |
|
107 | |||
| 108 | PROCESS (clk, rstn) |
|
108 | PROCESS (clk, rstn) | |
| 109 | BEGIN -- PROCESS |
|
109 | BEGIN -- PROCESS | |
| 110 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
110 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
| 111 |
|
|
111 | FOR k IN 0 TO ChannelCount-1 LOOP | |
| 112 |
|
|
112 | sample(k)(13 DOWNTO 0) <= (OTHERS => '0'); | |
| 113 |
|
|
113 | END LOOP; | |
| 114 |
|
|
114 | sample_val <= '0'; | |
| 115 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
115 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
| 116 |
|
|
116 | IF sample_val_adc = '1' THEN | |
| 117 |
|
|
117 | FOR k IN 0 TO ChannelCount-1 LOOP | |
| 118 |
|
|
118 | IF (UNSIGNED(sample_adc(k)(11 DOWNTO 0)) >= 2048) THEN | |
| 119 |
|
|
119 | sample(k)(13 DOWNTO 0) <= "00" & | |
| 120 |
|
|
120 | STD_LOGIC_VECTOR(UNSIGNED(sample_adc(k)(11 DOWNTO 0)) - 2048); | |
| 121 |
|
|
121 | ELSE | |
| 122 |
|
|
122 | sample(k)(13 DOWNTO 0) <= "11" & | |
| 123 |
|
|
123 | STD_LOGIC_VECTOR(UNSIGNED(sample_adc(k)(11 DOWNTO 0)) - 2048); | |
| 124 |
|
|
124 | END IF; | |
| 125 |
|
|
125 | END LOOP; | |
| 126 | -- FOR k IN 0 TO ChannelCount-1 LOOP |
|
126 | sample_val <= sample_val_adc; | |
| 127 | -- sample(k) <= sample_adc(k)(13 downto 0); |
|
127 | ELSE | |
| 128 | -- END LOOP; |
|
128 | sample_val <= '0'; | |
| 129 | sample_val <= sample_val_adc; |
|
129 | END IF; | |
| 130 | ELSE |
|
|||
| 131 | sample_val <= '0'; |
|
|||
| 132 | END IF; |
|
|||
| 133 | END IF; |
|
130 | END IF; | |
| 134 | END PROCESS; |
|
131 | END PROCESS; | |
| 135 |
|
132 | |||
| 136 | END ar_top_ad_conv_ADS7886_v2; No newline at end of file |
|
133 | END ar_top_ad_conv_ADS7886_v2; | |
| @@ -1,708 +1,714 | |||||
| 1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
| 2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
| 3 | USE ieee.numeric_std.ALL; |
|
3 | USE ieee.numeric_std.ALL; | |
| 4 |
|
4 | |||
| 5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
| 6 | USE lpp.lpp_ad_conv.ALL; |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
| 7 | USE lpp.iir_filter.ALL; |
|
7 | USE lpp.iir_filter.ALL; | |
| 8 | USE lpp.FILTERcfg.ALL; |
|
8 | USE lpp.FILTERcfg.ALL; | |
| 9 | USE lpp.lpp_memory.ALL; |
|
9 | USE lpp.lpp_memory.ALL; | |
| 10 | USE lpp.lpp_waveform_pkg.ALL; |
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |
| 11 | USE lpp.lpp_dma_pkg.ALL; |
|
11 | USE lpp.lpp_dma_pkg.ALL; | |
| 12 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
12 | USE lpp.lpp_top_lfr_pkg.ALL; | |
| 13 | USE lpp.lpp_lfr_pkg.ALL; |
|
13 | USE lpp.lpp_lfr_pkg.ALL; | |
| 14 | USE lpp.general_purpose.ALL; |
|
14 | USE lpp.general_purpose.ALL; | |
| 15 |
|
15 | |||
| 16 | LIBRARY techmap; |
|
16 | LIBRARY techmap; | |
| 17 | USE techmap.gencomp.ALL; |
|
17 | USE techmap.gencomp.ALL; | |
| 18 |
|
18 | |||
| 19 | LIBRARY grlib; |
|
19 | LIBRARY grlib; | |
| 20 | USE grlib.amba.ALL; |
|
20 | USE grlib.amba.ALL; | |
| 21 | USE grlib.stdlib.ALL; |
|
21 | USE grlib.stdlib.ALL; | |
| 22 | USE grlib.devices.ALL; |
|
22 | USE grlib.devices.ALL; | |
| 23 | USE GRLIB.DMA2AHB_Package.ALL; |
|
23 | USE GRLIB.DMA2AHB_Package.ALL; | |
| 24 |
|
24 | |||
| 25 | ENTITY lpp_lfr IS |
|
25 | ENTITY lpp_lfr IS | |
| 26 | GENERIC ( |
|
26 | GENERIC ( | |
| 27 | Mem_use : INTEGER := use_RAM; |
|
27 | Mem_use : INTEGER := use_RAM; | |
| 28 | nb_data_by_buffer_size : INTEGER := 11; |
|
28 | nb_data_by_buffer_size : INTEGER := 11; | |
| 29 | nb_word_by_buffer_size : INTEGER := 11; |
|
29 | nb_word_by_buffer_size : INTEGER := 11; | |
| 30 | nb_snapshot_param_size : INTEGER := 11; |
|
30 | nb_snapshot_param_size : INTEGER := 11; | |
| 31 | delta_vector_size : INTEGER := 20; |
|
31 | delta_vector_size : INTEGER := 20; | |
| 32 | delta_vector_size_f0_2 : INTEGER := 7; |
|
32 | delta_vector_size_f0_2 : INTEGER := 7; | |
| 33 |
|
33 | |||
| 34 | pindex : INTEGER := 4; |
|
34 | pindex : INTEGER := 4; | |
| 35 | paddr : INTEGER := 4; |
|
35 | paddr : INTEGER := 4; | |
| 36 | pmask : INTEGER := 16#fff#; |
|
36 | pmask : INTEGER := 16#fff#; | |
| 37 | pirq_ms : INTEGER := 0; |
|
37 | pirq_ms : INTEGER := 0; | |
| 38 | pirq_wfp : INTEGER := 1; |
|
38 | pirq_wfp : INTEGER := 1; | |
| 39 |
|
39 | |||
| 40 | hindex : INTEGER := 2; |
|
40 | hindex : INTEGER := 2; | |
| 41 |
|
41 | |||
| 42 | top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0') |
|
42 | top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0') | |
| 43 |
|
43 | |||
| 44 | ); |
|
44 | ); | |
| 45 | PORT ( |
|
45 | PORT ( | |
| 46 | clk : IN STD_LOGIC; |
|
46 | clk : IN STD_LOGIC; | |
| 47 | rstn : IN STD_LOGIC; |
|
47 | rstn : IN STD_LOGIC; | |
| 48 | -- SAMPLE |
|
48 | -- SAMPLE | |
| 49 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
49 | sample_B : IN Samples14v(2 DOWNTO 0); | |
| 50 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
50 | sample_E : IN Samples14v(4 DOWNTO 0); | |
| 51 | sample_val : IN STD_LOGIC; |
|
51 | sample_val : IN STD_LOGIC; | |
| 52 | -- APB |
|
52 | -- APB | |
| 53 | apbi : IN apb_slv_in_type; |
|
53 | apbi : IN apb_slv_in_type; | |
| 54 | apbo : OUT apb_slv_out_type; |
|
54 | apbo : OUT apb_slv_out_type; | |
| 55 | -- AHB |
|
55 | -- AHB | |
| 56 | ahbi : IN AHB_Mst_In_Type; |
|
56 | ahbi : IN AHB_Mst_In_Type; | |
| 57 | ahbo : OUT AHB_Mst_Out_Type; |
|
57 | ahbo : OUT AHB_Mst_Out_Type; | |
| 58 | -- TIME |
|
58 | -- TIME | |
| 59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
| 60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
| 61 | -- |
|
61 | -- | |
| 62 | data_shaping_BW : OUT STD_LOGIC; |
|
62 | data_shaping_BW : OUT STD_LOGIC; | |
| 63 |
|
63 | |||
| 64 | --debug |
|
64 | --debug | |
| 65 | debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
65 | debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
| 66 | debug_f0_data_valid : OUT STD_LOGIC; |
|
66 | debug_f0_data_valid : OUT STD_LOGIC; | |
| 67 | debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
67 | debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
| 68 | debug_f1_data_valid : OUT STD_LOGIC; |
|
68 | debug_f1_data_valid : OUT STD_LOGIC; | |
| 69 | debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
69 | debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
| 70 | debug_f2_data_valid : OUT STD_LOGIC; |
|
70 | debug_f2_data_valid : OUT STD_LOGIC; | |
| 71 | debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
71 | debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
| 72 | debug_f3_data_valid : OUT STD_LOGIC; |
|
72 | debug_f3_data_valid : OUT STD_LOGIC; | |
| 73 |
|
73 | |||
| 74 | -- debug FIFO_IN |
|
74 | -- debug FIFO_IN | |
| 75 | debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
75 | debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 76 | debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
|
76 | debug_f0_data_fifo_in_valid : OUT STD_LOGIC; | |
| 77 | debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
77 | debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 78 | debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
|
78 | debug_f1_data_fifo_in_valid : OUT STD_LOGIC; | |
| 79 | debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 80 | debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
|
80 | debug_f2_data_fifo_in_valid : OUT STD_LOGIC; | |
| 81 | debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
81 | debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 82 | debug_f3_data_fifo_in_valid : OUT STD_LOGIC; |
|
82 | debug_f3_data_fifo_in_valid : OUT STD_LOGIC; | |
| 83 |
|
83 | |||
| 84 | --debug FIFO OUT |
|
84 | --debug FIFO OUT | |
| 85 | debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
85 | debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 86 | debug_f0_data_fifo_out_valid : OUT STD_LOGIC; |
|
86 | debug_f0_data_fifo_out_valid : OUT STD_LOGIC; | |
| 87 | debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
87 | debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 88 | debug_f1_data_fifo_out_valid : OUT STD_LOGIC; |
|
88 | debug_f1_data_fifo_out_valid : OUT STD_LOGIC; | |
| 89 | debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
89 | debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 90 | debug_f2_data_fifo_out_valid : OUT STD_LOGIC; |
|
90 | debug_f2_data_fifo_out_valid : OUT STD_LOGIC; | |
| 91 | debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 92 | debug_f3_data_fifo_out_valid : OUT STD_LOGIC; |
|
92 | debug_f3_data_fifo_out_valid : OUT STD_LOGIC; | |
| 93 |
|
93 | |||
| 94 | --debug DMA IN |
|
94 | --debug DMA IN | |
| 95 | debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
95 | debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 96 | debug_f0_data_dma_in_valid : OUT STD_LOGIC; |
|
96 | debug_f0_data_dma_in_valid : OUT STD_LOGIC; | |
| 97 | debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
97 | debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 98 | debug_f1_data_dma_in_valid : OUT STD_LOGIC; |
|
98 | debug_f1_data_dma_in_valid : OUT STD_LOGIC; | |
| 99 | debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
99 | debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 100 | debug_f2_data_dma_in_valid : OUT STD_LOGIC; |
|
100 | debug_f2_data_dma_in_valid : OUT STD_LOGIC; | |
| 101 | debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
101 | debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 102 | debug_f3_data_dma_in_valid : OUT STD_LOGIC |
|
102 | debug_f3_data_dma_in_valid : OUT STD_LOGIC | |
| 103 | ); |
|
103 | ); | |
| 104 | END lpp_lfr; |
|
104 | END lpp_lfr; | |
| 105 |
|
105 | |||
| 106 | ARCHITECTURE beh OF lpp_lfr IS |
|
106 | ARCHITECTURE beh OF lpp_lfr IS | |
| 107 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
107 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
| 108 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
108 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
| 109 | -- |
|
109 | -- | |
| 110 | SIGNAL data_shaping_SP0 : STD_LOGIC; |
|
110 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |
| 111 | SIGNAL data_shaping_SP1 : STD_LOGIC; |
|
111 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |
| 112 | SIGNAL data_shaping_R0 : STD_LOGIC; |
|
112 | SIGNAL data_shaping_R0 : STD_LOGIC; | |
| 113 | SIGNAL data_shaping_R1 : STD_LOGIC; |
|
113 | SIGNAL data_shaping_R1 : STD_LOGIC; | |
| 114 | -- |
|
114 | -- | |
| 115 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
115 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 116 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
116 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 117 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
117 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 118 | -- |
|
118 | -- | |
| 119 | SIGNAL sample_f0_val : STD_LOGIC; |
|
119 | SIGNAL sample_f0_val : STD_LOGIC; | |
| 120 | SIGNAL sample_f1_val : STD_LOGIC; |
|
120 | SIGNAL sample_f1_val : STD_LOGIC; | |
| 121 | SIGNAL sample_f2_val : STD_LOGIC; |
|
121 | SIGNAL sample_f2_val : STD_LOGIC; | |
| 122 | SIGNAL sample_f3_val : STD_LOGIC; |
|
122 | SIGNAL sample_f3_val : STD_LOGIC; | |
| 123 | -- |
|
123 | -- | |
| 124 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
124 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 125 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
125 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 126 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
126 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 127 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
127 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 128 | -- |
|
128 | -- | |
| 129 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
129 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 130 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
130 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 131 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
131 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 132 |
|
132 | |||
| 133 | -- SM |
|
133 | -- SM | |
| 134 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; |
|
134 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; | |
| 135 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
135 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
| 136 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
136 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |
| 137 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
137 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |
| 138 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
138 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
| 139 | SIGNAL error_bad_component_error : STD_LOGIC; |
|
139 | SIGNAL error_bad_component_error : STD_LOGIC; | |
| 140 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
140 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 141 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; |
|
141 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; | |
| 142 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
142 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
| 143 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
143 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |
| 144 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
144 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |
| 145 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
|
145 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |
| 146 | SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
146 | SIGNAL status_error_bad_component_error : STD_LOGIC; | |
| 147 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
|
147 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |
| 148 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
148 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |
| 149 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
149 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 150 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
150 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 151 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
151 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 152 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
152 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 153 |
|
153 | |||
| 154 | -- WFP |
|
154 | -- WFP | |
| 155 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
155 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 156 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
156 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 157 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
157 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 158 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
158 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 159 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
159 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
| 160 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
160 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
| 161 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
161 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
| 162 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
162 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
| 163 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
163 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
| 164 |
|
164 | |||
| 165 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
165 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
| 166 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
166 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
| 167 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
167 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
| 168 | SIGNAL enable_f0 : STD_LOGIC; |
|
168 | SIGNAL enable_f0 : STD_LOGIC; | |
| 169 | SIGNAL enable_f1 : STD_LOGIC; |
|
169 | SIGNAL enable_f1 : STD_LOGIC; | |
| 170 | SIGNAL enable_f2 : STD_LOGIC; |
|
170 | SIGNAL enable_f2 : STD_LOGIC; | |
| 171 | SIGNAL enable_f3 : STD_LOGIC; |
|
171 | SIGNAL enable_f3 : STD_LOGIC; | |
| 172 | SIGNAL burst_f0 : STD_LOGIC; |
|
172 | SIGNAL burst_f0 : STD_LOGIC; | |
| 173 | SIGNAL burst_f1 : STD_LOGIC; |
|
173 | SIGNAL burst_f1 : STD_LOGIC; | |
| 174 | SIGNAL burst_f2 : STD_LOGIC; |
|
174 | SIGNAL burst_f2 : STD_LOGIC; | |
| 175 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
175 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 176 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
176 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 177 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
177 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 178 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
178 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 179 |
|
179 | |||
| 180 | SIGNAL run : STD_LOGIC; |
|
180 | SIGNAL run : STD_LOGIC; | |
| 181 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
181 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
| 182 |
|
182 | |||
| 183 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
183 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 184 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
184 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 185 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
|
185 | SIGNAL data_f0_data_out_valid : STD_LOGIC; | |
| 186 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
|
186 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; | |
| 187 | SIGNAL data_f0_data_out_ren : STD_LOGIC; |
|
187 | SIGNAL data_f0_data_out_ren : STD_LOGIC; | |
| 188 | --f1 |
|
188 | --f1 | |
| 189 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
189 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 190 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
190 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 191 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
|
191 | SIGNAL data_f1_data_out_valid : STD_LOGIC; | |
| 192 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
|
192 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; | |
| 193 | SIGNAL data_f1_data_out_ren : STD_LOGIC; |
|
193 | SIGNAL data_f1_data_out_ren : STD_LOGIC; | |
| 194 | --f2 |
|
194 | --f2 | |
| 195 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
195 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 196 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
196 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 197 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
|
197 | SIGNAL data_f2_data_out_valid : STD_LOGIC; | |
| 198 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
|
198 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; | |
| 199 | SIGNAL data_f2_data_out_ren : STD_LOGIC; |
|
199 | SIGNAL data_f2_data_out_ren : STD_LOGIC; | |
| 200 | --f3 |
|
200 | --f3 | |
| 201 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
201 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 202 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
202 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 203 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
|
203 | SIGNAL data_f3_data_out_valid : STD_LOGIC; | |
| 204 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
|
204 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; | |
| 205 | SIGNAL data_f3_data_out_ren : STD_LOGIC; |
|
205 | SIGNAL data_f3_data_out_ren : STD_LOGIC; | |
| 206 |
|
206 | |||
| 207 | ----------------------------------------------------------------------------- |
|
207 | ----------------------------------------------------------------------------- | |
| 208 | -- |
|
208 | -- | |
| 209 | ----------------------------------------------------------------------------- |
|
209 | ----------------------------------------------------------------------------- | |
| 210 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
210 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 211 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; |
|
211 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; | |
| 212 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; |
|
212 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; | |
| 213 | --f1 |
|
213 | --f1 | |
| 214 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
214 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 215 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; |
|
215 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; | |
| 216 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; |
|
216 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; | |
| 217 | --f2 |
|
217 | --f2 | |
| 218 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
218 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 219 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; |
|
219 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; | |
| 220 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; |
|
220 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; | |
| 221 | --f3 |
|
221 | --f3 | |
| 222 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
222 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 223 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; |
|
223 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; | |
| 224 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; |
|
224 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; | |
| 225 |
|
225 | |||
| 226 | ----------------------------------------------------------------------------- |
|
226 | ----------------------------------------------------------------------------- | |
| 227 | -- DMA RR |
|
227 | -- DMA RR | |
| 228 | ----------------------------------------------------------------------------- |
|
228 | ----------------------------------------------------------------------------- | |
| 229 | SIGNAL dma_sel_valid : STD_LOGIC; |
|
229 | SIGNAL dma_sel_valid : STD_LOGIC; | |
| 230 | SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
230 | SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 231 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
231 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 232 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
232 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 233 |
|
233 | |||
| 234 | ----------------------------------------------------------------------------- |
|
234 | ----------------------------------------------------------------------------- | |
| 235 | -- DMA_REG |
|
235 | -- DMA_REG | |
| 236 | ----------------------------------------------------------------------------- |
|
236 | ----------------------------------------------------------------------------- | |
| 237 | SIGNAL ongoing_reg : STD_LOGIC; |
|
237 | SIGNAL ongoing_reg : STD_LOGIC; | |
| 238 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
238 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 239 | SIGNAL dma_send_reg : STD_LOGIC; |
|
239 | SIGNAL dma_send_reg : STD_LOGIC; | |
| 240 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
240 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
| 241 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
241 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 242 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
242 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 243 |
|
243 | |||
| 244 |
|
244 | |||
| 245 | ----------------------------------------------------------------------------- |
|
245 | ----------------------------------------------------------------------------- | |
| 246 | -- DMA |
|
246 | -- DMA | |
| 247 | ----------------------------------------------------------------------------- |
|
247 | ----------------------------------------------------------------------------- | |
| 248 | SIGNAL dma_send : STD_LOGIC; |
|
248 | SIGNAL dma_send : STD_LOGIC; | |
| 249 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
249 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
| 250 | SIGNAL dma_done : STD_LOGIC; |
|
250 | SIGNAL dma_done : STD_LOGIC; | |
| 251 | SIGNAL dma_ren : STD_LOGIC; |
|
251 | SIGNAL dma_ren : STD_LOGIC; | |
| 252 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
252 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 253 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
253 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 254 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
254 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 255 |
|
255 | |||
| 256 | ----------------------------------------------------------------------------- |
|
256 | ----------------------------------------------------------------------------- | |
| 257 | -- DEBUG |
|
257 | -- DEBUG | |
| 258 | ----------------------------------------------------------------------------- |
|
258 | ----------------------------------------------------------------------------- | |
| 259 | -- |
|
259 | -- | |
| 260 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
260 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 261 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
261 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 262 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
262 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 263 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
263 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 264 |
|
264 | |||
| 265 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
265 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 266 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
266 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 267 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
267 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 268 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
268 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 269 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
269 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 270 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
270 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 271 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
271 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 272 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
272 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 273 |
|
273 | |||
| 274 | BEGIN |
|
274 | BEGIN | |
| 275 |
|
275 | |||
| 276 | sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
|
276 | sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |
| 277 | sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
|
277 | sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); | |
| 278 |
|
278 | |||
| 279 | all_channel : FOR i IN 7 DOWNTO 0 GENERATE |
|
279 | all_channel : FOR i IN 7 DOWNTO 0 GENERATE | |
| 280 | sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); |
|
280 | sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); | |
| 281 | END GENERATE all_channel; |
|
281 | END GENERATE all_channel; | |
| 282 |
|
282 | |||
| 283 | ----------------------------------------------------------------------------- |
|
283 | ----------------------------------------------------------------------------- | |
| 284 | lpp_lfr_filter_1 : lpp_lfr_filter |
|
284 | lpp_lfr_filter_1 : lpp_lfr_filter | |
| 285 | GENERIC MAP ( |
|
285 | GENERIC MAP ( | |
| 286 | Mem_use => Mem_use) |
|
286 | Mem_use => Mem_use) | |
| 287 | PORT MAP ( |
|
287 | PORT MAP ( | |
| 288 | sample => sample_s, |
|
288 | sample => sample_s, | |
| 289 | sample_val => sample_val, |
|
289 | sample_val => sample_val, | |
| 290 | clk => clk, |
|
290 | clk => clk, | |
| 291 | rstn => rstn, |
|
291 | rstn => rstn, | |
| 292 | data_shaping_SP0 => data_shaping_SP0, |
|
292 | data_shaping_SP0 => data_shaping_SP0, | |
| 293 | data_shaping_SP1 => data_shaping_SP1, |
|
293 | data_shaping_SP1 => data_shaping_SP1, | |
| 294 | data_shaping_R0 => data_shaping_R0, |
|
294 | data_shaping_R0 => data_shaping_R0, | |
| 295 | data_shaping_R1 => data_shaping_R1, |
|
295 | data_shaping_R1 => data_shaping_R1, | |
| 296 | sample_f0_val => sample_f0_val, |
|
296 | sample_f0_val => sample_f0_val, | |
| 297 | sample_f1_val => sample_f1_val, |
|
297 | sample_f1_val => sample_f1_val, | |
| 298 | sample_f2_val => sample_f2_val, |
|
298 | sample_f2_val => sample_f2_val, | |
| 299 | sample_f3_val => sample_f3_val, |
|
299 | sample_f3_val => sample_f3_val, | |
| 300 | sample_f0_wdata => sample_f0_data, |
|
300 | sample_f0_wdata => sample_f0_data, | |
| 301 | sample_f1_wdata => sample_f1_data, |
|
301 | sample_f1_wdata => sample_f1_data, | |
| 302 | sample_f2_wdata => sample_f2_data, |
|
302 | sample_f2_wdata => sample_f2_data, | |
| 303 | sample_f3_wdata => sample_f3_data); |
|
303 | sample_f3_wdata => sample_f3_data); | |
| 304 |
|
304 | |||
| 305 | ----------------------------------------------------------------------------- |
|
305 | ----------------------------------------------------------------------------- | |
| 306 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
|
306 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg | |
| 307 | GENERIC MAP ( |
|
307 | GENERIC MAP ( | |
| 308 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
308 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
| 309 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
309 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
| 310 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
310 | nb_snapshot_param_size => nb_snapshot_param_size, | |
| 311 | delta_vector_size => delta_vector_size, |
|
311 | delta_vector_size => delta_vector_size, | |
| 312 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
|
312 | delta_vector_size_f0_2 => delta_vector_size_f0_2, | |
| 313 | pindex => pindex, |
|
313 | pindex => pindex, | |
| 314 | paddr => paddr, |
|
314 | paddr => paddr, | |
| 315 | pmask => pmask, |
|
315 | pmask => pmask, | |
| 316 | pirq_ms => pirq_ms, |
|
316 | pirq_ms => pirq_ms, | |
| 317 | pirq_wfp => pirq_wfp, |
|
317 | pirq_wfp => pirq_wfp, | |
| 318 | top_lfr_version => top_lfr_version) |
|
318 | top_lfr_version => top_lfr_version) | |
| 319 | PORT MAP ( |
|
319 | PORT MAP ( | |
| 320 | HCLK => clk, |
|
320 | HCLK => clk, | |
| 321 | HRESETn => rstn, |
|
321 | HRESETn => rstn, | |
| 322 | apbi => apbi, |
|
322 | apbi => apbi, | |
| 323 | apbo => apbo, |
|
323 | apbo => apbo, | |
| 324 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
324 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
| 325 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
325 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
| 326 | ready_matrix_f1 => ready_matrix_f1, |
|
326 | ready_matrix_f1 => ready_matrix_f1, | |
| 327 | ready_matrix_f2 => ready_matrix_f2, |
|
327 | ready_matrix_f2 => ready_matrix_f2, | |
| 328 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
328 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
| 329 | error_bad_component_error => error_bad_component_error, |
|
329 | error_bad_component_error => error_bad_component_error, | |
| 330 | debug_reg => debug_reg, |
|
330 | debug_reg => debug_reg, | |
| 331 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
331 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
| 332 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
332 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
| 333 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
333 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
| 334 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
334 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
| 335 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
335 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
| 336 | status_error_bad_component_error => status_error_bad_component_error, |
|
336 | status_error_bad_component_error => status_error_bad_component_error, | |
| 337 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
337 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
| 338 | config_active_interruption_onError => config_active_interruption_onError, |
|
338 | config_active_interruption_onError => config_active_interruption_onError, | |
| 339 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
339 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
| 340 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
340 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
| 341 | addr_matrix_f1 => addr_matrix_f1, |
|
341 | addr_matrix_f1 => addr_matrix_f1, | |
| 342 | addr_matrix_f2 => addr_matrix_f2, |
|
342 | addr_matrix_f2 => addr_matrix_f2, | |
| 343 | status_full => status_full, |
|
343 | status_full => status_full, | |
| 344 | status_full_ack => status_full_ack, |
|
344 | status_full_ack => status_full_ack, | |
| 345 | status_full_err => status_full_err, |
|
345 | status_full_err => status_full_err, | |
| 346 | status_new_err => status_new_err, |
|
346 | status_new_err => status_new_err, | |
| 347 | data_shaping_BW => data_shaping_BW, |
|
347 | data_shaping_BW => data_shaping_BW, | |
| 348 | data_shaping_SP0 => data_shaping_SP0, |
|
348 | data_shaping_SP0 => data_shaping_SP0, | |
| 349 | data_shaping_SP1 => data_shaping_SP1, |
|
349 | data_shaping_SP1 => data_shaping_SP1, | |
| 350 | data_shaping_R0 => data_shaping_R0, |
|
350 | data_shaping_R0 => data_shaping_R0, | |
| 351 | data_shaping_R1 => data_shaping_R1, |
|
351 | data_shaping_R1 => data_shaping_R1, | |
| 352 | delta_snapshot => delta_snapshot, |
|
352 | delta_snapshot => delta_snapshot, | |
| 353 | delta_f0 => delta_f0, |
|
353 | delta_f0 => delta_f0, | |
| 354 | delta_f0_2 => delta_f0_2, |
|
354 | delta_f0_2 => delta_f0_2, | |
| 355 | delta_f1 => delta_f1, |
|
355 | delta_f1 => delta_f1, | |
| 356 | delta_f2 => delta_f2, |
|
356 | delta_f2 => delta_f2, | |
| 357 | nb_data_by_buffer => nb_data_by_buffer, |
|
357 | nb_data_by_buffer => nb_data_by_buffer, | |
| 358 | nb_word_by_buffer => nb_word_by_buffer, |
|
358 | nb_word_by_buffer => nb_word_by_buffer, | |
| 359 | nb_snapshot_param => nb_snapshot_param, |
|
359 | nb_snapshot_param => nb_snapshot_param, | |
| 360 | enable_f0 => enable_f0, |
|
360 | enable_f0 => enable_f0, | |
| 361 | enable_f1 => enable_f1, |
|
361 | enable_f1 => enable_f1, | |
| 362 | enable_f2 => enable_f2, |
|
362 | enable_f2 => enable_f2, | |
| 363 | enable_f3 => enable_f3, |
|
363 | enable_f3 => enable_f3, | |
| 364 | burst_f0 => burst_f0, |
|
364 | burst_f0 => burst_f0, | |
| 365 | burst_f1 => burst_f1, |
|
365 | burst_f1 => burst_f1, | |
| 366 | burst_f2 => burst_f2, |
|
366 | burst_f2 => burst_f2, | |
| 367 | run => run, |
|
367 | run => run, | |
| 368 | addr_data_f0 => addr_data_f0, |
|
368 | addr_data_f0 => addr_data_f0, | |
| 369 | addr_data_f1 => addr_data_f1, |
|
369 | addr_data_f1 => addr_data_f1, | |
| 370 | addr_data_f2 => addr_data_f2, |
|
370 | addr_data_f2 => addr_data_f2, | |
| 371 | addr_data_f3 => addr_data_f3, |
|
371 | addr_data_f3 => addr_data_f3, | |
| 372 | start_date => start_date, |
|
372 | start_date => start_date, | |
| 373 | --------------------------------------------------------------------------- |
|
373 | --------------------------------------------------------------------------- | |
| 374 | debug_reg0 => debug_reg0, |
|
374 | debug_reg0 => debug_reg0, | |
| 375 | debug_reg1 => debug_reg1, |
|
375 | debug_reg1 => debug_reg1, | |
| 376 | debug_reg2 => debug_reg2, |
|
376 | debug_reg2 => debug_reg2, | |
| 377 | debug_reg3 => debug_reg3, |
|
377 | debug_reg3 => debug_reg3, | |
| 378 | debug_reg4 => debug_reg4, |
|
378 | debug_reg4 => debug_reg4, | |
| 379 | debug_reg5 => debug_reg5, |
|
379 | debug_reg5 => debug_reg5, | |
| 380 | debug_reg6 => debug_reg6, |
|
380 | debug_reg6 => debug_reg6, | |
| 381 | debug_reg7 => debug_reg7); |
|
381 | debug_reg7 => debug_reg7); | |
| 382 |
|
382 | |||
| 383 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); |
|
383 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); | |
| 384 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); |
|
384 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); | |
| 385 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); |
|
385 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); | |
| 386 | ----------------------------------------------------------------------------- |
|
386 | ----------------------------------------------------------------------------- | |
| 387 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug |
|
387 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug | |
| 388 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug |
|
388 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug | |
| 389 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug |
|
389 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug | |
| 390 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug |
|
390 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug | |
| 391 |
|
391 | |||
| 392 |
|
392 | |||
| 393 | ----------------------------------------------------------------------------- |
|
393 | ----------------------------------------------------------------------------- | |
| 394 | lpp_waveform_1 : lpp_waveform |
|
394 | lpp_waveform_1 : lpp_waveform | |
| 395 | GENERIC MAP ( |
|
395 | GENERIC MAP ( | |
| 396 | tech => inferred, |
|
396 | tech => inferred, | |
| 397 | data_size => 6*16, |
|
397 | data_size => 6*16, | |
| 398 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
398 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
| 399 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
399 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
| 400 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
400 | nb_snapshot_param_size => nb_snapshot_param_size, | |
| 401 | delta_vector_size => delta_vector_size, |
|
401 | delta_vector_size => delta_vector_size, | |
| 402 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
|
402 | delta_vector_size_f0_2 => delta_vector_size_f0_2 | |
| 403 | ) |
|
403 | ) | |
| 404 | PORT MAP ( |
|
404 | PORT MAP ( | |
| 405 | clk => clk, |
|
405 | clk => clk, | |
| 406 | rstn => rstn, |
|
406 | rstn => rstn, | |
| 407 |
|
407 | |||
| 408 | reg_run => run, |
|
408 | reg_run => run, | |
| 409 | reg_start_date => start_date, |
|
409 | reg_start_date => start_date, | |
| 410 | reg_delta_snapshot => delta_snapshot, |
|
410 | reg_delta_snapshot => delta_snapshot, | |
| 411 | reg_delta_f0 => delta_f0, |
|
411 | reg_delta_f0 => delta_f0, | |
| 412 | reg_delta_f0_2 => delta_f0_2, |
|
412 | reg_delta_f0_2 => delta_f0_2, | |
| 413 | reg_delta_f1 => delta_f1, |
|
413 | reg_delta_f1 => delta_f1, | |
| 414 | reg_delta_f2 => delta_f2, |
|
414 | reg_delta_f2 => delta_f2, | |
| 415 |
|
415 | |||
| 416 | enable_f0 => enable_f0, |
|
416 | enable_f0 => enable_f0, | |
| 417 | enable_f1 => enable_f1, |
|
417 | enable_f1 => enable_f1, | |
| 418 | enable_f2 => enable_f2, |
|
418 | enable_f2 => enable_f2, | |
| 419 | enable_f3 => enable_f3, |
|
419 | enable_f3 => enable_f3, | |
| 420 | burst_f0 => burst_f0, |
|
420 | burst_f0 => burst_f0, | |
| 421 | burst_f1 => burst_f1, |
|
421 | burst_f1 => burst_f1, | |
| 422 | burst_f2 => burst_f2, |
|
422 | burst_f2 => burst_f2, | |
| 423 |
|
423 | |||
| 424 | nb_data_by_buffer => nb_data_by_buffer, |
|
424 | nb_data_by_buffer => nb_data_by_buffer, | |
| 425 | nb_word_by_buffer => nb_word_by_buffer, |
|
425 | nb_word_by_buffer => nb_word_by_buffer, | |
| 426 | nb_snapshot_param => nb_snapshot_param, |
|
426 | nb_snapshot_param => nb_snapshot_param, | |
| 427 | status_full => status_full, |
|
427 | status_full => status_full, | |
| 428 | status_full_ack => status_full_ack, |
|
428 | status_full_ack => status_full_ack, | |
| 429 | status_full_err => status_full_err, |
|
429 | status_full_err => status_full_err, | |
| 430 | status_new_err => status_new_err, |
|
430 | status_new_err => status_new_err, | |
| 431 |
|
431 | |||
| 432 | coarse_time => coarse_time, |
|
432 | coarse_time => coarse_time, | |
| 433 | fine_time => fine_time, |
|
433 | fine_time => fine_time, | |
| 434 |
|
434 | |||
| 435 | --f0 |
|
435 | --f0 | |
| 436 | addr_data_f0 => addr_data_f0, |
|
436 | addr_data_f0 => addr_data_f0, | |
| 437 | data_f0_in_valid => sample_f0_val, |
|
437 | data_f0_in_valid => sample_f0_val, | |
| 438 | data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug |
|
438 | data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug | |
| 439 | --f1 |
|
439 | --f1 | |
| 440 | addr_data_f1 => addr_data_f1, |
|
440 | addr_data_f1 => addr_data_f1, | |
| 441 | data_f1_in_valid => sample_f1_val, |
|
441 | data_f1_in_valid => sample_f1_val, | |
| 442 | data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, |
|
442 | data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, | |
| 443 | --f2 |
|
443 | --f2 | |
| 444 | addr_data_f2 => addr_data_f2, |
|
444 | addr_data_f2 => addr_data_f2, | |
| 445 | data_f2_in_valid => sample_f2_val, |
|
445 | data_f2_in_valid => sample_f2_val, | |
| 446 | data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, |
|
446 | data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, | |
| 447 | --f3 |
|
447 | --f3 | |
| 448 | addr_data_f3 => addr_data_f3, |
|
448 | addr_data_f3 => addr_data_f3, | |
| 449 | data_f3_in_valid => sample_f3_val, |
|
449 | data_f3_in_valid => sample_f3_val, | |
| 450 | data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, |
|
450 | data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, | |
| 451 | -- OUTPUT -- DMA interface |
|
451 | -- OUTPUT -- DMA interface | |
| 452 | --f0 |
|
452 | --f0 | |
| 453 | data_f0_addr_out => data_f0_addr_out_s, |
|
453 | data_f0_addr_out => data_f0_addr_out_s, | |
| 454 | data_f0_data_out => data_f0_data_out, |
|
454 | data_f0_data_out => data_f0_data_out, | |
| 455 | data_f0_data_out_valid => data_f0_data_out_valid_s, |
|
455 | data_f0_data_out_valid => data_f0_data_out_valid_s, | |
| 456 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, |
|
456 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, | |
| 457 | data_f0_data_out_ren => data_f0_data_out_ren, |
|
457 | data_f0_data_out_ren => data_f0_data_out_ren, | |
| 458 | --f1 |
|
458 | --f1 | |
| 459 | data_f1_addr_out => data_f1_addr_out_s, |
|
459 | data_f1_addr_out => data_f1_addr_out_s, | |
| 460 | data_f1_data_out => data_f1_data_out, |
|
460 | data_f1_data_out => data_f1_data_out, | |
| 461 | data_f1_data_out_valid => data_f1_data_out_valid_s, |
|
461 | data_f1_data_out_valid => data_f1_data_out_valid_s, | |
| 462 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, |
|
462 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, | |
| 463 | data_f1_data_out_ren => data_f1_data_out_ren, |
|
463 | data_f1_data_out_ren => data_f1_data_out_ren, | |
| 464 | --f2 |
|
464 | --f2 | |
| 465 | data_f2_addr_out => data_f2_addr_out_s, |
|
465 | data_f2_addr_out => data_f2_addr_out_s, | |
| 466 | data_f2_data_out => data_f2_data_out, |
|
466 | data_f2_data_out => data_f2_data_out, | |
| 467 | data_f2_data_out_valid => data_f2_data_out_valid_s, |
|
467 | data_f2_data_out_valid => data_f2_data_out_valid_s, | |
| 468 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, |
|
468 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, | |
| 469 | data_f2_data_out_ren => data_f2_data_out_ren, |
|
469 | data_f2_data_out_ren => data_f2_data_out_ren, | |
| 470 | --f3 |
|
470 | --f3 | |
| 471 | data_f3_addr_out => data_f3_addr_out_s, |
|
471 | data_f3_addr_out => data_f3_addr_out_s, | |
| 472 | data_f3_data_out => data_f3_data_out, |
|
472 | data_f3_data_out => data_f3_data_out, | |
| 473 | data_f3_data_out_valid => data_f3_data_out_valid_s, |
|
473 | data_f3_data_out_valid => data_f3_data_out_valid_s, | |
| 474 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, |
|
474 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, | |
| 475 | data_f3_data_out_ren => data_f3_data_out_ren, |
|
475 | data_f3_data_out_ren => data_f3_data_out_ren, | |
| 476 |
|
476 | |||
| 477 | -- debug SNAPSHOT_OUT |
|
477 | -- debug SNAPSHOT_OUT | |
| 478 | debug_f0_data => debug_f0_data, |
|
478 | debug_f0_data => debug_f0_data, | |
| 479 | debug_f0_data_valid => debug_f0_data_valid , |
|
479 | debug_f0_data_valid => debug_f0_data_valid , | |
| 480 | debug_f1_data => debug_f1_data , |
|
480 | debug_f1_data => debug_f1_data , | |
| 481 | debug_f1_data_valid => debug_f1_data_valid, |
|
481 | debug_f1_data_valid => debug_f1_data_valid, | |
| 482 | debug_f2_data => debug_f2_data , |
|
482 | debug_f2_data => debug_f2_data , | |
| 483 | debug_f2_data_valid => debug_f2_data_valid , |
|
483 | debug_f2_data_valid => debug_f2_data_valid , | |
| 484 | debug_f3_data => debug_f3_data , |
|
484 | debug_f3_data => debug_f3_data , | |
| 485 | debug_f3_data_valid => debug_f3_data_valid, |
|
485 | debug_f3_data_valid => debug_f3_data_valid, | |
| 486 |
|
486 | |||
| 487 | -- debug FIFO_IN |
|
487 | -- debug FIFO_IN | |
| 488 | debug_f0_data_fifo_in => debug_f0_data_fifo_in , |
|
488 | debug_f0_data_fifo_in => debug_f0_data_fifo_in , | |
| 489 | debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid, |
|
489 | debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid, | |
| 490 | debug_f1_data_fifo_in => debug_f1_data_fifo_in , |
|
490 | debug_f1_data_fifo_in => debug_f1_data_fifo_in , | |
| 491 | debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid, |
|
491 | debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid, | |
| 492 | debug_f2_data_fifo_in => debug_f2_data_fifo_in , |
|
492 | debug_f2_data_fifo_in => debug_f2_data_fifo_in , | |
| 493 | debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid, |
|
493 | debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid, | |
| 494 | debug_f3_data_fifo_in => debug_f3_data_fifo_in , |
|
494 | debug_f3_data_fifo_in => debug_f3_data_fifo_in , | |
| 495 | debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid |
|
495 | debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid | |
| 496 |
|
496 | |||
| 497 | ); |
|
497 | ); | |
| 498 |
|
498 | |||
| 499 |
|
499 | |||
| 500 | ----------------------------------------------------------------------------- |
|
500 | ----------------------------------------------------------------------------- | |
| 501 | -- DEBUG -- WFP OUT |
|
501 | -- DEBUG -- WFP OUT | |
| 502 | debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren; |
|
502 | debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren; | |
| 503 | debug_f0_data_fifo_out <= data_f0_data_out; |
|
503 | debug_f0_data_fifo_out <= data_f0_data_out; | |
| 504 | debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren; |
|
504 | debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren; | |
| 505 | debug_f1_data_fifo_out <= data_f1_data_out; |
|
505 | debug_f1_data_fifo_out <= data_f1_data_out; | |
| 506 | debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren; |
|
506 | debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren; | |
| 507 | debug_f2_data_fifo_out <= data_f2_data_out; |
|
507 | debug_f2_data_fifo_out <= data_f2_data_out; | |
| 508 | debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren; |
|
508 | debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren; | |
| 509 | debug_f3_data_fifo_out <= data_f3_data_out; |
|
509 | debug_f3_data_fifo_out <= data_f3_data_out; | |
| 510 | ----------------------------------------------------------------------------- |
|
510 | ----------------------------------------------------------------------------- | |
| 511 |
|
511 | |||
| 512 |
|
512 | |||
| 513 | ----------------------------------------------------------------------------- |
|
513 | ----------------------------------------------------------------------------- | |
| 514 | -- TEMP |
|
514 | -- TEMP | |
| 515 | ----------------------------------------------------------------------------- |
|
515 | ----------------------------------------------------------------------------- | |
| 516 |
|
516 | |||
| 517 | PROCESS (clk, rstn) |
|
517 | PROCESS (clk, rstn) | |
| 518 | BEGIN -- PROCESS |
|
518 | BEGIN -- PROCESS | |
| 519 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
519 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
| 520 | data_f0_data_out_valid <= '0'; |
|
520 | data_f0_data_out_valid <= '0'; | |
| 521 | data_f0_data_out_valid_burst <= '0'; |
|
521 | data_f0_data_out_valid_burst <= '0'; | |
| 522 | data_f1_data_out_valid <= '0'; |
|
522 | data_f1_data_out_valid <= '0'; | |
| 523 | data_f1_data_out_valid_burst <= '0'; |
|
523 | data_f1_data_out_valid_burst <= '0'; | |
| 524 | data_f2_data_out_valid <= '0'; |
|
524 | data_f2_data_out_valid <= '0'; | |
| 525 | data_f2_data_out_valid_burst <= '0'; |
|
525 | data_f2_data_out_valid_burst <= '0'; | |
| 526 | data_f3_data_out_valid <= '0'; |
|
526 | data_f3_data_out_valid <= '0'; | |
| 527 | data_f3_data_out_valid_burst <= '0'; |
|
527 | data_f3_data_out_valid_burst <= '0'; | |
| 528 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
528 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
| 529 | data_f0_data_out_valid <= data_f0_data_out_valid_s; |
|
529 | data_f0_data_out_valid <= data_f0_data_out_valid_s; | |
| 530 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; |
|
530 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; | |
| 531 | data_f1_data_out_valid <= data_f1_data_out_valid_s; |
|
531 | data_f1_data_out_valid <= data_f1_data_out_valid_s; | |
| 532 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; |
|
532 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; | |
| 533 | data_f2_data_out_valid <= data_f2_data_out_valid_s; |
|
533 | data_f2_data_out_valid <= data_f2_data_out_valid_s; | |
| 534 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; |
|
534 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; | |
| 535 | data_f3_data_out_valid <= data_f3_data_out_valid_s; |
|
535 | data_f3_data_out_valid <= data_f3_data_out_valid_s; | |
| 536 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; |
|
536 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; | |
| 537 | END IF; |
|
537 | END IF; | |
| 538 | END PROCESS; |
|
538 | END PROCESS; | |
| 539 |
|
539 | |||
| 540 | data_f0_addr_out <= data_f0_addr_out_s; |
|
540 | data_f0_addr_out <= data_f0_addr_out_s; | |
| 541 | data_f1_addr_out <= data_f1_addr_out_s; |
|
541 | data_f1_addr_out <= data_f1_addr_out_s; | |
| 542 | data_f2_addr_out <= data_f2_addr_out_s; |
|
542 | data_f2_addr_out <= data_f2_addr_out_s; | |
| 543 | data_f3_addr_out <= data_f3_addr_out_s; |
|
543 | data_f3_addr_out <= data_f3_addr_out_s; | |
| 544 |
|
544 | |||
| 545 | ----------------------------------------------------------------------------- |
|
545 | ----------------------------------------------------------------------------- | |
| 546 | -- RoundRobin Selection For DMA |
|
546 | -- RoundRobin Selection For DMA | |
| 547 | ----------------------------------------------------------------------------- |
|
547 | ----------------------------------------------------------------------------- | |
| 548 |
|
548 | |||
| 549 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; |
|
549 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; | |
| 550 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; |
|
550 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; | |
| 551 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; |
|
551 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; | |
| 552 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; |
|
552 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; | |
| 553 |
|
553 | |||
| 554 | RR_Arbiter_4_1 : RR_Arbiter_4 |
|
554 | RR_Arbiter_4_1 : RR_Arbiter_4 | |
| 555 | PORT MAP ( |
|
555 | PORT MAP ( | |
| 556 | clk => clk, |
|
556 | clk => clk, | |
| 557 | rstn => rstn, |
|
557 | rstn => rstn, | |
| 558 | in_valid => dma_rr_valid, |
|
558 | in_valid => dma_rr_valid, | |
| 559 | out_grant => dma_rr_grant); |
|
559 | out_grant => dma_rr_grant); | |
| 560 |
|
560 | |||
| 561 |
|
561 | |||
| 562 | ----------------------------------------------------------------------------- |
|
562 | ----------------------------------------------------------------------------- | |
| 563 | -- in : dma_rr_grant |
|
563 | -- in : dma_rr_grant | |
| 564 | -- send |
|
564 | -- send | |
| 565 | -- out : dma_sel |
|
565 | -- out : dma_sel | |
| 566 | -- dma_valid_burst |
|
566 | -- dma_valid_burst | |
| 567 | -- dma_sel_valid |
|
567 | -- dma_sel_valid | |
| 568 | ----------------------------------------------------------------------------- |
|
568 | ----------------------------------------------------------------------------- | |
| 569 | PROCESS (clk, rstn) |
|
569 | PROCESS (clk, rstn) | |
| 570 | BEGIN -- PROCESS |
|
570 | BEGIN -- PROCESS | |
| 571 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
571 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
| 572 | dma_sel <= (OTHERS => '0'); |
|
572 | dma_sel <= (OTHERS => '0'); | |
| 573 | dma_send <= '0'; |
|
573 | dma_send <= '0'; | |
| 574 | dma_valid_burst <= '0'; |
|
574 | dma_valid_burst <= '0'; | |
| 575 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
575 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
|
576 | IF run = '1' THEN | |||
| 576 | -- IF dma_sel = "0000" OR dma_send = '1' THEN |
|
577 | -- IF dma_sel = "0000" OR dma_send = '1' THEN | |
| 577 | IF dma_sel = "0000" OR dma_done = '1' THEN |
|
578 | IF dma_sel = "0000" OR dma_done = '1' THEN | |
| 578 | dma_sel <= dma_rr_grant; |
|
579 | dma_sel <= dma_rr_grant; | |
| 579 | IF dma_rr_grant(0) = '1' THEN |
|
580 | IF dma_rr_grant(0) = '1' THEN | |
| 580 | dma_send <= '1'; |
|
581 | dma_send <= '1'; | |
| 581 | dma_valid_burst <= data_f0_data_out_valid_burst; |
|
582 | dma_valid_burst <= data_f0_data_out_valid_burst; | |
| 582 | dma_sel_valid <= data_f0_data_out_valid; |
|
583 | dma_sel_valid <= data_f0_data_out_valid; | |
| 583 | ELSIF dma_rr_grant(1) = '1' THEN |
|
584 | ELSIF dma_rr_grant(1) = '1' THEN | |
| 584 | dma_send <= '1'; |
|
585 | dma_send <= '1'; | |
| 585 | dma_valid_burst <= data_f1_data_out_valid_burst; |
|
586 | dma_valid_burst <= data_f1_data_out_valid_burst; | |
| 586 | dma_sel_valid <= data_f1_data_out_valid; |
|
587 | dma_sel_valid <= data_f1_data_out_valid; | |
| 587 | ELSIF dma_rr_grant(2) = '1' THEN |
|
588 | ELSIF dma_rr_grant(2) = '1' THEN | |
| 588 | dma_send <= '1'; |
|
589 | dma_send <= '1'; | |
| 589 | dma_valid_burst <= data_f2_data_out_valid_burst; |
|
590 | dma_valid_burst <= data_f2_data_out_valid_burst; | |
| 590 | dma_sel_valid <= data_f2_data_out_valid; |
|
591 | dma_sel_valid <= data_f2_data_out_valid; | |
| 591 | ELSIF dma_rr_grant(3) = '1' THEN |
|
592 | ELSIF dma_rr_grant(3) = '1' THEN | |
| 592 | dma_send <= '1'; |
|
593 | dma_send <= '1'; | |
| 593 | dma_valid_burst <= data_f3_data_out_valid_burst; |
|
594 | dma_valid_burst <= data_f3_data_out_valid_burst; | |
| 594 | dma_sel_valid <= data_f3_data_out_valid; |
|
595 | dma_sel_valid <= data_f3_data_out_valid; | |
|
|
596 | END IF; | |||
|
|
597 | ELSE | |||
|
|
598 | dma_sel <= dma_sel; | |||
|
|
599 | dma_send <= '0'; | |||
| 595 | END IF; |
|
600 | END IF; | |
| 596 | ELSE |
|
601 | ELSE | |
| 597 | dma_sel <= dma_sel; |
|
602 | dma_sel <= (OTHERS => '0'); | |
| 598 | dma_send <= '0'; |
|
603 | dma_send <= '0'; | |
|
|
604 | dma_valid_burst <= '0'; | |||
| 599 | END IF; |
|
605 | END IF; | |
| 600 | END IF; |
|
606 | END IF; | |
| 601 | END PROCESS; |
|
607 | END PROCESS; | |
| 602 |
|
608 | |||
| 603 |
|
609 | |||
| 604 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE |
|
610 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE | |
| 605 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE |
|
611 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE | |
| 606 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE |
|
612 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE | |
| 607 | data_f3_addr_out; |
|
613 | data_f3_addr_out; | |
| 608 |
|
614 | |||
| 609 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE |
|
615 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE | |
| 610 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE |
|
616 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE | |
| 611 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE |
|
617 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE | |
| 612 | data_f3_data_out; |
|
618 | data_f3_data_out; | |
| 613 |
|
619 | |||
| 614 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; |
|
620 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; | |
| 615 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; |
|
621 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; | |
| 616 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; |
|
622 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; | |
| 617 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; |
|
623 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; | |
| 618 |
|
624 | |||
| 619 | dma_data_2 <= dma_data; |
|
625 | dma_data_2 <= dma_data; | |
| 620 |
|
626 | |||
| 621 |
|
627 | |||
| 622 |
|
628 | |||
| 623 |
|
629 | |||
| 624 |
|
630 | |||
| 625 | ----------------------------------------------------------------------------- |
|
631 | ----------------------------------------------------------------------------- | |
| 626 | -- DEBUG -- DMA IN |
|
632 | -- DEBUG -- DMA IN | |
| 627 | debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; |
|
633 | debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; | |
| 628 | debug_f0_data_dma_in <= dma_data; |
|
634 | debug_f0_data_dma_in <= dma_data; | |
| 629 | debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; |
|
635 | debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; | |
| 630 | debug_f1_data_dma_in <= dma_data; |
|
636 | debug_f1_data_dma_in <= dma_data; | |
| 631 | debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; |
|
637 | debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; | |
| 632 | debug_f2_data_dma_in <= dma_data; |
|
638 | debug_f2_data_dma_in <= dma_data; | |
| 633 | debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; |
|
639 | debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; | |
| 634 | debug_f3_data_dma_in <= dma_data; |
|
640 | debug_f3_data_dma_in <= dma_data; | |
| 635 | ----------------------------------------------------------------------------- |
|
641 | ----------------------------------------------------------------------------- | |
| 636 |
|
642 | |||
| 637 | ----------------------------------------------------------------------------- |
|
643 | ----------------------------------------------------------------------------- | |
| 638 | -- DMA |
|
644 | -- DMA | |
| 639 | ----------------------------------------------------------------------------- |
|
645 | ----------------------------------------------------------------------------- | |
| 640 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst |
|
646 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst | |
| 641 | GENERIC MAP ( |
|
647 | GENERIC MAP ( | |
| 642 | tech => inferred, |
|
648 | tech => inferred, | |
| 643 | hindex => hindex) |
|
649 | hindex => hindex) | |
| 644 | PORT MAP ( |
|
650 | PORT MAP ( | |
| 645 | HCLK => clk, |
|
651 | HCLK => clk, | |
| 646 | HRESETn => rstn, |
|
652 | HRESETn => rstn, | |
| 647 | run => run, |
|
653 | run => run, | |
| 648 | AHB_Master_In => ahbi, |
|
654 | AHB_Master_In => ahbi, | |
| 649 | AHB_Master_Out => ahbo, |
|
655 | AHB_Master_Out => ahbo, | |
| 650 |
|
656 | |||
| 651 |
send => dma_send, |
|
657 | send => dma_send, | |
| 652 |
valid_burst => dma_valid_burst, |
|
658 | valid_burst => dma_valid_burst, | |
| 653 | done => dma_done, |
|
659 | done => dma_done, | |
| 654 | ren => dma_ren, |
|
660 | ren => dma_ren, | |
| 655 |
address => dma_address, |
|
661 | address => dma_address, | |
| 656 | data => dma_data_2); |
|
662 | data => dma_data_2); | |
| 657 |
|
663 | |||
| 658 | ----------------------------------------------------------------------------- |
|
664 | ----------------------------------------------------------------------------- | |
| 659 | -- Matrix Spectral - TODO |
|
665 | -- Matrix Spectral - TODO | |
| 660 | ----------------------------------------------------------------------------- |
|
666 | ----------------------------------------------------------------------------- | |
| 661 | ----------------------------------------------------------------------------- |
|
667 | ----------------------------------------------------------------------------- | |
| 662 | --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & |
|
668 | --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & | |
| 663 | -- NOT(sample_f0_val) & NOT(sample_f0_val) ; |
|
669 | -- NOT(sample_f0_val) & NOT(sample_f0_val) ; | |
| 664 | --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & |
|
670 | --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & | |
| 665 | -- NOT(sample_f1_val) & NOT(sample_f1_val) ; |
|
671 | -- NOT(sample_f1_val) & NOT(sample_f1_val) ; | |
| 666 | --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & |
|
672 | --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & | |
| 667 | -- NOT(sample_f3_val) & NOT(sample_f3_val) ; |
|
673 | -- NOT(sample_f3_val) & NOT(sample_f3_val) ; | |
| 668 |
|
674 | |||
| 669 | --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) |
|
675 | --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) | |
| 670 | --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
|
676 | --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); | |
| 671 | --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); |
|
677 | --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); | |
| 672 | ------------------------------------------------------------------------------- |
|
678 | ------------------------------------------------------------------------------- | |
| 673 | --lpp_lfr_ms_1: lpp_lfr_ms |
|
679 | --lpp_lfr_ms_1: lpp_lfr_ms | |
| 674 | -- GENERIC MAP ( |
|
680 | -- GENERIC MAP ( | |
| 675 | -- hindex => hindex_ms) |
|
681 | -- hindex => hindex_ms) | |
| 676 | -- PORT MAP ( |
|
682 | -- PORT MAP ( | |
| 677 | -- clk => clk, |
|
683 | -- clk => clk, | |
| 678 | -- rstn => rstn, |
|
684 | -- rstn => rstn, | |
| 679 | -- sample_f0_wen => sample_f0_wen, |
|
685 | -- sample_f0_wen => sample_f0_wen, | |
| 680 | -- sample_f0_wdata => sample_f0_wdata, |
|
686 | -- sample_f0_wdata => sample_f0_wdata, | |
| 681 | -- sample_f1_wen => sample_f1_wen, |
|
687 | -- sample_f1_wen => sample_f1_wen, | |
| 682 | -- sample_f1_wdata => sample_f1_wdata, |
|
688 | -- sample_f1_wdata => sample_f1_wdata, | |
| 683 | -- sample_f3_wen => sample_f3_wen, |
|
689 | -- sample_f3_wen => sample_f3_wen, | |
| 684 | -- sample_f3_wdata => sample_f3_wdata, |
|
690 | -- sample_f3_wdata => sample_f3_wdata, | |
| 685 | -- AHB_Master_In => ahbi_ms, |
|
691 | -- AHB_Master_In => ahbi_ms, | |
| 686 | -- AHB_Master_Out => ahbo_ms, |
|
692 | -- AHB_Master_Out => ahbo_ms, | |
| 687 |
|
693 | |||
| 688 | -- ready_matrix_f0_0 => ready_matrix_f0_0, |
|
694 | -- ready_matrix_f0_0 => ready_matrix_f0_0, | |
| 689 | -- ready_matrix_f0_1 => ready_matrix_f0_1, |
|
695 | -- ready_matrix_f0_1 => ready_matrix_f0_1, | |
| 690 | -- ready_matrix_f1 => ready_matrix_f1, |
|
696 | -- ready_matrix_f1 => ready_matrix_f1, | |
| 691 | -- ready_matrix_f2 => ready_matrix_f2, |
|
697 | -- ready_matrix_f2 => ready_matrix_f2, | |
| 692 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
698 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
| 693 | -- error_bad_component_error => error_bad_component_error, |
|
699 | -- error_bad_component_error => error_bad_component_error, | |
| 694 | -- debug_reg => debug_reg, |
|
700 | -- debug_reg => debug_reg, | |
| 695 | -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
701 | -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
| 696 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
702 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
| 697 | -- status_ready_matrix_f1 => status_ready_matrix_f1, |
|
703 | -- status_ready_matrix_f1 => status_ready_matrix_f1, | |
| 698 | -- status_ready_matrix_f2 => status_ready_matrix_f2, |
|
704 | -- status_ready_matrix_f2 => status_ready_matrix_f2, | |
| 699 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
705 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
| 700 | -- status_error_bad_component_error => status_error_bad_component_error, |
|
706 | -- status_error_bad_component_error => status_error_bad_component_error, | |
| 701 | -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
707 | -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
| 702 | -- config_active_interruption_onError => config_active_interruption_onError, |
|
708 | -- config_active_interruption_onError => config_active_interruption_onError, | |
| 703 | -- addr_matrix_f0_0 => addr_matrix_f0_0, |
|
709 | -- addr_matrix_f0_0 => addr_matrix_f0_0, | |
| 704 | -- addr_matrix_f0_1 => addr_matrix_f0_1, |
|
710 | -- addr_matrix_f0_1 => addr_matrix_f0_1, | |
| 705 | -- addr_matrix_f1 => addr_matrix_f1, |
|
711 | -- addr_matrix_f1 => addr_matrix_f1, | |
| 706 | -- addr_matrix_f2 => addr_matrix_f2); |
|
712 | -- addr_matrix_f2 => addr_matrix_f2); | |
| 707 |
|
713 | |||
| 708 | END beh; |
|
714 | END beh; | |
| @@ -1,200 +1,218 | |||||
| 1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
| 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
| 3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
| 4 | -- |
|
4 | -- | |
| 5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
| 6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
| 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
| 8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
| 9 | -- |
|
9 | -- | |
| 10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
| 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
| 14 | -- |
|
14 | -- | |
| 15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
| 16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
| 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
| 19 | -- Author : Jean-christophe PELLION |
|
19 | -- Author : Jean-christophe PELLION | |
| 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
| 21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
| 22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
| 23 | USE IEEE.std_logic_1164.ALL; |
|
23 | USE IEEE.std_logic_1164.ALL; | |
| 24 | USE IEEE.numeric_std.ALL; |
|
24 | USE IEEE.numeric_std.ALL; | |
| 25 | LIBRARY lpp; |
|
25 | LIBRARY lpp; | |
| 26 | USE lpp.lpp_memory.ALL; |
|
26 | USE lpp.lpp_memory.ALL; | |
| 27 | USE lpp.iir_filter.ALL; |
|
27 | USE lpp.iir_filter.ALL; | |
| 28 | USE lpp.lpp_waveform_pkg.ALL; |
|
28 | USE lpp.lpp_waveform_pkg.ALL; | |
| 29 |
|
29 | |||
| 30 | LIBRARY techmap; |
|
30 | LIBRARY techmap; | |
| 31 | USE techmap.gencomp.ALL; |
|
31 | USE techmap.gencomp.ALL; | |
| 32 |
|
32 | |||
| 33 | ENTITY lpp_waveform_fifo_headreg IS |
|
33 | ENTITY lpp_waveform_fifo_headreg IS | |
| 34 | GENERIC( |
|
34 | GENERIC( | |
| 35 | tech : INTEGER := 0 |
|
35 | tech : INTEGER := 0 | |
| 36 | ); |
|
36 | ); | |
| 37 | PORT( |
|
37 | PORT( | |
| 38 | clk : IN STD_LOGIC; |
|
38 | clk : IN STD_LOGIC; | |
| 39 | rstn : IN STD_LOGIC; |
|
39 | rstn : IN STD_LOGIC; | |
| 40 | --------------------------------------------------------------------------- |
|
40 | --------------------------------------------------------------------------- | |
| 41 | run : IN STD_LOGIC; |
|
41 | run : IN STD_LOGIC; | |
| 42 | --------------------------------------------------------------------------- |
|
42 | --------------------------------------------------------------------------- | |
| 43 | o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b |
|
43 | o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b | |
| 44 | o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
44 | o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 45 | o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
45 | o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 46 | o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- |
|
46 | o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- | |
| 47 | o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- |
|
47 | o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- | |
| 48 | o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- |
|
48 | o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- | |
| 49 | o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- |
|
49 | o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- | |
| 50 | --------------------------------------------------------------------------- |
|
50 | --------------------------------------------------------------------------- | |
| 51 | i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
51 | i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 52 | i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
52 | i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 53 | i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- |
|
53 | i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- | |
| 54 | i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
54 | i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
| 55 | ); |
|
55 | ); | |
| 56 | END ENTITY; |
|
56 | END ENTITY; | |
| 57 |
|
57 | |||
| 58 |
|
58 | |||
| 59 | ARCHITECTURE ar_lpp_waveform_fifo_headreg OF lpp_waveform_fifo_headreg IS |
|
59 | ARCHITECTURE ar_lpp_waveform_fifo_headreg OF lpp_waveform_fifo_headreg IS | |
| 60 | SIGNAL reg_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
60 | SIGNAL reg_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 61 | SIGNAL s_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
61 | SIGNAL s_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 62 | SIGNAL s_ren_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
62 | SIGNAL s_ren_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 63 | SIGNAL one_ren_and_notEmpty : STD_LOGIC; |
|
63 | SIGNAL one_ren_and_notEmpty : STD_LOGIC; | |
| 64 | SIGNAL ren_and_notEmpty : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
64 | SIGNAL ren_and_notEmpty : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 65 | SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
65 | SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 66 | SIGNAL s_rdata_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
66 | SIGNAL s_rdata_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 67 | SIGNAL s_rdata_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
67 | SIGNAL s_rdata_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 68 | SIGNAL s_rdata_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
68 | SIGNAL s_rdata_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 69 | SIGNAL s_rdata_3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
69 | SIGNAL s_rdata_3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 70 | BEGIN |
|
70 | BEGIN | |
| 71 |
|
71 | |||
| 72 | ----------------------------------------------------------------------------- |
|
72 | ----------------------------------------------------------------------------- | |
| 73 | -- DATA_REN_FIFO |
|
73 | -- DATA_REN_FIFO | |
| 74 | ----------------------------------------------------------------------------- |
|
74 | ----------------------------------------------------------------------------- | |
| 75 | i_data_ren <= s_ren; |
|
75 | i_data_ren <= s_ren; | |
| 76 | PROCESS (clk, rstn) |
|
76 | PROCESS (clk, rstn) | |
| 77 | BEGIN |
|
77 | BEGIN | |
| 78 | IF rstn = '0' THEN |
|
78 | IF rstn = '0' THEN | |
| 79 | s_ren_reg <= (OTHERS => '1'); |
|
79 | s_ren_reg <= (OTHERS => '1'); | |
| 80 | ELSIF clk'EVENT AND clk = '1' THEN |
|
80 | ELSIF clk'EVENT AND clk = '1' THEN | |
| 81 | s_ren_reg <= s_ren; |
|
81 | IF run = '1' THEN | |
|
|
82 | s_ren_reg <= s_ren; | |||
|
|
83 | ELSE | |||
|
|
84 | s_ren_reg <= (OTHERS => '1'); | |||
|
|
85 | END IF; | |||
| 82 | END IF; |
|
86 | END IF; | |
| 83 | END PROCESS; |
|
87 | END PROCESS; | |
| 84 |
|
88 | |||
| 85 | s_ren(0) <= o_data_ren(0) WHEN one_ren_and_notEmpty = '1' ELSE |
|
89 | s_ren(0) <= o_data_ren(0) WHEN one_ren_and_notEmpty = '1' ELSE | |
| 86 | NOT ((NOT i_empty(0)) AND (NOT reg_full(0))); |
|
90 | NOT ((NOT i_empty(0)) AND (NOT reg_full(0))); | |
| 87 | s_ren(1) <= o_data_ren(1) WHEN one_ren_and_notEmpty = '1' ELSE |
|
91 | s_ren(1) <= o_data_ren(1) WHEN one_ren_and_notEmpty = '1' ELSE | |
| 88 | '1' WHEN s_ren(0) = '0' ELSE |
|
92 | '1' WHEN s_ren(0) = '0' ELSE | |
| 89 | NOT ((NOT i_empty(1)) AND (NOT reg_full(1))); |
|
93 | NOT ((NOT i_empty(1)) AND (NOT reg_full(1))); | |
| 90 | s_ren(2) <= o_data_ren(2) WHEN one_ren_and_notEmpty = '1' ELSE |
|
94 | s_ren(2) <= o_data_ren(2) WHEN one_ren_and_notEmpty = '1' ELSE | |
| 91 | '1' WHEN s_ren(0) = '0' ELSE |
|
95 | '1' WHEN s_ren(0) = '0' ELSE | |
| 92 | '1' WHEN s_ren(1) = '0' ELSE |
|
96 | '1' WHEN s_ren(1) = '0' ELSE | |
| 93 | NOT ((NOT i_empty(2)) AND (NOT reg_full(2))); |
|
97 | NOT ((NOT i_empty(2)) AND (NOT reg_full(2))); | |
| 94 | s_ren(3) <= o_data_ren(3) WHEN one_ren_and_notEmpty = '1' ELSE |
|
98 | s_ren(3) <= o_data_ren(3) WHEN one_ren_and_notEmpty = '1' ELSE | |
| 95 | '1' WHEN s_ren(0) = '0' ELSE |
|
99 | '1' WHEN s_ren(0) = '0' ELSE | |
| 96 | '1' WHEN s_ren(1) = '0' ELSE |
|
100 | '1' WHEN s_ren(1) = '0' ELSE | |
| 97 | '1' WHEN s_ren(2) = '0' ELSE |
|
101 | '1' WHEN s_ren(2) = '0' ELSE | |
| 98 | NOT ((NOT i_empty(3)) AND (NOT reg_full(3))); |
|
102 | NOT ((NOT i_empty(3)) AND (NOT reg_full(3))); | |
| 99 | ----------------------------------------------------------------------------- |
|
103 | ----------------------------------------------------------------------------- | |
| 100 | all_ren : FOR I IN 3 DOWNTO 0 GENERATE |
|
104 | all_ren : FOR I IN 3 DOWNTO 0 GENERATE | |
| 101 | ren_and_notEmpty(I) <= (NOT o_data_ren(I)) AND (NOT i_empty(I)); |
|
105 | ren_and_notEmpty(I) <= (NOT o_data_ren(I)) AND (NOT i_empty(I)); | |
| 102 | END GENERATE all_ren; |
|
106 | END GENERATE all_ren; | |
| 103 | one_ren_and_notEmpty <= '0' WHEN ren_and_notEmpty = "0000" ELSE '1'; |
|
107 | one_ren_and_notEmpty <= '0' WHEN ren_and_notEmpty = "0000" ELSE '1'; | |
| 104 |
|
108 | |||
| 105 | ----------------------------------------------------------------------------- |
|
109 | ----------------------------------------------------------------------------- | |
| 106 | -- DATA |
|
110 | -- DATA | |
| 107 | ----------------------------------------------------------------------------- |
|
111 | ----------------------------------------------------------------------------- | |
| 108 | o_rdata_0 <= i_rdata WHEN s_ren_reg(0) = '0' AND s_ren(0) = '0' ELSE s_rdata_0; |
|
112 | o_rdata_0 <= i_rdata WHEN s_ren_reg(0) = '0' AND s_ren(0) = '0' ELSE s_rdata_0; | |
| 109 | o_rdata_1 <= i_rdata WHEN s_ren_reg(1) = '0' AND s_ren(1) = '0' ELSE s_rdata_1; |
|
113 | o_rdata_1 <= i_rdata WHEN s_ren_reg(1) = '0' AND s_ren(1) = '0' ELSE s_rdata_1; | |
| 110 | o_rdata_2 <= i_rdata WHEN s_ren_reg(2) = '0' AND s_ren(2) = '0' ELSE s_rdata_2; |
|
114 | o_rdata_2 <= i_rdata WHEN s_ren_reg(2) = '0' AND s_ren(2) = '0' ELSE s_rdata_2; | |
| 111 | o_rdata_3 <= i_rdata WHEN s_ren_reg(3) = '0' AND s_ren(3) = '0' ELSE s_rdata_3; |
|
115 | o_rdata_3 <= i_rdata WHEN s_ren_reg(3) = '0' AND s_ren(3) = '0' ELSE s_rdata_3; | |
| 112 |
|
116 | |||
| 113 | PROCESS (clk, rstn) |
|
117 | PROCESS (clk, rstn) | |
| 114 | BEGIN |
|
118 | BEGIN | |
| 115 | IF rstn = '0' THEN |
|
119 | IF rstn = '0' THEN | |
| 116 | s_rdata_0 <= (OTHERS => '0'); |
|
120 | s_rdata_0 <= (OTHERS => '0'); | |
| 117 | s_rdata_1 <= (OTHERS => '0'); |
|
121 | s_rdata_1 <= (OTHERS => '0'); | |
| 118 | s_rdata_2 <= (OTHERS => '0'); |
|
122 | s_rdata_2 <= (OTHERS => '0'); | |
| 119 | s_rdata_3 <= (OTHERS => '0'); |
|
123 | s_rdata_3 <= (OTHERS => '0'); | |
| 120 | ELSIF clk'EVENT AND clk = '1' THEN |
|
124 | ELSIF clk'EVENT AND clk = '1' THEN | |
| 121 | IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF; |
|
125 | IF run = '1' THEN | |
| 122 |
IF s_ren_reg( |
|
126 | IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF; | |
| 123 |
IF s_ren_reg( |
|
127 | IF s_ren_reg(1) = '0' THEN s_rdata_1 <= i_rdata; END IF; | |
| 124 |
IF s_ren_reg( |
|
128 | IF s_ren_reg(2) = '0' THEN s_rdata_2 <= i_rdata; END IF; | |
|
|
129 | IF s_ren_reg(3) = '0' THEN s_rdata_3 <= i_rdata; END IF; | |||
|
|
130 | ELSE | |||
|
|
131 | s_rdata_0 <= (OTHERS => '0'); | |||
|
|
132 | s_rdata_1 <= (OTHERS => '0'); | |||
|
|
133 | s_rdata_2 <= (OTHERS => '0'); | |||
|
|
134 | s_rdata_3 <= (OTHERS => '0'); | |||
|
|
135 | END IF; | |||
| 125 | END IF; |
|
136 | END IF; | |
| 126 | END PROCESS; |
|
137 | END PROCESS; | |
| 127 |
|
138 | |||
| 128 | all_reg_full : FOR I IN 3 DOWNTO 0 GENERATE |
|
139 | all_reg_full : FOR I IN 3 DOWNTO 0 GENERATE | |
| 129 | PROCESS (clk, rstn) |
|
140 | PROCESS (clk, rstn) | |
| 130 | BEGIN |
|
141 | BEGIN | |
| 131 | IF rstn = '0' THEN |
|
142 | IF rstn = '0' THEN | |
| 132 | reg_full(I) <= '0'; |
|
143 | reg_full(I) <= '0'; | |
| 133 | ELSIF clk'EVENT AND clk = '1' THEN |
|
144 | ELSIF clk'EVENT AND clk = '1' THEN | |
| 134 | -- IF s_ren_reg(I) = '0' THEN |
|
145 | -- IF s_ren_reg(I) = '0' THEN | |
| 135 |
IF |
|
146 | IF run = '1' THEN | |
| 136 |
|
|
147 | IF s_ren(I) = '0' THEN | |
| 137 | ELSIF o_data_ren(I) = '0' THEN |
|
148 | reg_full(I) <= '1'; | |
|
|
149 | ELSIF o_data_ren(I) = '0' THEN | |||
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150 | reg_full(I) <= '0'; | |||
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151 | END IF; | |||
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152 | ELSE | |||
| 138 | reg_full(I) <= '0'; |
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153 | reg_full(I) <= '0'; | |
| 139 | END IF; |
|
154 | END IF; | |
| 140 | END IF; |
|
155 | END IF; | |
| 141 | END PROCESS; |
|
156 | END PROCESS; | |
| 142 | END GENERATE all_reg_full; |
|
157 | END GENERATE all_reg_full; | |
| 143 |
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158 | |||
| 144 | ----------------------------------------------------------------------------- |
|
159 | ----------------------------------------------------------------------------- | |
| 145 | -- EMPTY |
|
160 | -- EMPTY | |
| 146 | ----------------------------------------------------------------------------- |
|
161 | ----------------------------------------------------------------------------- | |
| 147 | o_empty <= NOT reg_full; |
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162 | o_empty <= NOT reg_full; | |
| 148 |
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163 | |||
| 149 | ----------------------------------------------------------------------------- |
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164 | ----------------------------------------------------------------------------- | |
| 150 | -- EMPTY_ALMOST |
|
165 | -- EMPTY_ALMOST | |
| 151 | ----------------------------------------------------------------------------- |
|
166 | ----------------------------------------------------------------------------- | |
| 152 | o_empty_almost <= s_empty_almost; |
|
167 | o_empty_almost <= s_empty_almost; | |
| 153 |
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168 | |||
| 154 | all_empty_almost: FOR I IN 3 DOWNTO 0 GENERATE |
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169 | all_empty_almost: FOR I IN 3 DOWNTO 0 GENERATE | |
| 155 | PROCESS (clk, rstn) |
|
170 | PROCESS (clk, rstn) | |
| 156 | BEGIN -- PROCESS |
|
171 | BEGIN -- PROCESS | |
| 157 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
172 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
| 158 | s_empty_almost(I) <= '1'; |
|
173 | s_empty_almost(I) <= '1'; | |
| 159 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
174 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
| 160 |
|
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175 | IF run = '1' THEN | |
| 161 | IF s_ren(I) = '0' THEN |
|
176 | IF s_ren(I) = '0' THEN | |
| 162 | s_empty_almost(I) <= i_empty_almost(I); |
|
177 | s_empty_almost(I) <= i_empty_almost(I); | |
| 163 | ELSIF o_data_ren(I) = '0' THEN |
|
178 | ELSIF o_data_ren(I) = '0' THEN | |
|
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179 | s_empty_almost(I) <= '1'; | |||
|
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180 | ELSE | |||
|
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181 | IF i_empty_almost(I) = '0' THEN | |||
|
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182 | s_empty_almost(I) <= '0'; | |||
|
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183 | END IF; | |||
|
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184 | END IF; | |||
|
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185 | ELSE | |||
| 164 | s_empty_almost(I) <= '1'; |
|
186 | s_empty_almost(I) <= '1'; | |
| 165 | ELSE |
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|||
| 166 | IF i_empty_almost(I) = '0' THEN |
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|||
| 167 | s_empty_almost(I) <= '0'; |
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|||
| 168 | END IF; |
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|||
| 169 | END IF; |
|
187 | END IF; | |
| 170 | END IF; |
|
188 | END IF; | |
| 171 | END PROCESS; |
|
189 | END PROCESS; | |
| 172 | END GENERATE all_empty_almost; |
|
190 | END GENERATE all_empty_almost; | |
| 173 |
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191 | |||
| 174 | END ARCHITECTURE; |
|
192 | END ARCHITECTURE; | |
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