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2 | 2 | quietly WaveActivateNextPane {} 0 |
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3 | 3 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot |
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4 | 4 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run |
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5 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out | |
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6 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out | |
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7 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out | |
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5 | add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out | |
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6 | add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out | |
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7 | add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out | |
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8 | 8 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid |
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9 | 9 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid |
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10 | 10 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid |
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11 |
add wave -noupdate -radix hexadecimal |
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11 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd | |
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12 | 12 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address |
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13 | 13 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in |
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14 | 14 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out |
| @@ -23,20 +23,20 add wave -noupdate -group DMA_S_or_B /te | |||
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23 | 23 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst |
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24 | 24 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin |
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25 | 25 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout |
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26 | add wave -noupdate -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.address {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain | |
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26 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain | |
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27 | 27 | add wave -noupdate -label data -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data |
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28 | 28 | add wave -noupdate -label grant /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout.grant |
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29 | 29 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout |
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30 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_0(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_0 | |
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31 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_0(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_0 | |
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32 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_1(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_1 | |
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33 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_1(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_1 | |
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34 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_2 | |
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35 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2 | |
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36 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_3 | |
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37 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_3 | |
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30 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_0 | |
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31 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_0 | |
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32 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_1 | |
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33 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_1 | |
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34 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_2 | |
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35 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/async_1mx16_1/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2 | |
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36 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/async_1mx16_0/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_3 | |
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37 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_3 | |
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38 | 38 | TreeUpdate [SetDefaultTree] |
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39 |
WaveRestoreCursors {{Cursor 1} { |
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39 | WaveRestoreCursors {{Cursor 1} {340947831721 ps} 0} | |
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40 | 40 | configure wave -namecolwidth 540 |
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41 | 41 | configure wave -valuecolwidth 316 |
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42 | 42 | configure wave -justifyvalue left |
| @@ -51,4 +51,4 configure wave -griddelta 40 | |||
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51 | 51 | configure wave -timeline 0 |
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52 | 52 | configure wave -timelineunits ns |
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53 | 53 | update |
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54 |
WaveRestoreZoom {0 ps} {6 |
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54 | WaveRestoreZoom {0 ps} {628873035 ns} | |
| @@ -39,7 +39,7 LIBRARY lpp; | |||
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39 | 39 | USE lpp.lpp_memory.ALL; |
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40 | 40 | USE lpp.lpp_ad_conv.ALL; |
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41 | 41 | --USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
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42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
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43 | 43 | USE lpp.iir_filter.ALL; |
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44 | 44 | USE lpp.general_purpose.ALL; |
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45 | 45 | USE lpp.lpp_lfr_time_management.ALL; |
| @@ -61,15 +61,15 ENTITY MINI_LFR_top IS | |||
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61 | 61 | --UARTs |
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62 | 62 | TXD1 : IN STD_LOGIC; |
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63 | 63 | RXD1 : OUT STD_LOGIC; |
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64 |
nCTS1 : OUT STD_LOGIC; |
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65 |
nRTS1 : IN STD_LOGIC; |
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64 | nCTS1 : OUT STD_LOGIC; | |
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65 | nRTS1 : IN STD_LOGIC; | |
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66 | 66 | |
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67 | 67 | TXD2 : IN STD_LOGIC; |
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68 | 68 | RXD2 : OUT STD_LOGIC; |
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69 |
nCTS2 : OUT STD_LOGIC; |
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70 |
nDTR2 : IN STD_LOGIC; |
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71 |
nRTS2 : IN STD_LOGIC; |
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72 |
nDCD2 : OUT STD_LOGIC; |
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69 | nCTS2 : OUT STD_LOGIC; | |
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70 | nDTR2 : IN STD_LOGIC; | |
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71 | nRTS2 : IN STD_LOGIC; | |
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72 | nDCD2 : OUT STD_LOGIC; | |
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73 | 73 | |
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74 | 74 | --EXT CONNECTOR |
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75 | 75 | IO0 : INOUT STD_LOGIC; |
| @@ -86,19 +86,19 ENTITY MINI_LFR_top IS | |||
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86 | 86 | IO11 : INOUT STD_LOGIC; |
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87 | 87 | |
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88 | 88 | --SPACE WIRE |
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89 |
SPW_EN : OUT STD_LOGIC; |
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90 |
SPW_NOM_DIN : IN STD_LOGIC; |
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89 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |
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90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |
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91 | 91 | SPW_NOM_SIN : IN STD_LOGIC; |
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92 | 92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
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93 | 93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
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94 |
SPW_RED_DIN : IN STD_LOGIC; |
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94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |
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95 | 95 | SPW_RED_SIN : IN STD_LOGIC; |
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96 | 96 | SPW_RED_DOUT : OUT STD_LOGIC; |
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97 | 97 | SPW_RED_SOUT : OUT STD_LOGIC; |
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98 | 98 | -- MINI LFR ADC INPUTS |
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99 | 99 | ADC_nCS : OUT STD_LOGIC; |
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100 | 100 | ADC_CLK : OUT STD_LOGIC; |
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101 |
ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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102 | 102 | |
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103 | 103 | -- SRAM |
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104 | 104 | SRAM_nWE : OUT STD_LOGIC; |
| @@ -113,61 +113,61 END MINI_LFR_top; | |||
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113 | 113 | |
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114 | 114 | |
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115 | 115 | ARCHITECTURE beh OF MINI_LFR_top IS |
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116 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
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117 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
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116 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
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117 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
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118 | 118 | ----------------------------------------------------------------------------- |
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119 |
SIGNAL coarse_time |
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120 |
SIGNAL fine_time |
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119 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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120 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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121 | 121 | -- |
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122 | SIGNAL errorn : STD_LOGIC; | |
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122 | SIGNAL errorn : STD_LOGIC; | |
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123 | 123 | -- UART AHB --------------------------------------------------------------- |
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124 |
SIGNAL |
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125 |
SIGNAL |
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124 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |
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125 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |
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126 | 126 | |
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127 | 127 | -- UART APB --------------------------------------------------------------- |
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128 |
SIGNAL |
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129 |
SIGNAL |
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130 |
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128 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |
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129 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |
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130 | -- | |
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131 | 131 | SIGNAL I00_s : STD_LOGIC; |
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132 | ||
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132 | ||
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133 | 133 | -- CONSTANTS |
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134 |
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134 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
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135 | 135 | -- |
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136 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
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136 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
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137 | 137 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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138 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
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139 | ||
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140 |
SIGNAL |
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141 |
SIGNAL |
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142 |
SIGNAL |
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143 |
SIGNAL |
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144 |
SIGNAL |
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145 |
SIGNAL |
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146 | ||
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138 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
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139 | ||
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140 | SIGNAL apbi_ext : apb_slv_in_type; | |
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141 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); | |
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142 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
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143 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); | |
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144 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
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145 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); | |
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146 | ||
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147 | 147 | -- Spacewire signals |
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148 |
SIGNAL dtmp |
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149 |
SIGNAL stmp |
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150 |
SIGNAL spw_rxclk |
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151 |
SIGNAL spw_rxtxclk |
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152 |
SIGNAL spw_rxclkn |
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153 |
SIGNAL spw_clk |
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154 |
SIGNAL swni |
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155 |
SIGNAL swno |
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156 |
-- SIGNAL clkmn |
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157 |
-- SIGNAL txclk |
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148 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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149 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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150 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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151 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
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152 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
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153 | SIGNAL spw_clk : STD_LOGIC; | |
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154 | SIGNAL swni : grspw_in_type; | |
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155 | SIGNAL swno : grspw_out_type; | |
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156 | -- SIGNAL clkmn : STD_ULOGIC; | |
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157 | -- SIGNAL txclk : STD_ULOGIC; | |
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158 | 158 | |
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159 | 159 | --GPIO |
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160 |
SIGNAL gpioi |
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161 |
SIGNAL gpioo |
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160 | SIGNAL gpioi : gpio_in_type; | |
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161 | SIGNAL gpioo : gpio_out_type; | |
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162 | 162 | |
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163 | 163 | -- AD Converter ADS7886 |
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164 |
SIGNAL sample |
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165 |
SIGNAL sample_val |
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166 |
SIGNAL ADC_nCS_sig |
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167 |
SIGNAL ADC_CLK_sig |
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168 |
SIGNAL ADC_SDO_sig |
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169 | ||
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170 |
SIGNAL |
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164 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
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165 | SIGNAL sample_val : STD_LOGIC; | |
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166 | SIGNAL ADC_nCS_sig : STD_LOGIC; | |
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167 | SIGNAL ADC_CLK_sig : STD_LOGIC; | |
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168 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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169 | ||
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170 | SIGNAL bias_fail_sw_sig : STD_LOGIC; | |
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171 | 171 | |
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172 | 172 | BEGIN -- beh |
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173 | 173 | |
| @@ -181,7 +181,7 BEGIN -- beh | |||
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181 | 181 | clk_50_s <= NOT clk_50_s; |
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182 | 182 | END IF; |
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183 | 183 | END PROCESS; |
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184 | ||
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184 | ||
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185 | 185 | PROCESS(clk_50_s) |
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186 | 186 | BEGIN |
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187 | 187 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
| @@ -190,7 +190,7 BEGIN -- beh | |||
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190 | 190 | END PROCESS; |
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191 | 191 | |
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192 | 192 | ----------------------------------------------------------------------------- |
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193 | ||
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193 | ||
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194 | 194 | PROCESS (clk_25, reset) |
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195 | 195 | BEGIN -- PROCESS |
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196 | 196 | IF reset = '0' THEN -- asynchronous reset (active low) |
| @@ -208,7 +208,7 BEGIN -- beh | |||
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208 | 208 | --IO9 <= '0'; |
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209 | 209 | --IO10 <= '0'; |
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210 | 210 | --IO11 <= '0'; |
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211 |
ELSIF clk_25' |
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211 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
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212 | 212 | LED0 <= '0'; |
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213 | 213 | LED1 <= '1'; |
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214 | 214 | LED2 <= BP0; |
| @@ -222,30 +222,30 BEGIN -- beh | |||
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222 | 222 | --IO8 <= ADC_SDO(5); |
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223 | 223 | --IO9 <= ADC_SDO(6); |
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224 | 224 | --IO10 <= ADC_SDO(7); |
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225 |
IO11 |
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225 | IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
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226 | 226 | END IF; |
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227 | 227 | END PROCESS; |
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228 | ||
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228 | ||
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229 | 229 | PROCESS (clk_49, reset) |
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230 | 230 | BEGIN -- PROCESS |
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231 | 231 | IF reset = '0' THEN -- asynchronous reset (active low) |
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232 |
I00_s |
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233 |
ELSIF clk_49' |
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234 |
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235 |
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232 | I00_s <= '0'; | |
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233 | ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge | |
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234 | I00_s <= NOT I00_s; | |
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235 | END IF; | |
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236 | 236 | END PROCESS; |
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237 | 237 | -- IO0 <= I00_s; |
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238 | 238 | |
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239 | 239 | --UARTs |
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240 |
nCTS1 |
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241 |
nCTS2 |
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242 |
nDCD2 |
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240 | nCTS1 <= '1'; | |
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241 | nCTS2 <= '1'; | |
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242 | nDCD2 <= '1'; | |
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243 | 243 | |
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244 | 244 | --EXT CONNECTOR |
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245 | 245 | |
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246 | 246 | --SPACE WIRE |
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247 | 247 | |
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248 | leon3_soc_1: leon3_soc | |
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248 | leon3_soc_1 : leon3_soc | |
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249 | 249 | GENERIC MAP ( |
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250 | 250 | fabtech => apa3e, |
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251 | 251 | memtech => apa3e, |
| @@ -267,34 +267,34 BEGIN -- beh | |||
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267 | 267 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
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268 | 268 | NB_APB_SLAVE => NB_APB_SLAVE) |
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269 | 269 | PORT MAP ( |
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270 |
clk |
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271 |
reset |
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272 |
errorn |
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273 |
ahbrxd |
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274 |
ahbtxd |
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275 |
urxd1 |
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276 |
utxd1 |
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277 |
address |
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278 |
data |
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279 |
nSRAM_BE0 |
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280 |
nSRAM_BE1 |
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281 |
nSRAM_BE2 |
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282 |
nSRAM_BE3 |
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283 |
nSRAM_WE |
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284 |
nSRAM_CE |
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285 |
nSRAM_OE |
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286 | ||
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270 | clk => clk_25, | |
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271 | reset => reset, | |
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272 | errorn => errorn, | |
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273 | ahbrxd => TXD1, | |
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274 | ahbtxd => RXD1, | |
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275 | urxd1 => TXD2, | |
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276 | utxd1 => RXD2, | |
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277 | address => SRAM_A, | |
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278 | data => SRAM_DQ, | |
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279 | nSRAM_BE0 => SRAM_nBE(0), | |
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280 | nSRAM_BE1 => SRAM_nBE(1), | |
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281 | nSRAM_BE2 => SRAM_nBE(2), | |
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282 | nSRAM_BE3 => SRAM_nBE(3), | |
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283 | nSRAM_WE => SRAM_nWE, | |
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284 | nSRAM_CE => SRAM_CE, | |
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285 | nSRAM_OE => SRAM_nOE, | |
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286 | ||
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287 | 287 | apbi_ext => apbi_ext, |
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288 | 288 | apbo_ext => apbo_ext, |
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289 | 289 | ahbi_s_ext => ahbi_s_ext, |
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290 | 290 | ahbo_s_ext => ahbo_s_ext, |
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291 | 291 | ahbi_m_ext => ahbi_m_ext, |
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292 | 292 | ahbo_m_ext => ahbo_m_ext); |
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293 | ||
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293 | ||
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294 | 294 | ------------------------------------------------------------------------------- |
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295 | 295 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
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296 | 296 | ------------------------------------------------------------------------------- |
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297 | apb_lfr_time_management_1: apb_lfr_time_management | |
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297 | apb_lfr_time_management_1 : apb_lfr_time_management | |
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298 | 298 | GENERIC MAP ( |
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299 | 299 | pindex => 6, |
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300 | 300 | paddr => 6, |
| @@ -309,93 +309,93 BEGIN -- beh | |||
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309 | 309 | apbo => apbo_ext(6), |
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310 | 310 | coarse_time => coarse_time, |
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311 | 311 | fine_time => fine_time); |
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312 | ||
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312 | ||
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313 | 313 | ----------------------------------------------------------------------- |
|
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314 | 314 | --- SpaceWire -------------------------------------------------------- |
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315 | 315 | ----------------------------------------------------------------------- |
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316 | 316 | |
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317 |
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318 | ||
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319 |
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320 |
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321 |
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322 | ||
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323 |
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324 |
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325 |
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326 |
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327 |
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328 |
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329 |
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330 |
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331 |
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332 |
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333 |
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334 |
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335 |
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336 |
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337 |
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338 |
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339 |
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340 |
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317 | SPW_EN <= '1'; | |
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318 | ||
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319 | spw_clk <= clk_50_s; | |
|
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320 | spw_rxtxclk <= spw_clk; | |
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321 | spw_rxclkn <= NOT spw_rxtxclk; | |
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322 | ||
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323 | -- PADS for SPW1 | |
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324 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |
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325 | PORT MAP (SPW_NOM_DIN, dtmp(0)); | |
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326 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |
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327 | PORT MAP (SPW_NOM_SIN, stmp(0)); | |
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328 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |
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329 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); | |
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330 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |
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331 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); | |
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332 | -- PADS FOR SPW2 | |
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333 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
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334 | PORT MAP (SPW_RED_SIN, dtmp(1)); | |
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335 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
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336 | PORT MAP (SPW_RED_DIN, stmp(1)); | |
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337 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |
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338 | PORT MAP (SPW_RED_DOUT, swno.d(1)); | |
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339 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |
|
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340 | PORT MAP (SPW_RED_SOUT, swno.s(1)); | |
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341 | 341 | |
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342 |
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343 |
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344 | spw_inputloop: for j in 0 to 1 generate | |
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345 |
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346 | generic map( | |
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347 |
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348 |
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349 |
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350 | port map( | |
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351 |
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352 |
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353 |
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354 |
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355 |
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356 |
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357 |
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358 | end generate spw_inputloop; | |
|
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342 | -- GRSPW PHY | |
|
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343 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |
|
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344 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
|
|
345 | spw_phy0 : grspw_phy | |
|
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346 | GENERIC MAP( | |
|
|
347 | tech => apa3e, | |
|
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348 | rxclkbuftype => 1, | |
|
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349 | scantest => 0) | |
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350 | PORT MAP( | |
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351 | rxrst => swno.rxrst, | |
|
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352 | di => dtmp(j), | |
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353 | si => stmp(j), | |
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354 | rxclko => spw_rxclk(j), | |
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355 | do => swni.d(j), | |
|
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356 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
|
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357 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
|
|
358 | END GENERATE spw_inputloop; | |
|
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359 | 359 | |
|
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360 |
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|
361 | sw0 : grspwm generic map( | |
|
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362 |
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363 |
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364 |
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365 |
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366 | pirq => 11, | |
|
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367 |
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368 |
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369 |
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370 |
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371 |
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372 |
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373 |
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374 |
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|
375 | ft => 0, | |
|
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376 |
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377 |
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378 |
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379 |
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380 |
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381 |
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382 |
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383 |
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384 |
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385 | ) | |
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386 |
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387 |
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388 |
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389 |
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390 | ||
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391 |
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392 |
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393 |
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394 |
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395 |
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396 |
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397 |
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|
398 | ||
|
|
360 | -- SPW core | |
|
|
361 | sw0 : grspwm GENERIC MAP( | |
|
|
362 | tech => apa3e, | |
|
|
363 | hindex => 1, | |
|
|
364 | pindex => 5, | |
|
|
365 | paddr => 5, | |
|
|
366 | pirq => 11, | |
|
|
367 | sysfreq => 25000, -- CPU_FREQ | |
|
|
368 | rmap => 1, | |
|
|
369 | rmapcrc => 1, | |
|
|
370 | fifosize1 => 16, | |
|
|
371 | fifosize2 => 16, | |
|
|
372 | rxclkbuftype => 1, | |
|
|
373 | rxunaligned => 0, | |
|
|
374 | rmapbufs => 4, | |
|
|
375 | ft => 0, | |
|
|
376 | netlist => 0, | |
|
|
377 | ports => 2, | |
|
|
378 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
|
|
379 | memtech => apa3e, | |
|
|
380 | destkey => 2, | |
|
|
381 | spwcore => 1 | |
|
|
382 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
|
|
383 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
|
|
384 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
|
|
385 | ) | |
|
|
386 | PORT MAP(reset, clk_25, spw_rxclk(0), | |
|
|
387 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |
|
|
388 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |
|
|
389 | swni, swno); | |
|
|
390 | ||
|
|
391 | swni.tickin <= '0'; | |
|
|
392 | swni.rmapen <= '1'; | |
|
|
393 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |
|
|
394 | swni.tickinraw <= '0'; | |
|
|
395 | swni.timein <= (OTHERS => '0'); | |
|
|
396 | swni.dcrstval <= (OTHERS => '0'); | |
|
|
397 | swni.timerrstval <= (OTHERS => '0'); | |
|
|
398 | ||
|
|
399 | 399 | ------------------------------------------------------------------------------- |
|
|
400 | 400 | -- LFR ------------------------------------------------------------------------ |
|
|
401 | 401 | ------------------------------------------------------------------------------- |
| @@ -428,7 +428,7 BEGIN -- beh | |||
|
|
428 | 428 | -- fine_time => fine_time, |
|
|
429 | 429 | -- data_shaping_BW => bias_fail_sw_sig); |
|
|
430 | 430 | |
|
|
431 |
|
|
|
|
431 | waveform_picker0 : top_wf_picker | |
|
|
432 | 432 | GENERIC MAP( |
|
|
433 | 433 | hindex => 2, |
|
|
434 | 434 | pindex => 15, |
| @@ -438,7 +438,7 BEGIN -- beh | |||
|
|
438 | 438 | tech => apa3e, |
|
|
439 | 439 | nb_burst_available_size => 12, -- size of the register holding the nb of burst |
|
|
440 | 440 | nb_snapshot_param_size => 12, -- size of the register holding the snapshots size |
|
|
441 | delta_snapshot_size => 16, -- snapshots period | |
|
|
441 | delta_snapshot_size => 16, -- snapshots period | |
|
|
442 | 442 | delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts |
|
|
443 | 443 | delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot |
|
|
444 | 444 | ENABLE_FILTER => '1' |
| @@ -447,9 +447,9 BEGIN -- beh | |||
|
|
447 | 447 | cnv_clk => clk_25, |
|
|
448 | 448 | cnv_rstn => reset, |
|
|
449 | 449 | -- SAMPLES |
|
|
450 | sample_B => sample(2 DOWNTO 0), | |
|
|
451 | sample_E => sample(7 DOWNTO 3), | |
|
|
452 |
sample_val => sample_val, |
|
|
|
450 | sample_B => sample(2 DOWNTO 0), | |
|
|
451 | sample_E => sample(7 DOWNTO 3), | |
|
|
452 | sample_val => sample_val, | |
|
|
453 | 453 | -- AMBA AHB system signals |
|
|
454 | 454 | HCLK => clk_25, |
|
|
455 | 455 | HRESETn => reset, |
| @@ -462,68 +462,52 BEGIN -- beh | |||
|
|
462 | 462 | -- |
|
|
463 | 463 | coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time |
|
|
464 | 464 | -- |
|
|
465 |
data_shaping_BW => bias_fail_sw_sig |
|
|
|
465 | data_shaping_BW => bias_fail_sw_sig | |
|
|
466 | 466 | ); |
|
|
467 | 467 | |
|
|
468 |
|
|
|
|
468 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 | |
|
|
469 | 469 | GENERIC MAP( |
|
|
470 |
|
|
|
|
471 |
|
|
|
|
472 |
ncycle_cnv_high => 80, |
|
|
|
473 | ncycle_cnv => 500) -- 49 152 000 / 98304 | |
|
|
470 | ChannelCount => 8, | |
|
|
471 | SampleNbBits => 14, | |
|
|
472 | ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63 | |
|
|
473 | ncycle_cnv => 500) -- 49 152 000 / 98304 | |
|
|
474 | 474 | PORT MAP ( |
|
|
475 |
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|
|
476 |
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|
|
477 |
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|
|
478 |
|
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|
479 |
|
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|
|
480 |
|
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|
|
481 |
|
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|
|
482 |
|
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|
|
483 |
|
|
|
|
484 |
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|
|
485 |
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|
|
486 |
|
|
|
|
487 | ||
|
|
488 | IO10 <= ADC_SDO_sig(5); | |
|
|
489 | IO9 <= ADC_SDO_sig(4); | |
|
|
490 | IO8 <= ADC_SDO_sig(3); | |
|
|
475 | -- CONV | |
|
|
476 | cnv_clk => clk_49, | |
|
|
477 | cnv_rstn => reset, | |
|
|
478 | cnv => ADC_nCS_sig, | |
|
|
479 | -- DATA | |
|
|
480 | clk => clk_25, | |
|
|
481 | rstn => reset, | |
|
|
482 | sck => ADC_CLK_sig, | |
|
|
483 | sdo => ADC_SDO_sig, | |
|
|
484 | -- SAMPLE | |
|
|
485 | sample => sample, | |
|
|
486 | sample_val => sample_val); | |
|
|
491 | 487 | |
|
|
492 |
|
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|
|
493 |
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|
|
494 |
|
|
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|
495 | ||
|
|
488 | IO10 <= ADC_SDO_sig(5); | |
|
|
489 | IO9 <= ADC_SDO_sig(4); | |
|
|
490 | IO8 <= ADC_SDO_sig(3); | |
|
|
491 | ||
|
|
492 | ADC_nCS <= ADC_nCS_sig; | |
|
|
493 | ADC_CLK <= ADC_CLK_sig; | |
|
|
494 | ADC_SDO_sig <= ADC_SDO; | |
|
|
495 | ||
|
|
496 | 496 | ---------------------------------------------------------------------- |
|
|
497 | 497 | --- GPIO ----------------------------------------------------------- |
|
|
498 | 498 | ---------------------------------------------------------------------- |
|
|
499 | 499 | |
|
|
500 | grgpio0: grgpio | |
|
|
501 |
|
|
|
|
502 |
|
|
|
|
503 | ||
|
|
504 | pio_pad_0 : iopad | |
|
|
505 | generic map (tech => CFG_PADTECH) | |
|
|
506 | port map (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); | |
|
|
507 | pio_pad_1 : iopad | |
|
|
508 | generic map (tech => CFG_PADTECH) | |
|
|
509 | port map (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); | |
|
|
510 | pio_pad_2 : iopad | |
|
|
511 | generic map (tech => CFG_PADTECH) | |
|
|
512 | port map (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); | |
|
|
513 | pio_pad_3 : iopad | |
|
|
514 | generic map (tech => CFG_PADTECH) | |
|
|
515 | port map (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); | |
|
|
516 | pio_pad_4 : iopad | |
|
|
517 | generic map (tech => CFG_PADTECH) | |
|
|
518 | port map (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); | |
|
|
519 | pio_pad_5 : iopad | |
|
|
520 | generic map (tech => CFG_PADTECH) | |
|
|
521 | port map (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); | |
|
|
522 | pio_pad_6 : iopad | |
|
|
523 | generic map (tech => CFG_PADTECH) | |
|
|
524 | port map (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); | |
|
|
525 | pio_pad_7 : iopad | |
|
|
526 | generic map (tech => CFG_PADTECH) | |
|
|
527 | port map (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); | |
|
|
500 | grgpio0 : grgpio | |
|
|
501 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) | |
|
|
502 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); | |
|
|
503 | ||
|
|
504 | pio_pad_0 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); | |
|
|
505 | pio_pad_1 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); | |
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506 | pio_pad_2 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); | |
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507 | pio_pad_3 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); | |
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508 | pio_pad_4 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); | |
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509 | pio_pad_5 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); | |
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510 | pio_pad_6 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); | |
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511 | pio_pad_7 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); | |
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528 | 512 | |
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529 | END beh; No newline at end of file | |
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513 | END beh; | |
| @@ -413,7 +413,7 BEGIN -- beh | |||
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413 | 413 | pirq_ms => 6, |
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414 | 414 | pirq_wfp => 14, |
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415 | 415 | hindex => 2, |
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416 |
top_lfr_version => X"0000000 |
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416 | top_lfr_version => X"0000000B") | |
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417 | 417 | PORT MAP ( |
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418 | 418 | clk => clk_25, |
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419 | 419 | rstn => reset, |
| @@ -8,21 +8,21 USE lpp.general_purpose.SYNC_FF; | |||
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8 | 8 | |
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9 | 9 | ENTITY top_ad_conv_ADS7886_v2 IS |
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10 | 10 | GENERIC( |
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11 |
ChannelCount |
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12 |
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13 |
ncycle_cnv_high : INTEGER := 40; |
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11 | ChannelCount : INTEGER := 8; | |
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12 | SampleNbBits : INTEGER := 14; | |
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13 | ncycle_cnv_high : INTEGER := 40; -- at least 32 cycles | |
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14 | 14 | ncycle_cnv : INTEGER := 500); |
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15 | 15 | PORT ( |
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16 |
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17 |
cnv_clk |
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18 |
cnv_rstn |
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19 |
cnv |
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20 |
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21 |
clk |
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22 |
rstn |
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23 |
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24 |
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25 |
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16 | -- CONV | |
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17 | cnv_clk : IN STD_LOGIC; | |
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18 | cnv_rstn : IN STD_LOGIC; | |
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19 | cnv : OUT STD_LOGIC; | |
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20 | -- DATA | |
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21 | clk : IN STD_LOGIC; | |
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22 | rstn : IN STD_LOGIC; | |
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23 | sck : OUT STD_LOGIC; | |
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24 | sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0); | |
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25 | -- SAMPLE | |
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26 | 26 | sample : OUT Samples14v(ChannelCount-1 DOWNTO 0); |
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27 | 27 | sample_val : OUT STD_LOGIC |
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28 | 28 | ); |
| @@ -33,10 +33,10 ARCHITECTURE ar_top_ad_conv_ADS7886_v2 O | |||
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33 | 33 | SIGNAL cnv_cycle_counter : INTEGER; |
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34 | 34 | SIGNAL cnv_s : STD_LOGIC; |
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35 | 35 | SIGNAL cnv_sync : STD_LOGIC; |
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36 |
SIGNAL cnv_sync_not |
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37 | ||
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38 |
SIGNAL sample_adc |
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39 |
SIGNAL sample_val_adc |
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36 | SIGNAL cnv_sync_not : STD_LOGIC; | |
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37 | ||
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38 | SIGNAL sample_adc : Samples(ChannelCount-1 DOWNTO 0); | |
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39 | SIGNAL sample_val_adc : STD_LOGIC; | |
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40 | 40 | |
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41 | 41 | BEGIN |
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42 | 42 | |
| @@ -69,68 +69,65 BEGIN | |||
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69 | 69 | END IF; |
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70 | 70 | END PROCESS; |
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71 | 71 | |
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72 |
cnv |
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72 | cnv <= NOT(cnv_s); | |
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73 | 73 | |
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74 | 74 | ----------------------------------------------------------------------------- |
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75 | 75 | -- SYNC CNV |
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76 | 76 | ----------------------------------------------------------------------------- |
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77 | ||
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77 | ||
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78 | 78 | SYNC_FF_cnv : SYNC_FF |
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79 | 79 | GENERIC MAP ( |
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80 | 80 | NB_FF_OF_SYNC => 2) |
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81 | 81 | PORT MAP ( |
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82 | 82 | clk => clk, |
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83 | 83 | rstn => rstn, |
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84 |
A => cnv_s, |
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84 | A => cnv_s, -- the data fetching begins immediately | |
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85 | 85 | A_sync => cnv_sync); |
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86 | 86 | |
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87 | 87 | ----------------------------------------------------------------------------- |
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88 | 88 | |
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89 |
cnv_sync_not |
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89 | cnv_sync_not <= NOT(cnv_sync); | |
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90 | 90 | |
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91 |
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92 |
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93 |
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94 |
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95 |
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96 |
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97 |
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98 |
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99 |
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100 |
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101 | rstn => rstn, | |
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102 | sck => sck, | |
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103 | sdo => sdo, | |
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104 |
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105 |
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106 |
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91 | ADS7886_drvr_v2_1 : ADS7886_drvr_v2 | |
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92 | GENERIC MAP( | |
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93 | ChannelCount => 8, | |
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94 | NbBitsSamples => 16) | |
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95 | PORT MAP( | |
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96 | -- CONV -- | |
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97 | cnv_clk => cnv_sync_not, | |
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98 | cnv_rstn => rstn, | |
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99 | -- DATA -- | |
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100 | clk => clk, -- master clock, 25 MHz | |
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101 | rstn => rstn, | |
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102 | sck => sck, | |
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103 | sdo => sdo, | |
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104 | -- SAMPLE -- | |
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|
105 | sample => sample_adc, | |
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106 | sample_val => sample_val_adc); | |
|
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107 | 107 | |
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108 | PROCESS (clk, rstn) | |
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108 | PROCESS (clk, rstn) | |
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109 | 109 | BEGIN -- PROCESS |
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110 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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111 |
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112 |
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113 |
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114 |
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110 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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111 | FOR k IN 0 TO ChannelCount-1 LOOP | |
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112 | sample(k)(13 DOWNTO 0) <= (OTHERS => '0'); | |
|
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113 | END LOOP; | |
|
|
114 | sample_val <= '0'; | |
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|
115 | 115 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
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116 |
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117 |
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118 |
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119 |
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120 |
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121 |
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122 |
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123 |
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124 |
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125 |
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|
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126 | -- FOR k IN 0 TO ChannelCount-1 LOOP | |
|
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127 | -- sample(k) <= sample_adc(k)(13 downto 0); | |
|
|
128 | -- END LOOP; | |
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|
129 | sample_val <= sample_val_adc; | |
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130 | ELSE | |
|
|
131 | sample_val <= '0'; | |
|
|
132 | END IF; | |
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|
116 | IF sample_val_adc = '1' THEN | |
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117 | FOR k IN 0 TO ChannelCount-1 LOOP | |
|
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118 | IF (UNSIGNED(sample_adc(k)(11 DOWNTO 0)) >= 2048) THEN | |
|
|
119 | sample(k)(13 DOWNTO 0) <= "00" & | |
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|
120 | STD_LOGIC_VECTOR(UNSIGNED(sample_adc(k)(11 DOWNTO 0)) - 2048); | |
|
|
121 | ELSE | |
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122 | sample(k)(13 DOWNTO 0) <= "11" & | |
|
|
123 | STD_LOGIC_VECTOR(UNSIGNED(sample_adc(k)(11 DOWNTO 0)) - 2048); | |
|
|
124 | END IF; | |
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125 | END LOOP; | |
|
|
126 | sample_val <= sample_val_adc; | |
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|
127 | ELSE | |
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128 | sample_val <= '0'; | |
|
|
129 | END IF; | |
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133 | 130 | END IF; |
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|
134 | END PROCESS; | |
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131 | END PROCESS; | |
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135 | 132 | |
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136 | END ar_top_ad_conv_ADS7886_v2; No newline at end of file | |
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|
133 | END ar_top_ad_conv_ADS7886_v2; | |
| @@ -90,7 +90,7 ENTITY lpp_lfr IS | |||
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|
90 | 90 | debug_f2_data_fifo_out_valid : OUT STD_LOGIC; |
|
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91 | 91 | debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
92 | 92 | debug_f3_data_fifo_out_valid : OUT STD_LOGIC; |
|
|
93 | ||
|
|
93 | ||
|
|
94 | 94 | --debug DMA IN |
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95 | 95 | debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
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96 | 96 | debug_f0_data_dma_in_valid : OUT STD_LOGIC; |
| @@ -573,29 +573,35 BEGIN | |||
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573 | 573 | dma_send <= '0'; |
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574 | 574 | dma_valid_burst <= '0'; |
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|
575 | 575 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
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|
576 | IF run = '1' THEN | |
|
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576 | 577 | -- IF dma_sel = "0000" OR dma_send = '1' THEN |
|
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577 | IF dma_sel = "0000" OR dma_done = '1' THEN | |
|
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578 | dma_sel <= dma_rr_grant; | |
|
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579 | IF dma_rr_grant(0) = '1' THEN | |
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580 | dma_send <= '1'; | |
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581 | dma_valid_burst <= data_f0_data_out_valid_burst; | |
|
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582 | dma_sel_valid <= data_f0_data_out_valid; | |
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583 | ELSIF dma_rr_grant(1) = '1' THEN | |
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584 | dma_send <= '1'; | |
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585 | dma_valid_burst <= data_f1_data_out_valid_burst; | |
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586 | dma_sel_valid <= data_f1_data_out_valid; | |
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587 | ELSIF dma_rr_grant(2) = '1' THEN | |
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588 | dma_send <= '1'; | |
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589 | dma_valid_burst <= data_f2_data_out_valid_burst; | |
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590 | dma_sel_valid <= data_f2_data_out_valid; | |
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591 | ELSIF dma_rr_grant(3) = '1' THEN | |
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592 | dma_send <= '1'; | |
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593 | dma_valid_burst <= data_f3_data_out_valid_burst; | |
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594 | dma_sel_valid <= data_f3_data_out_valid; | |
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578 | IF dma_sel = "0000" OR dma_done = '1' THEN | |
|
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579 | dma_sel <= dma_rr_grant; | |
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580 | IF dma_rr_grant(0) = '1' THEN | |
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581 | dma_send <= '1'; | |
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582 | dma_valid_burst <= data_f0_data_out_valid_burst; | |
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583 | dma_sel_valid <= data_f0_data_out_valid; | |
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584 | ELSIF dma_rr_grant(1) = '1' THEN | |
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585 | dma_send <= '1'; | |
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586 | dma_valid_burst <= data_f1_data_out_valid_burst; | |
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587 | dma_sel_valid <= data_f1_data_out_valid; | |
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|
588 | ELSIF dma_rr_grant(2) = '1' THEN | |
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589 | dma_send <= '1'; | |
|
|
590 | dma_valid_burst <= data_f2_data_out_valid_burst; | |
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|
591 | dma_sel_valid <= data_f2_data_out_valid; | |
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|
592 | ELSIF dma_rr_grant(3) = '1' THEN | |
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|
593 | dma_send <= '1'; | |
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594 | dma_valid_burst <= data_f3_data_out_valid_burst; | |
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595 | dma_sel_valid <= data_f3_data_out_valid; | |
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596 | END IF; | |
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|
597 | ELSE | |
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|
598 | dma_sel <= dma_sel; | |
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599 | dma_send <= '0'; | |
|
|
595 | 600 | END IF; |
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|
596 | 601 | ELSE |
|
|
597 | dma_sel <= dma_sel; | |
|
|
598 | dma_send <= '0'; | |
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|
602 | dma_sel <= (OTHERS => '0'); | |
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|
603 | dma_send <= '0'; | |
|
|
604 | dma_valid_burst <= '0'; | |
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|
599 | 605 | END IF; |
|
|
600 | 606 | END IF; |
|
|
601 | 607 | END PROCESS; |
| @@ -619,7 +625,7 BEGIN | |||
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|
619 | 625 | dma_data_2 <= dma_data; |
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|
620 | 626 | |
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621 | 627 | |
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622 | ||
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628 | ||
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623 | 629 | |
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624 | 630 | |
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625 | 631 | ----------------------------------------------------------------------------- |
| @@ -633,7 +639,7 BEGIN | |||
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633 | 639 | debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; |
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|
634 | 640 | debug_f3_data_dma_in <= dma_data; |
|
|
635 | 641 | ----------------------------------------------------------------------------- |
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636 | ||
|
|
642 | ||
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637 | 643 | ----------------------------------------------------------------------------- |
|
|
638 | 644 | -- DMA |
|
|
639 | 645 | ----------------------------------------------------------------------------- |
| @@ -648,11 +654,11 BEGIN | |||
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648 | 654 | AHB_Master_In => ahbi, |
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649 | 655 | AHB_Master_Out => ahbo, |
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650 | 656 | |
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651 |
send => dma_send, |
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652 |
valid_burst => dma_valid_burst, |
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657 | send => dma_send, | |
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|
658 | valid_burst => dma_valid_burst, | |
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653 | 659 | done => dma_done, |
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654 | 660 | ren => dma_ren, |
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655 |
address => dma_address, |
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661 | address => dma_address, | |
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656 | 662 | data => dma_data_2); |
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657 | 663 | |
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|
658 | 664 | ----------------------------------------------------------------------------- |
| @@ -78,7 +78,11 BEGIN | |||
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|
78 | 78 | IF rstn = '0' THEN |
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79 | 79 | s_ren_reg <= (OTHERS => '1'); |
|
|
80 | 80 | ELSIF clk'EVENT AND clk = '1' THEN |
|
|
81 | s_ren_reg <= s_ren; | |
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|
81 | IF run = '1' THEN | |
|
|
82 | s_ren_reg <= s_ren; | |
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|
83 | ELSE | |
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|
84 | s_ren_reg <= (OTHERS => '1'); | |
|
|
85 | END IF; | |
|
|
82 | 86 | END IF; |
|
|
83 | 87 | END PROCESS; |
|
|
84 | 88 | |
| @@ -118,10 +122,17 BEGIN | |||
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118 | 122 | s_rdata_2 <= (OTHERS => '0'); |
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119 | 123 | s_rdata_3 <= (OTHERS => '0'); |
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120 | 124 | ELSIF clk'EVENT AND clk = '1' THEN |
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121 | IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF; | |
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122 |
IF s_ren_reg( |
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123 |
IF s_ren_reg( |
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124 |
IF s_ren_reg( |
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125 | IF run = '1' THEN | |
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|
126 | IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF; | |
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127 | IF s_ren_reg(1) = '0' THEN s_rdata_1 <= i_rdata; END IF; | |
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128 | IF s_ren_reg(2) = '0' THEN s_rdata_2 <= i_rdata; END IF; | |
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129 | IF s_ren_reg(3) = '0' THEN s_rdata_3 <= i_rdata; END IF; | |
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130 | ELSE | |
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131 | s_rdata_0 <= (OTHERS => '0'); | |
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132 | s_rdata_1 <= (OTHERS => '0'); | |
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133 | s_rdata_2 <= (OTHERS => '0'); | |
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134 | s_rdata_3 <= (OTHERS => '0'); | |
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135 | END IF; | |
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125 | 136 | END IF; |
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|
126 | 137 | END PROCESS; |
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127 | 138 | |
| @@ -132,9 +143,13 BEGIN | |||
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132 | 143 | reg_full(I) <= '0'; |
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133 | 144 | ELSIF clk'EVENT AND clk = '1' THEN |
|
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134 | 145 | -- IF s_ren_reg(I) = '0' THEN |
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135 |
IF |
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136 |
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137 | ELSIF o_data_ren(I) = '0' THEN | |
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146 | IF run = '1' THEN | |
|
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147 | IF s_ren(I) = '0' THEN | |
|
|
148 | reg_full(I) <= '1'; | |
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149 | ELSIF o_data_ren(I) = '0' THEN | |
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|
150 | reg_full(I) <= '0'; | |
|
|
151 | END IF; | |
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152 | ELSE | |
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138 | 153 | reg_full(I) <= '0'; |
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139 | 154 | END IF; |
|
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140 | 155 | END IF; |
| @@ -157,15 +172,18 BEGIN | |||
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157 | 172 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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158 | 173 | s_empty_almost(I) <= '1'; |
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159 | 174 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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160 |
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161 | IF s_ren(I) = '0' THEN | |
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162 | s_empty_almost(I) <= i_empty_almost(I); | |
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163 | ELSIF o_data_ren(I) = '0' THEN | |
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175 | IF run = '1' THEN | |
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176 | IF s_ren(I) = '0' THEN | |
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177 | s_empty_almost(I) <= i_empty_almost(I); | |
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178 | ELSIF o_data_ren(I) = '0' THEN | |
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179 | s_empty_almost(I) <= '1'; | |
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180 | ELSE | |
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181 | IF i_empty_almost(I) = '0' THEN | |
|
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182 | s_empty_almost(I) <= '0'; | |
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|
183 | END IF; | |
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184 | END IF; | |
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185 | ELSE | |
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164 | 186 | s_empty_almost(I) <= '1'; |
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165 | ELSE | |
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|
166 | IF i_empty_almost(I) = '0' THEN | |
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|
167 | s_empty_almost(I) <= '0'; | |
|
|
168 | END IF; | |
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169 | 187 | END IF; |
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|
170 | 188 | END IF; |
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171 | 189 | END PROCESS; |
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