##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.
Alexis -
r20:4ef18b3e796e default
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,5
1 vhdl lpp "../../lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd"
2 vhdl lpp "../../lib/lpp/general_purpose/general_purpose.vhd"
3 vhdl lpp "../../lib/lpp/lpp_ad_Conv/AD7688_spi_if.vhd"
4 vhdl lpp "../../lib/lpp/general_purpose/Clk_divider.vhd"
5 vhdl lpp "../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd"
Show file before | Show file after | Hide comments
@@ -0,0 +1,12
1 vhdl grlib "../../lib/grlib/stdlib/version.vhd"
2 vhdl grlib "../../lib/grlib/stdlib/stdlib.vhd"
3 vhdl grlib "../../lib/grlib/stdlib/config.vhd"
4 vhdl grlib "../../lib/grlib/amba/amba.vhd"
5 vhdl grlib "../../lib/grlib/amba/devices.vhd"
6 vhdl lpp "../../lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd"
7 vhdl lpp "../../lib/lpp/general_purpose/general_purpose.vhd"
8 vhdl lpp "../../lib/lpp/lpp_ad_Conv/AD7688_spi_if.vhd"
9 vhdl lpp "../../lib/lpp/general_purpose/Clk_divider.vhd"
10 vhdl lpp "../../lib/lpp/lpp_amba/lpp_amba.vhd"
11 vhdl lpp "../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd"
12 vhdl lpp "../../lib/lpp/lpp_ad_Conv/lpp_apb_ad_conv.vhd"
Show file before | Show file after | Hide comments
@@ -0,0 +1,12
1 vhdl grlib "/opt/GRLIB/grlib-gpl-1.1.0-b4104/lib/grlib/stdlib/version.vhd"
2 vhdl grlib "/opt/GRLIB/grlib-gpl-1.1.0-b4104/lib/grlib/stdlib/stdlib.vhd"
3 vhdl grlib "/opt/GRLIB/grlib-gpl-1.1.0-b4104/lib/grlib/stdlib/config.vhd"
4 vhdl grlib "/opt/GRLIB/grlib-gpl-1.1.0-b4104/lib/grlib/amba/amba.vhd"
5 vhdl grlib "/opt/GRLIB/grlib-gpl-1.1.0-b4104/lib/grlib/amba/devices.vhd"
6 vhdl lpp "/opt/GRLIB/grlib-gpl-1.1.0-b4104/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd"
7 vhdl lpp "/opt/GRLIB/grlib-gpl-1.1.0-b4104/lib/lpp/general_purpose/general_purpose.vhd"
8 vhdl lpp "/opt/GRLIB/grlib-gpl-1.1.0-b4104/lib/lpp/lpp_ad_Conv/AD7688_spi_if.vhd"
9 vhdl lpp "/opt/GRLIB/grlib-gpl-1.1.0-b4104/lib/lpp/general_purpose/Clk_divider.vhd"
10 vhdl lpp "/opt/GRLIB/grlib-gpl-1.1.0-b4104/lib/lpp/lpp_amba/lpp_amba.vhd"
11 vhdl lpp "/opt/GRLIB/grlib-gpl-1.1.0-b4104/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd"
12 vhdl lpp "/opt/GRLIB/grlib-gpl-1.1.0-b4104/lib/lpp/lpp_ad_Conv/lpp_apb_ad_conv.vhd"
Show file before | Show file after | Hide comments
@@ -0,0 +1,12
1 <?xml version="1.0" encoding="UTF-8"?>
2 <drawing version="7">
3 <attr value="spartan3e" name="DeviceFamilyName">
4 <trait delete="all:0" />
5 <trait editname="all:0" />
6 <trait edittrait="all:0" />
7 </attr>
8 <netlist>
9 </netlist>
10 <sheet sheetnum="1" width="3520" height="2720">
11 </sheet>
12 </drawing> No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,75
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 library IEEE;
20 use IEEE.STD_LOGIC_1164.ALL;
21 library lpp;
22 use lpp.lpp_ad_conv.all;
23 use lpp.general_purpose.Clk_divider;
24
25 entity AD7688_spi_if is
26 generic(ChanelCount : integer);
27 Port( clk : in STD_LOGIC;
28 reset : in STD_LOGIC;
29 cnv : in STD_LOGIC;
30 DataReady: out std_logic;
31 sdi : in AD7688_in(ChanelCount-1 downto 0);
32 smpout : out Samples_out(ChanelCount-1 downto 0)
33 );
34 end AD7688_spi_if;
35
36 architecture ar_AD7688_spi_if of AD7688_spi_if is
37
38 signal shift_reg : Samples_out(ChanelCount-1 downto 0);
39 signal i : integer range 0 to 15 :=0;
40 signal cnv_reg : std_logic := '0';
41
42 begin
43
44
45
46 process(clk,reset)
47 begin
48 if reset = '0' then
49 for l in 0 to ChanelCount-1 loop
50 shift_reg(l) <= (others => '0');
51 end loop;
52 i <= 0;
53 cnv_reg <= '0';
54 elsif clk'event and clk = '1' then
55 if cnv = '0' and cnv_reg = '0' then
56 if i = 15 then
57 i <= 0;
58 cnv_reg <= '1';
59 else
60 DataReady <= '0';
61 i <= i+1;
62 for l in 0 to ChanelCount-1 loop
63 shift_reg(l)(0) <= sdi(l).SDI;
64 shift_reg(l)(15 downto 1) <= shift_reg(l)(14 downto 0);
65 end loop;
66 end if;
67 else
68 cnv_reg <= not cnv;
69 smpout <= shift_reg;
70 DataReady <= '1';
71 end if;
72 end if;
73 end process;
74
75 end ar_AD7688_spi_if;
Show file before | Show file after | Hide comments
@@ -0,0 +1,102
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 library IEEE;
20 use IEEE.STD_LOGIC_1164.ALL;
21 library lpp;
22 use lpp.lpp_ad_conv.all;
23 use lpp.general_purpose.Clk_divider;
24
25 entity ADS7886_drvr is
26 generic(ChanelCount : integer;
27 clkkHz : integer);
28 Port ( clk : in STD_LOGIC;
29 reset : in STD_LOGIC;
30 smplClk: in STD_LOGIC;
31 DataReady : out std_logic;
32 smpout : out Samples_out(ChanelCount-1 downto 0);
33 AD_in : in AD7688_in(ChanelCount-1 downto 0);
34 AD_out : out AD7688_out);
35 end ADS7886_drvr;
36
37 architecture ar_ADS7886_drvr of ADS7886_drvr is
38
39 constant convTrigger : integer:= clkkHz*1/1000; --tconv = 1.6µs
40
41 signal i : integer range 0 to convTrigger :=0;
42 signal clk_int : std_logic;
43 signal smplClk_reg : std_logic;
44 signal cnv_int : std_logic;
45 signal smpout_int : Samples_out(ChanelCount-1 downto 0);
46
47
48 begin
49
50
51 clkdiv: if clkkHz>=20000 generate
52 clkdivider: Clk_divider
53 generic map(clkkHz*1000,19000000)
54 Port map( clk ,reset,clk_int);
55 end generate;
56
57
58 clknodiv: if clkkHz<20000 generate
59 nodiv: clk_int <= clk;
60 end generate;
61
62 AD_out.CNV <= cnv_int;
63 AD_out.SCK <= clk_int;
64
65
66 sckgen: process(clk,reset)
67 begin
68 if reset = '0' then
69 i <= 0;
70 cnv_int <= '0';
71 smplClk_reg <= '0';
72 elsif clk'event and clk = '1' then
73 if smplClk = '1' and smplClk_reg = '0' then
74 if i = convTrigger then
75 smplClk_reg <= '1';
76 i <= 0;
77 cnv_int <= '0';
78 else
79 i <= i+1;
80 cnv_int <= '1';
81 end if;
82 elsif smplClk = '0' and smplClk_reg = '1' then
83 smplClk_reg <= '0';
84 end if;
85 end if;
86 end process;
87
88
89 NDMSK: for i in 0 to ChanelCount-1
90 generate
91 smpout(i) <= smpout_int(i) and X"0FFF";
92 end generate;
93
94
95 spidrvr: AD7688_spi_if
96 generic map(ChanelCount)
97 Port map(clk_int,reset,cnv_int,DataReady,AD_in,smpout_int);
98
99
100
101 end ar_ADS7886_drvr;
102
Show file before | Show file after | Hide comments
@@ -0,0 +1,142
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 library IEEE;
20 use IEEE.STD_LOGIC_1164.ALL;
21 use ieee.numeric_std.all;
22 library grlib;
23 use grlib.amba.all;
24 use grlib.stdlib.all;
25 use grlib.devices.all;
26 library lpp;
27 use lpp.lpp_ad_conv.all;
28 use lpp.lpp_amba.all;
29 use lpp.general_purpose.Clk_divider;
30
31 entity lpp_apb_ad_conv is
32 generic(
33 pindex : integer := 0;
34 paddr : integer := 0;
35 pmask : integer := 16#fff#;
36 pirq : integer := 0;
37 abits : integer := 8;
38 ChanelCount : integer := 1;
39 clkkHz : integer := 50000;
40 smpClkHz : integer := 100;
41 ADCref : integer := AD7688);
42 Port (
43 clk : in STD_LOGIC;
44 reset : in STD_LOGIC;
45 apbi : in apb_slv_in_type;
46 apbo : out apb_slv_out_type;
47 AD_in : in AD7688_in(ChanelCount-1 downto 0);
48 AD_out : out AD7688_out);
49 end lpp_apb_ad_conv;
50
51
52 architecture ar_lpp_apb_ad_conv of lpp_apb_ad_conv is
53 constant REVISION : integer := 1;
54
55 constant pconfig : apb_config_type := (
56 0 => ahb_device_reg (VENDOR_LPP, LPP_ADC_7688, 0, REVISION, 0),
57 1 => apb_iobar(paddr, pmask));
58
59 signal Rdata : std_logic_vector(31 downto 0);
60 signal smpout : Samples_out(ChanelCount-1 downto 0);
61 signal smplClk : STD_LOGIC;
62 signal DataReady : STD_LOGIC;
63
64 type lpp_apb_ad_conv_Reg is record
65 CTRL_Reg : std_logic_vector(31 downto 0);
66 sample : Samples_out(ChanelCount-1 downto 0);
67 end record;
68
69 signal r : lpp_apb_ad_conv_Reg;
70
71 begin
72
73
74 caseAD7688: if ADCref = AD7688 generate
75 AD7688: AD7688_drvr
76 generic map(ChanelCount,clkkHz)
77 Port map(clk,reset,smplClk,DataReady,smpout,AD_in,AD_out);
78 end generate;
79
80 caseADS786: if ADCref = ADS7886 generate
81 ADS7886: ADS7886_drvr
82 generic map(ChanelCount,clkkHz)
83 Port map(clk,reset,smplClk,DataReady,smpout,AD_in,AD_out);
84 end generate;
85
86
87 clkdivider: Clk_divider
88 generic map(clkkHz*1000,smpClkHz)
89 Port map( clk ,reset,smplClk);
90
91
92
93 r.CTRL_Reg(0) <= DataReady;
94
95 r.sample <= smpout;
96
97
98 process(reset,clk)
99 begin
100 if reset = '0' then
101 --r.CTRL_Reg(9 downto 0) <= (others => '0');
102 elsif clk'event and clk = '1' then
103
104 --APB Write OP
105 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
106 case apbi.paddr(7 downto 2) is
107 when "000000" =>
108 --r.CTRL_Reg(9 downto 0) <= apbi.pwdata(9 downto 0);
109 when others =>
110 end case;
111 end if;
112
113 --APB READ OP
114 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
115 case apbi.paddr(7 downto 2) is
116 when "000000" =>
117 Rdata <= r.CTRL_Reg;
118 when others =>
119 readC: for i in 1 to ChanelCount loop
120 if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then
121 Rdata(15 downto 0) <= r.sample(i-1)(15 downto 0);
122 end if;
123 end loop;
124 end case;
125 end if;
126 end if;
127 apbo.pconfig <= pconfig;
128 end process;
129
130 apbo.prdata <= Rdata when apbi.penable = '1' ;
131
132
133 end ar_lpp_apb_ad_conv;
134
135
136
137
138
139
140
141
142
Show file before | Show file after | Hide comments
@@ -1,148 +1,193
1 <?xml version='1.0' encoding='utf-8'?>
1 <?xml version='1.0' encoding='utf-8'?>
2 <!--This is an ISE project configuration file.-->
2 <!--This is an ISE project configuration file.-->
3 <!--It holds project specific layout data for the projectmgr plugin.-->
3 <!--It holds project specific layout data for the projectmgr plugin.-->
4 <!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
4 <!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
5 <Project version="2" owner="projectmgr" name="leon3mp" >
5 <Project version="2" owner="projectmgr" name="leon3mp" >
6 <!--This is an ISE project configuration file.-->
6 <!--This is an ISE project configuration file.-->
7 <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
7 <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
8 <ClosedNodes>
8 <ClosedNodes>
9 <ClosedNodesVersion>2</ClosedNodesVersion>
9 <ClosedNodesVersion>2</ClosedNodesVersion>
10 <ClosedNode>/Unassigned User Library Modules</ClosedNode>
10 <ClosedNode>/Unassigned User Library Modules</ClosedNode>
11 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/LCD0 - apb_lcd_ctrlr - Behavioral</ClosedNode>
12 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/addr_pad - outpadv - rtl</ClosedNode>
13 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/ahbjtag0 - ahbjtag - struct</ClosedNode>
14 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/ahbram0 - ahbram - rtl</ClosedNode>
15 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/clk_pad - clkpad - rtl</ClosedNode>
16 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/clkgen0 - clkgen - struct</ClosedNode>
17 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/dcom0 - ahbuart - struct</ClosedNode>
18 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/ddrc - ddrspa - rtl</ClosedNode>
19 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/dsu0 - dsu3 - rtl</ClosedNode>
20 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/dsubre_pad - inpad - rtl</ClosedNode>
21 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/dsurx_pad - inpad - rtl</ClosedNode>
22 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/dsutx_pad - outpad - rtl</ClosedNode>
23 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/e1 - grethm - rtl</ClosedNode>
24 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/emdc_pad - outpad - rtl</ClosedNode>
25 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/emdio_pad - iopad - rtl</ClosedNode>
26 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/error_pad - odpad - rtl</ClosedNode>
27 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/erxc_pad - inpad - rtl</ClosedNode>
28 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/erxco_pad - inpad - rtl</ClosedNode>
29 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/erxcr_pad - inpad - rtl</ClosedNode>
30 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/erxd_pad - inpadv - rtl</ClosedNode>
31 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/erxdv_pad - inpad - rtl</ClosedNode>
32 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/erxer_pad - inpad - rtl</ClosedNode>
33 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/etxc_pad - inpad - rtl</ClosedNode>
34 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/etxd_pad - outpadv - rtl</ClosedNode>
35 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/etxen_pad - outpad - rtl</ClosedNode>
36 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/etxer_pad - outpad - rtl</ClosedNode>
37 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/horiz_sync_pad - outpad - rtl</ClosedNode>
38 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/kbdata_pad - iopad - rtl</ClosedNode>
39 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/kbdclk_pad - iopad - rtl</ClosedNode>
40 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/oen_pad - outpad - rtl</ClosedNode>
41 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/roms_pad - outpad - rtl</ClosedNode>
42 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/serrx_pad - inpad - rtl</ClosedNode>
43 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/sertx_pad - outpad - rtl</ClosedNode>
44 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/sr1 - mctrl - rtl</ClosedNode>
45 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/svga0 - svgactrl - rtl</ClosedNode>
46 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/u0 - leon3s - rtl</ClosedNode>
47 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/vert_sync_pad - outpad - rtl</ClosedNode>
48 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/video_out_b_pad - outpad - rtl</ClosedNode>
49 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/video_out_g_pad - outpad - rtl</ClosedNode>
50 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/video_out_r_pad - outpad - rtl</ClosedNode>
51 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-APB_LCD-digilent-xc3s1600e|leon3mp.vhd/wri_pad - outpad - rtl</ClosedNode>
11 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/LCD0 - apb_lcd_ctrlr - Behavioral</ClosedNode>
52 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/LCD0 - apb_lcd_ctrlr - Behavioral</ClosedNode>
12 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/addr_pad - outpadv - rtl</ClosedNode>
53 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/addr_pad - outpadv - rtl</ClosedNode>
13 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/ahbjtag0 - ahbjtag - struct</ClosedNode>
54 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/ahbjtag0 - ahbjtag - struct</ClosedNode>
14 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/ahbram0 - ahbram - rtl</ClosedNode>
55 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/ahbram0 - ahbram - rtl</ClosedNode>
15 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/clk_pad - clkpad - rtl</ClosedNode>
56 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/clk_pad - clkpad - rtl</ClosedNode>
16 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/clkgen0 - clkgen - struct</ClosedNode>
57 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/clkgen0 - clkgen - struct</ClosedNode>
17 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/data_pad - iopadv - rtl</ClosedNode>
58 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/data_pad - iopadv - rtl</ClosedNode>
18 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/dcom0 - ahbuart - struct</ClosedNode>
59 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/dcom0 - ahbuart - struct</ClosedNode>
19 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/ddrc - ddrspa - rtl</ClosedNode>
60 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/ddrc - ddrspa - rtl</ClosedNode>
20 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/dsu0 - dsu3 - rtl</ClosedNode>
61 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/dsu0 - dsu3 - rtl</ClosedNode>
21 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/dsubre_pad - inpad - rtl</ClosedNode>
62 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/dsubre_pad - inpad - rtl</ClosedNode>
22 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/dsurx_pad - inpad - rtl</ClosedNode>
63 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/dsurx_pad - inpad - rtl</ClosedNode>
23 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/dsutx_pad - outpad - rtl</ClosedNode>
64 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/dsutx_pad - outpad - rtl</ClosedNode>
24 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/e1 - grethm - rtl</ClosedNode>
65 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/e1 - grethm - rtl</ClosedNode>
25 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/emdc_pad - outpad - rtl</ClosedNode>
66 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/emdc_pad - outpad - rtl</ClosedNode>
26 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/emdio_pad - iopad - rtl</ClosedNode>
67 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/emdio_pad - iopad - rtl</ClosedNode>
27 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/error_pad - odpad - rtl</ClosedNode>
68 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/error_pad - odpad - rtl</ClosedNode>
28 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/erxc_pad - inpad - rtl</ClosedNode>
69 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/erxc_pad - inpad - rtl</ClosedNode>
29 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/erxco_pad - inpad - rtl</ClosedNode>
70 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/erxco_pad - inpad - rtl</ClosedNode>
30 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/erxcr_pad - inpad - rtl</ClosedNode>
71 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/erxcr_pad - inpad - rtl</ClosedNode>
31 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/erxd_pad - inpadv - rtl</ClosedNode>
72 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/erxd_pad - inpadv - rtl</ClosedNode>
32 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/erxdv_pad - inpad - rtl</ClosedNode>
73 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/erxdv_pad - inpad - rtl</ClosedNode>
33 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/erxer_pad - inpad - rtl</ClosedNode>
74 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/erxer_pad - inpad - rtl</ClosedNode>
34 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/etxc_pad - inpad - rtl</ClosedNode>
75 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/etxc_pad - inpad - rtl</ClosedNode>
35 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/etxd_pad - outpadv - rtl</ClosedNode>
76 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/etxd_pad - outpadv - rtl</ClosedNode>
36 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/etxen_pad - outpad - rtl</ClosedNode>
77 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/etxen_pad - outpad - rtl</ClosedNode>
37 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/etxer_pad - outpad - rtl</ClosedNode>
78 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/etxer_pad - outpad - rtl</ClosedNode>
38 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/horiz_sync_pad - outpad - rtl</ClosedNode>
79 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/horiz_sync_pad - outpad - rtl</ClosedNode>
39 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/kbdata_pad - iopad - rtl</ClosedNode>
80 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/kbdata_pad - iopad - rtl</ClosedNode>
40 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/kbdclk_pad - iopad - rtl</ClosedNode>
81 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/kbdclk_pad - iopad - rtl</ClosedNode>
41 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/oen_pad - outpad - rtl</ClosedNode>
82 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/oen_pad - outpad - rtl</ClosedNode>
42 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/roms_pad - outpad - rtl</ClosedNode>
83 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/roms_pad - outpad - rtl</ClosedNode>
43 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/serrx_pad - inpad - rtl</ClosedNode>
84 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/serrx_pad - inpad - rtl</ClosedNode>
44 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/sertx_pad - outpad - rtl</ClosedNode>
85 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/sertx_pad - outpad - rtl</ClosedNode>
45 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/sr1 - mctrl - rtl</ClosedNode>
86 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/sr1 - mctrl - rtl</ClosedNode>
46 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/svga0 - svgactrl - rtl</ClosedNode>
87 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/svga0 - svgactrl - rtl</ClosedNode>
47 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/u0 - leon3s - rtl</ClosedNode>
88 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/u0 - leon3s - rtl</ClosedNode>
48 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/vert_sync_pad - outpad - rtl</ClosedNode>
89 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/vert_sync_pad - outpad - rtl</ClosedNode>
49 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/video_out_b_pad - outpad - rtl</ClosedNode>
90 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/video_out_b_pad - outpad - rtl</ClosedNode>
50 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/video_out_g_pad - outpad - rtl</ClosedNode>
91 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/video_out_g_pad - outpad - rtl</ClosedNode>
51 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/video_out_r_pad - outpad - rtl</ClosedNode>
92 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/video_out_r_pad - outpad - rtl</ClosedNode>
52 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/wri_pad - outpad - rtl</ClosedNode>
93 <ClosedNode>/leon3mp - rtl |opt|GRLIB|grlib-gpl-1.1.0-b4104|designs|leon3-digilent-xc3s1600e|leon3mp.vhd/wri_pad - outpad - rtl</ClosedNode>
53 </ClosedNodes>
94 </ClosedNodes>
54 <SelectedItems>
95 <SelectedItems>
55 <SelectedItem>leon3mp - rtl (/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-digilent-xc3s1600e/leon3mp.vhd)</SelectedItem>
96 <SelectedItem>clkdivider - Clk_divider - ar_Clk_divider (/opt/GRLIB/grlib-gpl-1.1.0-b4104/lib/lpp/general_purpose/Clk_divider.vhd)</SelectedItem>
56 </SelectedItems>
97 </SelectedItems>
57 <ScrollbarPosition orientation="vertical" >33</ScrollbarPosition>
98 <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
58 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
99 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
59 <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000278000000020000000000000000000000000000000064ffffffff000000810000000000000002000002780000000100000000000000000000000100000000</ViewHeaderState>
100 <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002be000000020000000000000000000000000000000064ffffffff000000810000000000000002000002be0000000100000000000000000000000100000000</ViewHeaderState>
60 <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
101 <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
61 <CurrentItem>leon3mp - rtl (/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-digilent-xc3s1600e/leon3mp.vhd)</CurrentItem>
102 <CurrentItem>clkdivider - Clk_divider - ar_Clk_divider (/opt/GRLIB/grlib-gpl-1.1.0-b4104/lib/lpp/general_purpose/Clk_divider.vhd)</CurrentItem>
62 </ItemView>
103 </ItemView>
63 <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
104 <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
64 <ClosedNodes>
105 <ClosedNodes>
65 <ClosedNodesVersion>1</ClosedNodesVersion>
106 <ClosedNodesVersion>1</ClosedNodesVersion>
107 <ClosedNode>Configure Target Device</ClosedNode>
66 <ClosedNode>Design Utilities</ClosedNode>
108 <ClosedNode>Design Utilities</ClosedNode>
109 <ClosedNode>Implement Design</ClosedNode>
67 <ClosedNode>Implement Design/Map</ClosedNode>
110 <ClosedNode>Implement Design/Map</ClosedNode>
68 <ClosedNode>Implement Design/Place &amp; Route</ClosedNode>
111 <ClosedNode>Implement Design/Place &amp; Route</ClosedNode>
69 <ClosedNode>Implement Design/Translate</ClosedNode>
112 <ClosedNode>Implement Design/Translate</ClosedNode>
70 <ClosedNode>Synthesize - XST</ClosedNode>
113 <ClosedNode>Synthesize - XST</ClosedNode>
71 <ClosedNode>User Constraints</ClosedNode>
114 <ClosedNode>User Constraints</ClosedNode>
72 </ClosedNodes>
115 </ClosedNodes>
73 <SelectedItems>
116 <SelectedItems>
74 <SelectedItem>Configure Target Device</SelectedItem>
117 <SelectedItem></SelectedItem>
75 </SelectedItems>
118 </SelectedItems>
76 <ScrollbarPosition orientation="vertical" >7</ScrollbarPosition>
119 <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
77 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
120 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
78 <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000177000000010000000100000000000000000000000064ffffffff000000810000000000000001000001770000000100000000</ViewHeaderState>
121 <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000163000000010000000100000000000000000000000064ffffffff000000810000000000000001000001630000000100000000</ViewHeaderState>
79 <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
122 <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
80 <CurrentItem>Configure Target Device</CurrentItem>
123 <CurrentItem></CurrentItem>
81 </ItemView>
124 </ItemView>
82 <ItemView guiview="File" >
125 <ItemView guiview="File" >
83 <ClosedNodes>
126 <ClosedNodes>
84 <ClosedNodesVersion>1</ClosedNodesVersion>
127 <ClosedNodesVersion>1</ClosedNodesVersion>
85 </ClosedNodes>
128 </ClosedNodes>
86 <SelectedItems/>
129 <SelectedItems>
87 <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
130 <SelectedItem>../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd</SelectedItem>
131 </SelectedItems>
132 <ScrollbarPosition orientation="vertical" >178</ScrollbarPosition>
88 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
133 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
89 <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000598000000040101000100000000000000000000000064ffffffff000000810000000000000004000001970000000100000000000000d60000000100000000000000840000000100000000000002a70000000100000000</ViewHeaderState>
134 <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000598000000040101000100000000000000000000000064ffffffff000000810000000000000004000001970000000100000000000000d60000000100000000000000840000000100000000000002a70000000100000000</ViewHeaderState>
90 <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
135 <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
91 <CurrentItem>../../lib/cypress/ssram/components.vhd</CurrentItem>
136 <CurrentItem>../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd</CurrentItem>
92 </ItemView>
137 </ItemView>
93 <ItemView guiview="Library" >
138 <ItemView guiview="Library" >
94 <ClosedNodes>
139 <ClosedNodes>
95 <ClosedNodesVersion>1</ClosedNodesVersion>
140 <ClosedNodesVersion>1</ClosedNodesVersion>
96 <ClosedNode>cypress</ClosedNode>
141 <ClosedNode>cypress</ClosedNode>
97 <ClosedNode>dw02</ClosedNode>
142 <ClosedNode>dw02</ClosedNode>
98 <ClosedNode>esa</ClosedNode>
143 <ClosedNode>esa</ClosedNode>
99 <ClosedNode>eth</ClosedNode>
144 <ClosedNode>eth</ClosedNode>
100 <ClosedNode>fmf</ClosedNode>
145 <ClosedNode>fmf</ClosedNode>
101 <ClosedNode>gaisler</ClosedNode>
146 <ClosedNode>gaisler</ClosedNode>
102 <ClosedNode>gsi</ClosedNode>
147 <ClosedNode>gsi</ClosedNode>
103 <ClosedNode>hynix</ClosedNode>
148 <ClosedNode>hynix</ClosedNode>
104 <ClosedNode>micron</ClosedNode>
149 <ClosedNode>micron</ClosedNode>
105 <ClosedNode>synplify</ClosedNode>
150 <ClosedNode>synplify</ClosedNode>
106 <ClosedNode>techmap</ClosedNode>
151 <ClosedNode>techmap</ClosedNode>
107 <ClosedNode>unisim</ClosedNode>
152 <ClosedNode>unisim</ClosedNode>
108 </ClosedNodes>
153 </ClosedNodes>
109 <SelectedItems>
154 <SelectedItems>
110 <SelectedItem>../../lib/lpp/lpp_amba/lpp_amba.vhd</SelectedItem>
155 <SelectedItem>../../lib/lpp/lpp_ad_Conv/lpp_apb_ad_conv.vhd</SelectedItem>
111 </SelectedItems>
156 </SelectedItems>
112 <ScrollbarPosition orientation="vertical" >43</ScrollbarPosition>
157 <ScrollbarPosition orientation="vertical" >66</ScrollbarPosition>
113 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
158 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
114 <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000177000000010001000100000000000000000000000064ffffffff000000810000000000000001000001770000000100000000</ViewHeaderState>
159 <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000119000000010001000100000000000000000000000064ffffffff000000810000000000000001000001190000000100000000</ViewHeaderState>
115 <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
160 <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
116 <CurrentItem>../../lib/lpp/lpp_amba/lpp_amba.vhd</CurrentItem>
161 <CurrentItem>../../lib/lpp/lpp_ad_Conv/lpp_apb_ad_conv.vhd</CurrentItem>
117 </ItemView>
162 </ItemView>
118 <SourceProcessView>000000ff0000000000000002000001f4000000b001000000060100000002</SourceProcessView>
163 <SourceProcessView>000000ff0000000000000002000001f4000000b001000000060100000002</SourceProcessView>
119 <CurrentView>Implementation</CurrentView>
164 <CurrentView>Implementation</CurrentView>
120 <ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
165 <ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
121 <ClosedNodes>
166 <ClosedNodes>
122 <ClosedNodesVersion>1</ClosedNodesVersion>
167 <ClosedNodesVersion>1</ClosedNodesVersion>
123 <ClosedNode>User Constraints</ClosedNode>
168 <ClosedNode>User Constraints</ClosedNode>
124 </ClosedNodes>
169 </ClosedNodes>
125 <SelectedItems>
170 <SelectedItems>
126 <SelectedItem/>
171 <SelectedItem/>
127 </SelectedItems>
172 </SelectedItems>
128 <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
173 <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
129 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
174 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
130 <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000fd000000010000000100000000000000000000000064ffffffff000000810000000000000001000000fd0000000100000000</ViewHeaderState>
175 <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000138000000010000000100000000000000000000000064ffffffff000000810000000000000001000001380000000100000000</ViewHeaderState>
131 <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
176 <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
132 <CurrentItem/>
177 <CurrentItem/>
133 </ItemView>
178 </ItemView>
134 <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
179 <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
135 <ClosedNodes>
180 <ClosedNodes>
136 <ClosedNodesVersion>1</ClosedNodesVersion>
181 <ClosedNodesVersion>1</ClosedNodesVersion>
137 <ClosedNode>Design Utilities</ClosedNode>
182 <ClosedNode>Design Utilities</ClosedNode>
138 </ClosedNodes>
183 </ClosedNodes>
139 <SelectedItems>
184 <SelectedItems>
140 <SelectedItem/>
185 <SelectedItem/>
141 </SelectedItems>
186 </SelectedItems>
142 <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
187 <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
143 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
188 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
144 <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000fd000000010000000100000000000000000000000064ffffffff000000810000000000000001000000fd0000000100000000</ViewHeaderState>
189 <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000fd000000010000000100000000000000000000000064ffffffff000000810000000000000001000000fd0000000100000000</ViewHeaderState>
145 <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
190 <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
146 <CurrentItem/>
191 <CurrentItem/>
147 </ItemView>
192 </ItemView>
148 </Project>
193 </Project>
Show file before | Show file after | Hide comments
@@ -1,217 +1,217
1 <?xml version='1.0' encoding='UTF-8'?>
1 <?xml version='1.0' encoding='UTF-8'?>
2 <report-views version="2.0" >
2 <report-views version="2.0" >
3 <header>
3 <header>
4 <DateModified>2010-11-22T09:58:07</DateModified>
4 <DateModified>2010-12-02T07:02:18</DateModified>
5 <ModuleName>leon3mp</ModuleName>
5 <ModuleName>leon3mp</ModuleName>
6 <SummaryTimeStamp>Unknown</SummaryTimeStamp>
6 <SummaryTimeStamp>Unknown</SummaryTimeStamp>
7 <SavedFilePath>/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-digilent-xc3s1600e/iseconfig/leon3mp.xreport</SavedFilePath>
7 <SavedFilePath>/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-APB_LCD-digilent-xc3s1600e/iseconfig/leon3mp.xreport</SavedFilePath>
8 <ImplementationReportsDirectory>/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-digilent-xc3s1600e/</ImplementationReportsDirectory>
8 <ImplementationReportsDirectory>/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-APB_LCD-digilent-xc3s1600e/</ImplementationReportsDirectory>
9 <DateInitialized>2010-11-19T08:25:19</DateInitialized>
9 <DateInitialized>2010-11-19T08:25:19</DateInitialized>
10 <EnableMessageFiltering>false</EnableMessageFiltering>
10 <EnableMessageFiltering>false</EnableMessageFiltering>
11 </header>
11 </header>
12 <body>
12 <body>
13 <viewgroup label="Design Overview" >
13 <viewgroup label="Design Overview" >
14 <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="leon3mp_summary.html" label="Summary" >
14 <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="leon3mp_summary.html" label="Summary" >
15 <toc-item title="Design Overview" target="Design Overview" />
15 <toc-item title="Design Overview" target="Design Overview" />
16 <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
16 <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
17 <toc-item title="Performance Summary" target="Performance Summary" />
17 <toc-item title="Performance Summary" target="Performance Summary" />
18 <toc-item title="Failing Constraints" target="Failing Constraints" />
18 <toc-item title="Failing Constraints" target="Failing Constraints" />
19 <toc-item title="Detailed Reports" target="Detailed Reports" />
19 <toc-item title="Detailed Reports" target="Detailed Reports" />
20 </view>
20 </view>
21 <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="leon3mp_envsettings.html" label="System Settings" />
21 <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="leon3mp_envsettings.html" label="System Settings" />
22 <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="leon3mp_map.xrpt" label="IOB Properties" />
22 <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="leon3mp_map.xrpt" label="IOB Properties" />
23 <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="leon3mp_map.xrpt" label="Control Set Information" />
23 <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="leon3mp_map.xrpt" label="Control Set Information" />
24 <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="leon3mp_map.xrpt" label="Module Level Utilization" />
24 <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="leon3mp_map.xrpt" label="Module Level Utilization" />
25 <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="leon3mp.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
25 <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="leon3mp.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
26 <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="leon3mp_par.xrpt" label="Pinout Report" />
26 <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="leon3mp_par.xrpt" label="Pinout Report" />
27 <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="leon3mp_par.xrpt" label="Clock Report" />
27 <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="leon3mp_par.xrpt" label="Clock Report" />
28 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="leon3mp.twx" label="Static Timing" />
28 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="leon3mp.twx" label="Static Timing" />
29 <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="leon3mp_html/fit/report.htm" label="CPLD Fitter Report" />
29 <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="leon3mp_html/fit/report.htm" label="CPLD Fitter Report" />
30 <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="leon3mp_html/tim/report.htm" label="CPLD Timing Report" />
30 <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="leon3mp_html/tim/report.htm" label="CPLD Timing Report" />
31 </viewgroup>
31 </viewgroup>
32 <viewgroup label="XPS Errors and Warnings" >
32 <viewgroup label="XPS Errors and Warnings" >
33 <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
33 <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
34 <view program="libgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/libgen.xmsgs" label="Libgen Messages" />
34 <view program="libgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/libgen.xmsgs" label="Libgen Messages" />
35 <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
35 <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
36 <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
36 <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
37 </viewgroup>
37 </viewgroup>
38 <viewgroup label="XPS Reports" >
38 <viewgroup label="XPS Reports" >
39 <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
39 <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
40 <view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="libgen.log" label="Libgen Log File" />
40 <view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="libgen.log" label="Libgen Log File" />
41 <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
41 <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
42 <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
42 <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
43 <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="leon3mp.log" label="System Log File" />
43 <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="leon3mp.log" label="System Log File" />
44 </viewgroup>
44 </viewgroup>
45 <viewgroup label="Errors and Warnings" >
45 <viewgroup label="Errors and Warnings" >
46 <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
46 <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
47 <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
47 <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
48 <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
48 <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
49 <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
49 <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
50 <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
50 <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
51 <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
51 <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
52 <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
52 <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
53 <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
53 <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
54 <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
54 <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
55 <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
55 <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
56 <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
56 <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
57 </viewgroup>
57 </viewgroup>
58 <viewgroup label="Detailed Reports" >
58 <viewgroup label="Detailed Reports" >
59 <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="leon3mp.syr" label="Synthesis Report" >
59 <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="leon3mp.syr" label="Synthesis Report" >
60 <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
60 <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
61 <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
61 <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
62 <toc-item title="HDL Compilation" target=" HDL Compilation " />
62 <toc-item title="HDL Compilation" target=" HDL Compilation " />
63 <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
63 <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
64 <toc-item title="HDL Analysis" target=" HDL Analysis " />
64 <toc-item title="HDL Analysis" target=" HDL Analysis " />
65 <toc-item title="HDL Parsing" target=" HDL Parsing " />
65 <toc-item title="HDL Parsing" target=" HDL Parsing " />
66 <toc-item title="HDL Elaboration" target=" HDL Elaboration " />
66 <toc-item title="HDL Elaboration" target=" HDL Elaboration " />
67 <toc-item title="HDL Synthesis" target=" HDL Synthesis " />
67 <toc-item title="HDL Synthesis" target=" HDL Synthesis " />
68 <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
68 <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
69 <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
69 <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
70 <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
70 <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
71 <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
71 <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
72 <toc-item title="Partition Report" target=" Partition Report " />
72 <toc-item title="Partition Report" target=" Partition Report " />
73 <toc-item title="Final Report" target=" Final Report " />
73 <toc-item title="Final Report" target=" Final Report " />
74 <toc-item title="Design Summary" target=" Design Summary " />
74 <toc-item title="Design Summary" target=" Design Summary " />
75 <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
75 <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
76 <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
76 <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
77 <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
77 <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
78 <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
78 <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
79 <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
79 <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
80 <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
80 <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
81 <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
81 <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
82 <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
82 <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
83 <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
83 <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
84 </view>
84 </view>
85 <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="leon3mp.srr" label="Synplify Report" />
85 <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="leon3mp.srr" label="Synplify Report" />
86 <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="leon3mp.prec_log" label="Precision Report" />
86 <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="leon3mp.prec_log" label="Precision Report" />
87 <view inputState="Synthesized" program="ngdbuild" type="Report" file="leon3mp.bld" label="Translation Report" >
87 <view inputState="Synthesized" program="ngdbuild" type="Report" file="leon3mp.bld" label="Translation Report" >
88 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
88 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
89 <toc-item title="Command Line" target="Command Line:" />
89 <toc-item title="Command Line" target="Command Line:" />
90 <toc-item title="Partition Status" target="Partition Implementation Status" />
90 <toc-item title="Partition Status" target="Partition Implementation Status" />
91 <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
91 <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
92 </view>
92 </view>
93 <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="leon3mp_map.mrp" label="Map Report" >
93 <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="leon3mp_map.mrp" label="Map Report" >
94 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
94 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
95 <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
95 <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
96 <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
96 <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
97 <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
97 <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
98 <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
98 <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
99 <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
99 <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
100 <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
100 <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
101 <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
101 <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
102 <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
102 <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
103 <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
103 <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
104 <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
104 <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
105 <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
105 <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
106 <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
106 <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
107 <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
107 <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
108 </view>
108 </view>
109 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="leon3mp.par" label="Place and Route Report" >
109 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="leon3mp.par" label="Place and Route Report" >
110 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
110 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
111 <toc-item title="Device Utilization" target="Device Utilization Summary:" />
111 <toc-item title="Device Utilization" target="Device Utilization Summary:" />
112 <toc-item title="Router Information" target="Starting Router" />
112 <toc-item title="Router Information" target="Starting Router" />
113 <toc-item title="Partition Status" target="Partition Implementation Status" />
113 <toc-item title="Partition Status" target="Partition Implementation Status" />
114 <toc-item title="Clock Report" target="Generating Clock Report" />
114 <toc-item title="Clock Report" target="Generating Clock Report" />
115 <toc-item title="Timing Results" target="Timing Score:" />
115 <toc-item title="Timing Results" target="Timing Score:" />
116 <toc-item title="Final Summary" target="Peak Memory Usage:" />
116 <toc-item title="Final Summary" target="Peak Memory Usage:" />
117 </view>
117 </view>
118 <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="leon3mp.twr" label="Post-PAR Static Timing Report" >
118 <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="leon3mp.twr" label="Post-PAR Static Timing Report" >
119 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
119 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
120 <toc-item title="Timing Report Description" target="Device,package,speed:" />
120 <toc-item title="Timing Report Description" target="Device,package,speed:" />
121 <toc-item title="Informational Messages" target="INFO:" />
121 <toc-item title="Informational Messages" target="INFO:" />
122 <toc-item title="Warning Messages" target="WARNING:" />
122 <toc-item title="Warning Messages" target="WARNING:" />
123 <toc-item title="Timing Constraints" target="Timing constraint:" />
123 <toc-item title="Timing Constraints" target="Timing constraint:" />
124 <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
124 <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
125 <toc-item title="Data Sheet Report" target="Data Sheet report:" />
125 <toc-item title="Data Sheet Report" target="Data Sheet report:" />
126 <toc-item title="Timing Summary" target="Timing summary:" />
126 <toc-item title="Timing Summary" target="Timing summary:" />
127 <toc-item title="Trace Settings" target="Trace Settings:" />
127 <toc-item title="Trace Settings" target="Trace Settings:" />
128 </view>
128 </view>
129 <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="leon3mp.rpt" label="CPLD Fitter Report (Text)" >
129 <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="leon3mp.rpt" label="CPLD Fitter Report (Text)" >
130 <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
130 <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
131 <toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
131 <toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
132 <toc-item title="Pin Resources" target="** Pin Resources **" />
132 <toc-item title="Pin Resources" target="** Pin Resources **" />
133 <toc-item title="Global Resources" target="** Global Control Resources **" />
133 <toc-item title="Global Resources" target="** Global Control Resources **" />
134 </view>
134 </view>
135 <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="leon3mp.tim" label="CPLD Timing Report (Text)" >
135 <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="leon3mp.tim" label="CPLD Timing Report (Text)" >
136 <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
136 <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
137 <toc-item title="Performance Summary" target="Performance Summary:" />
137 <toc-item title="Performance Summary" target="Performance Summary:" />
138 </view>
138 </view>
139 <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="leon3mp.pwr" label="Power Report" >
139 <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="leon3mp.pwr" label="Power Report" >
140 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
140 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
141 <toc-item title="Power summary" target="Power summary" />
141 <toc-item title="Power summary" target="Power summary" />
142 <toc-item title="Thermal summary" target="Thermal summary" />
142 <toc-item title="Thermal summary" target="Thermal summary" />
143 </view>
143 </view>
144 <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="leon3mp.bgn" label="Bitgen Report" >
144 <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="leon3mp.bgn" label="Bitgen Report" >
145 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
145 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
146 <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
146 <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
147 <toc-item title="Final Summary" target="DRC detected" />
147 <toc-item title="Final Summary" target="DRC detected" />
148 </view>
148 </view>
149 </viewgroup>
149 </viewgroup>
150 <viewgroup label="Secondary Reports" >
150 <viewgroup label="Secondary Reports" >
151 <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
151 <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
152 <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/leon3mp_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
152 <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/leon3mp_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
153 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
153 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
154 </view>
154 </view>
155 <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/leon3mp_translate.nlf" label="Post-Translate Simulation Model Report" >
155 <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/leon3mp_translate.nlf" label="Post-Translate Simulation Model Report" >
156 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
156 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
157 </view>
157 </view>
158 <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="leon3mp_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
158 <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="leon3mp_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
159 <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="leon3mp_map.map" label="Map Log File" >
159 <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="leon3mp_map.map" label="Map Log File" >
160 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
160 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
161 <toc-item title="Design Information" target="Design Information" />
161 <toc-item title="Design Information" target="Design Information" />
162 <toc-item title="Design Summary" target="Design Summary" />
162 <toc-item title="Design Summary" target="Design Summary" />
163 </view>
163 </view>
164 <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
164 <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
165 <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp_preroute.twr" label="Post-Map Static Timing Report" >
165 <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp_preroute.twr" label="Post-Map Static Timing Report" >
166 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
166 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
167 <toc-item title="Timing Report Description" target="Device,package,speed:" />
167 <toc-item title="Timing Report Description" target="Device,package,speed:" />
168 <toc-item title="Informational Messages" target="INFO:" />
168 <toc-item title="Informational Messages" target="INFO:" />
169 <toc-item title="Warning Messages" target="WARNING:" />
169 <toc-item title="Warning Messages" target="WARNING:" />
170 <toc-item title="Timing Constraints" target="Timing constraint:" />
170 <toc-item title="Timing Constraints" target="Timing constraint:" />
171 <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
171 <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
172 <toc-item title="Data Sheet Report" target="Data Sheet report:" />
172 <toc-item title="Data Sheet Report" target="Data Sheet report:" />
173 <toc-item title="Timing Summary" target="Timing summary:" />
173 <toc-item title="Timing Summary" target="Timing summary:" />
174 <toc-item title="Trace Settings" target="Trace Settings:" />
174 <toc-item title="Trace Settings" target="Trace Settings:" />
175 </view>
175 </view>
176 <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/leon3mp_map.nlf" label="Post-Map Simulation Model Report" />
176 <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/leon3mp_map.nlf" label="Post-Map Simulation Model Report" />
177 <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp_map.psr" label="Physical Synthesis Report" >
177 <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp_map.psr" label="Physical Synthesis Report" >
178 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
178 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
179 </view>
179 </view>
180 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="leon3mp_pad.txt" label="Pad Report" >
180 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="leon3mp_pad.txt" label="Pad Report" >
181 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
181 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
182 </view>
182 </view>
183 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="leon3mp.unroutes" label="Unroutes Report" >
183 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="leon3mp.unroutes" label="Unroutes Report" >
184 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
184 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
185 </view>
185 </view>
186 <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp_preroute.tsi" label="Post-Map Constraints Interaction Report" >
186 <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp_preroute.tsi" label="Post-Map Constraints Interaction Report" >
187 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
187 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
188 </view>
188 </view>
189 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.grf" label="Guide Results Report" />
189 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.grf" label="Guide Results Report" />
190 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.dly" label="Asynchronous Delay Report" />
190 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.dly" label="Asynchronous Delay Report" />
191 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.clk_rgn" label="Clock Region Report" />
191 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.clk_rgn" label="Clock Region Report" />
192 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.tsi" label="Post-Place and Route Constraints Interaction Report" >
192 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.tsi" label="Post-Place and Route Constraints Interaction Report" >
193 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
193 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
194 </view>
194 </view>
195 <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="leon3mp_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
195 <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="leon3mp_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
196 <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/leon3mp_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
196 <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/leon3mp_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
197 <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="leon3mp_sta.nlf" label="Primetime Netlist Report" >
197 <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="leon3mp_sta.nlf" label="Primetime Netlist Report" >
198 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
198 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
199 </view>
199 </view>
200 <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="leon3mp.ibs" label="IBIS Model" >
200 <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="leon3mp.ibs" label="IBIS Model" >
201 <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
201 <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
202 <toc-item title="Component" target="Component " />
202 <toc-item title="Component" target="Component " />
203 </view>
203 </view>
204 <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.lck" label="Back-annotate Pin Report" >
204 <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.lck" label="Back-annotate Pin Report" >
205 <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
205 <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
206 <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
206 <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
207 </view>
207 </view>
208 <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.lpc" label="Locked Pin Constraints" >
208 <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.lpc" label="Locked Pin Constraints" >
209 <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
209 <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
210 <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
210 <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
211 </view>
211 </view>
212 <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/leon3mp_timesim.nlf" label="Post-Fit Simulation Model Report" />
212 <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/leon3mp_timesim.nlf" label="Post-Fit Simulation Model Report" />
213 <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
213 <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
214 <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
214 <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
215 </viewgroup>
215 </viewgroup>
216 </body>
216 </body>
217 </report-views>
217 </report-views>
Show file before | Show file after | Hide comments
@@ -1,242 +1,255
1
1
2 # ==== Clock inputs (CLK) ====
2 # ==== Clock inputs (CLK) ====
3 NET "clk_50mhz" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
3 NET "clk_50mhz" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
4 #NET "clk_67mhz" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
4 #NET "clk_67mhz" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
5 NET "clk_50mhz" PERIOD = 20ns HIGH 40%;
5 NET "clk_50mhz" PERIOD = 20ns HIGH 40%;
6
6
7 NET erx_clk PERIOD = 40.000 ;
7 NET erx_clk PERIOD = 40.000 ;
8 OFFSET = IN : 10.000 : BEFORE erx_clk ;
8 OFFSET = IN : 10.000 : BEFORE erx_clk ;
9 NET etx_clk PERIOD = 40.000 ;
9 NET etx_clk PERIOD = 40.000 ;
10 OFFSET = OUT : 20.000 : AFTER etx_clk ;
10 OFFSET = OUT : 20.000 : AFTER etx_clk ;
11 OFFSET = IN : 8.000 : BEFORE etx_clk ;
11 OFFSET = IN : 8.000 : BEFORE etx_clk ;
12
12
13 NET "clkm" TNM_NET = "clkm";
13 NET "clkm" TNM_NET = "clkm";
14 NET "clkml" TNM_NET = "clkml";
14 NET "clkml" TNM_NET = "clkml";
15 TIMESPEC "TS_clkm_clkml" = FROM "clkm" TO "clkml" TIG;
15 TIMESPEC "TS_clkm_clkml" = FROM "clkm" TO "clkml" TIG;
16 TIMESPEC "TS_clkml_clkm" = FROM "clkml" TO "clkm" TIG;
16 TIMESPEC "TS_clkml_clkm" = FROM "clkml" TO "clkm" TIG;
17 NET "lock" TIG;
17 NET "lock" TIG;
18
18
19 NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb";
19 NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb";
20 TIMESPEC "TS_ddr_clk_fb" = PERIOD "ddr_clk_fb" 10.00 ns HIGH 50 %;
20 TIMESPEC "TS_ddr_clk_fb" = PERIOD "ddr_clk_fb" 10.00 ns HIGH 50 %;
21 NET "ddr_clk_fb" MAXDELAY = 1660 ps;
21 NET "ddr_clk_fb" MAXDELAY = 1660 ps;
22 NET "*dqinl*" MAXDELAY = 1900 ps;
22 NET "*dqinl*" MAXDELAY = 1900 ps;
23 NET "ddrsp0.ddrc/ddr16.ddrc/rwdata*" MAXDELAY = 2100 ps;
23 NET "ddrsp0.ddrc/ddr16.ddrc/rwdata*" MAXDELAY = 2100 ps;
24
24
25 INST "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/nops.read_dll" LOC = DCM_X1Y3;
25 INST "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/nops.read_dll" LOC = DCM_X1Y3;
26 INST "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/ps.read_dll" LOC = DCM_X1Y3;
26 INST "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/ps.read_dll" LOC = DCM_X1Y3;
27 INST "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/dll" LOC = DCM_X0Y2;
27 INST "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/dll" LOC = DCM_X0Y2;
28
28
29 # Enable this for ISE-10
29 # Enable this for ISE-10
30 PIN "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/dll.CLK270" CLOCK_DEDICATED_ROUTE = FALSE;
30 PIN "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/dll.CLK270" CLOCK_DEDICATED_ROUTE = FALSE;
31 NET etx_clk CLOCK_DEDICATED_ROUTE = FALSE;
31 NET etx_clk CLOCK_DEDICATED_ROUTE = FALSE;
32 NET erx_clk CLOCK_DEDICATED_ROUTE = FALSE;
32 NET erx_clk CLOCK_DEDICATED_ROUTE = FALSE;
33 PIN "clkgen0/xc3s.v/dll0.CLK2X" CLOCK_DEDICATED_ROUTE = FALSE;
33 PIN "clkgen0/xc3s.v/dll0.CLK2X" CLOCK_DEDICATED_ROUTE = FALSE;
34 PIN "clkgen0/xc3s.v/dll0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
34 PIN "clkgen0/xc3s.v/dll0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
35 NET "clk_50mhz" CLOCK_DEDICATED_ROUTE = FALSE;
35 NET "clk_50mhz" CLOCK_DEDICATED_ROUTE = FALSE;
36
36
37 #NET "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/vlockl_1" TIG;
37 #NET "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/vlockl_1" TIG;
38
38
39 NET "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/rclk90b" TNM_NET = "rclk90b";
39 NET "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc3se.ddr_phy0/rclk90b" TNM_NET = "rclk90b";
40 TIMEGRP "rclk270b_rise" = FALLING "rclk90b";
40 TIMEGRP "rclk270b_rise" = FALLING "rclk90b";
41 TIMEGRP "clkml_rise" = RISING "clkml";
41 TIMEGRP "clkml_rise" = RISING "clkml";
42 TIMESPEC "TS_rclk270b_clkml_rise" = FROM "rclk270b_rise" TO "clkml_rise" 4.500;
42 TIMESPEC "TS_rclk270b_clkml_rise" = FROM "rclk270b_rise" TO "clkml_rise" 4.500;
43
43
44 # ==== Pushbuttons (BTN) ====
44 # ==== Pushbuttons (BTN) ====
45 #NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
45 #NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
46 NET "dsubre" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
46 NET "dsubre" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
47 NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
47 NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
48 #NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
48 #NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
49 NET "reset" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
49 NET "reset" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
50 NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
50 NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
51 #NET "btn0" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
51 #NET "btn0" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
52 #NET "btn1" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
52 #NET "btn1" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
53 #NET "btn2" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
53 #NET "btn2" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
54
54
55
55
56 # ==== Discrete LEDs (LED) ====
56 # ==== Discrete LEDs (LED) ====
57 # These are shared connections with the FX2 connector
57 # These are shared connections with the FX2 connector
58 NET "led(0)" LOC = "R14" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
58 NET "led(0)" LOC = "R14" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
59 NET "led(1)" LOC = "C3" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
59 NET "led(1)" LOC = "C3" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
60 NET "led(2)" LOC = "E6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
60 NET "led(2)" LOC = "E6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
61 NET "led(3)" LOC = "D6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
61 NET "led(3)" LOC = "D6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
62 NET "led(4)" LOC = "D13" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
62 NET "led(4)" LOC = "D13" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
63 NET "led(5)" LOC = "A7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
63 NET "led(5)" LOC = "A7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
64 #NET "led(6)" LOC = "G9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
64 #NET "led(6)" LOC = "G9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
65 #NET "dsuact" LOC = "G9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
65 #NET "dsuact" LOC = "G9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
66 #NET "led(7)" LOC = "A8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
66 #NET "led(7)" LOC = "A8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
67 NET "errorn" LOC = "A8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
67 NET "errorn" LOC = "A8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
68
68
69 # ==== Rotary Encoder ====
69 # ==== Rotary Encoder ====
70 #NET "rotary(0)" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;
70 #NET "rotary(0)" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;
71 #NET "rotary(1)" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
71 #NET "rotary(1)" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
72 #NET "rotary(2)" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
72 #NET "rotary(2)" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
73
73
74 # ==== Slide Switches (SW) ====
74 # ==== Slide Switches (SW) ====
75 #NET "sw(0)" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
75 #NET "sw(0)" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
76 #NET "sw(1)" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
76 #NET "sw(1)" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
77 #NET "sw(2)" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
77 #NET "sw(2)" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
78 #NET "sw(3)" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
78 #NET "sw(3)" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
79
79
80 # ==== RS-232 Serial Ports (RS232) ====
80 # ==== RS-232 Serial Ports (RS232) ====
81 NET "urxd1" LOC = "U8" | IOSTANDARD = LVTTL ;
81 NET "urxd1" LOC = "U8" | IOSTANDARD = LVTTL ;
82 NET "dsurx" LOC = "R7" | IOSTANDARD = LVTTL ;
82 NET "dsurx" LOC = "R7" | IOSTANDARD = LVTTL ;
83 NET "utxd1" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
83 NET "utxd1" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
84 NET "dsutx" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
84 NET "dsutx" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
85
85
86
86
87 # ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)
87 # ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)
88 NET "ddr_ad(0)" LOC = "T1" | IOSTANDARD = SSTL2_I ;
88 NET "ddr_ad(0)" LOC = "T1" | IOSTANDARD = SSTL2_I ;
89 NET "ddr_ad(1)" LOC = "R3" | IOSTANDARD = SSTL2_I ;
89 NET "ddr_ad(1)" LOC = "R3" | IOSTANDARD = SSTL2_I ;
90 NET "ddr_ad(2)" LOC = "R2" | IOSTANDARD = SSTL2_I ;
90 NET "ddr_ad(2)" LOC = "R2" | IOSTANDARD = SSTL2_I ;
91 NET "ddr_ad(3)" LOC = "P1" | IOSTANDARD = SSTL2_I ;
91 NET "ddr_ad(3)" LOC = "P1" | IOSTANDARD = SSTL2_I ;
92 NET "ddr_ad(4)" LOC = "E4" | IOSTANDARD = SSTL2_I ;
92 NET "ddr_ad(4)" LOC = "E4" | IOSTANDARD = SSTL2_I ;
93 NET "ddr_ad(5)" LOC = "H4" | IOSTANDARD = SSTL2_I ;
93 NET "ddr_ad(5)" LOC = "H4" | IOSTANDARD = SSTL2_I ;
94 NET "ddr_ad(6)" LOC = "H3" | IOSTANDARD = SSTL2_I ;
94 NET "ddr_ad(6)" LOC = "H3" | IOSTANDARD = SSTL2_I ;
95 NET "ddr_ad(7)" LOC = "H1" | IOSTANDARD = SSTL2_I ;
95 NET "ddr_ad(7)" LOC = "H1" | IOSTANDARD = SSTL2_I ;
96 NET "ddr_ad(8)" LOC = "H2" | IOSTANDARD = SSTL2_I ;
96 NET "ddr_ad(8)" LOC = "H2" | IOSTANDARD = SSTL2_I ;
97 NET "ddr_ad(9)" LOC = "N4" | IOSTANDARD = SSTL2_I ;
97 NET "ddr_ad(9)" LOC = "N4" | IOSTANDARD = SSTL2_I ;
98 NET "ddr_ad(10)" LOC = "T2" | IOSTANDARD = SSTL2_I ;
98 NET "ddr_ad(10)" LOC = "T2" | IOSTANDARD = SSTL2_I ;
99 NET "ddr_ad(11)" LOC = "N5" | IOSTANDARD = SSTL2_I ;
99 NET "ddr_ad(11)" LOC = "N5" | IOSTANDARD = SSTL2_I ;
100 NET "ddr_ad(12)" LOC = "P2" | IOSTANDARD = SSTL2_I ;
100 NET "ddr_ad(12)" LOC = "P2" | IOSTANDARD = SSTL2_I ;
101 NET "ddr_ba(0)" LOC = "K5" | IOSTANDARD = SSTL2_I ;
101 NET "ddr_ba(0)" LOC = "K5" | IOSTANDARD = SSTL2_I ;
102 NET "ddr_ba(1)" LOC = "K6" | IOSTANDARD = SSTL2_I ;
102 NET "ddr_ba(1)" LOC = "K6" | IOSTANDARD = SSTL2_I ;
103 NET "ddr_casb" LOC = "C2" | IOSTANDARD = SSTL2_I ;
103 NET "ddr_casb" LOC = "C2" | IOSTANDARD = SSTL2_I ;
104 NET "ddr_clk0b" LOC = "J4" | IOSTANDARD = SSTL2_I ;
104 NET "ddr_clk0b" LOC = "J4" | IOSTANDARD = SSTL2_I ;
105 NET "ddr_clk0" LOC = "J5" | IOSTANDARD = SSTL2_I ;
105 NET "ddr_clk0" LOC = "J5" | IOSTANDARD = SSTL2_I ;
106 NET "ddr_cke0" LOC = "K3" | IOSTANDARD = SSTL2_I ;
106 NET "ddr_cke0" LOC = "K3" | IOSTANDARD = SSTL2_I ;
107 NET "ddr_cs0b" LOC = "K4" | IOSTANDARD = SSTL2_I ;
107 NET "ddr_cs0b" LOC = "K4" | IOSTANDARD = SSTL2_I ;
108 NET "ddr_dq(0)" LOC = "L2" | IOSTANDARD = SSTL2_I ;
108 NET "ddr_dq(0)" LOC = "L2" | IOSTANDARD = SSTL2_I ;
109 NET "ddr_dq(1)" LOC = "L1" | IOSTANDARD = SSTL2_I ;
109 NET "ddr_dq(1)" LOC = "L1" | IOSTANDARD = SSTL2_I ;
110 NET "ddr_dq(2)" LOC = "L3" | IOSTANDARD = SSTL2_I ;
110 NET "ddr_dq(2)" LOC = "L3" | IOSTANDARD = SSTL2_I ;
111 NET "ddr_dq(3)" LOC = "L4" | IOSTANDARD = SSTL2_I ;
111 NET "ddr_dq(3)" LOC = "L4" | IOSTANDARD = SSTL2_I ;
112 NET "ddr_dq(4)" LOC = "M3" | IOSTANDARD = SSTL2_I ;
112 NET "ddr_dq(4)" LOC = "M3" | IOSTANDARD = SSTL2_I ;
113 NET "ddr_dq(5)" LOC = "M4" | IOSTANDARD = SSTL2_I ;
113 NET "ddr_dq(5)" LOC = "M4" | IOSTANDARD = SSTL2_I ;
114 NET "ddr_dq(6)" LOC = "M5" | IOSTANDARD = SSTL2_I ;
114 NET "ddr_dq(6)" LOC = "M5" | IOSTANDARD = SSTL2_I ;
115 NET "ddr_dq(7)" LOC = "M6" | IOSTANDARD = SSTL2_I ;
115 NET "ddr_dq(7)" LOC = "M6" | IOSTANDARD = SSTL2_I ;
116 NET "ddr_dq(8)" LOC = "E2" | IOSTANDARD = SSTL2_I ;
116 NET "ddr_dq(8)" LOC = "E2" | IOSTANDARD = SSTL2_I ;
117 NET "ddr_dq(9)" LOC = "E1" | IOSTANDARD = SSTL2_I ;
117 NET "ddr_dq(9)" LOC = "E1" | IOSTANDARD = SSTL2_I ;
118 NET "ddr_dq(10)" LOC = "F1" | IOSTANDARD = SSTL2_I ;
118 NET "ddr_dq(10)" LOC = "F1" | IOSTANDARD = SSTL2_I ;
119 NET "ddr_dq(11)" LOC = "F2" | IOSTANDARD = SSTL2_I ;
119 NET "ddr_dq(11)" LOC = "F2" | IOSTANDARD = SSTL2_I ;
120 NET "ddr_dq(12)" LOC = "G6" | IOSTANDARD = SSTL2_I ;
120 NET "ddr_dq(12)" LOC = "G6" | IOSTANDARD = SSTL2_I ;
121 NET "ddr_dq(13)" LOC = "G5" | IOSTANDARD = SSTL2_I ;
121 NET "ddr_dq(13)" LOC = "G5" | IOSTANDARD = SSTL2_I ;
122 NET "ddr_dq(14)" LOC = "H6" | IOSTANDARD = SSTL2_I ;
122 NET "ddr_dq(14)" LOC = "H6" | IOSTANDARD = SSTL2_I ;
123 NET "ddr_dq(15)" LOC = "H5" | IOSTANDARD = SSTL2_I ;
123 NET "ddr_dq(15)" LOC = "H5" | IOSTANDARD = SSTL2_I ;
124 NET "ddr_dm(0)" LOC = "J2" | IOSTANDARD = SSTL2_I ;
124 NET "ddr_dm(0)" LOC = "J2" | IOSTANDARD = SSTL2_I ;
125 NET "ddr_dqs(0)" LOC = "L6" | IOSTANDARD = SSTL2_I ;
125 NET "ddr_dqs(0)" LOC = "L6" | IOSTANDARD = SSTL2_I ;
126 NET "ddr_rasb" LOC = "C1" | IOSTANDARD = SSTL2_I ;
126 NET "ddr_rasb" LOC = "C1" | IOSTANDARD = SSTL2_I ;
127 NET "ddr_dm(1)" LOC = "J1" | IOSTANDARD = SSTL2_I ;
127 NET "ddr_dm(1)" LOC = "J1" | IOSTANDARD = SSTL2_I ;
128 NET "ddr_dqs(1)" LOC = "G3" | IOSTANDARD = SSTL2_I ;
128 NET "ddr_dqs(1)" LOC = "G3" | IOSTANDARD = SSTL2_I ;
129 NET "ddr_web" LOC = "D1" | IOSTANDARD = SSTL2_I ;
129 NET "ddr_web" LOC = "D1" | IOSTANDARD = SSTL2_I ;
130
130
131 Net ddr_clk_fb LOC=B9 | IOSTANDARD = LVCMOS33;
131 Net ddr_clk_fb LOC=B9 | IOSTANDARD = LVCMOS33;
132
132
133 Net etx_clk LOC=T7;
133 Net etx_clk LOC=T7;
134 Net etx_clk IOSTANDARD = LVCMOS33;
134 Net etx_clk IOSTANDARD = LVCMOS33;
135 Net erx_clk LOC=V3 ;
135 Net erx_clk LOC=V3 ;
136 Net erx_clk IOSTANDARD = LVCMOS33;
136 Net erx_clk IOSTANDARD = LVCMOS33;
137 Net erx_crs LOC=U13;
137 Net erx_crs LOC=U13;
138 Net erx_crs IOSTANDARD = LVCMOS33;
138 Net erx_crs IOSTANDARD = LVCMOS33;
139 Net erx_dv LOC=V2;
139 Net erx_dv LOC=V2;
140 Net erx_dv IOSTANDARD = LVCMOS33;
140 Net erx_dv IOSTANDARD = LVCMOS33;
141 Net erxd(0) LOC=V8;
141 Net erxd(0) LOC=V8;
142 Net erxd(0) IOSTANDARD = LVCMOS33;
142 Net erxd(0) IOSTANDARD = LVCMOS33;
143 Net erxd(1) LOC=T11;
143 Net erxd(1) LOC=T11;
144 Net erxd(1) IOSTANDARD = LVCMOS33;
144 Net erxd(1) IOSTANDARD = LVCMOS33;
145 Net erxd(2) LOC=U11;
145 Net erxd(2) LOC=U11;
146 Net erxd(2) IOSTANDARD = LVCMOS33;
146 Net erxd(2) IOSTANDARD = LVCMOS33;
147 Net erxd(3) LOC=V14;
147 Net erxd(3) LOC=V14;
148 Net erxd(3) IOSTANDARD = LVCMOS33;
148 Net erxd(3) IOSTANDARD = LVCMOS33;
149 Net erx_col LOC=U6;
149 Net erx_col LOC=U6;
150 Net erx_col IOSTANDARD = LVCMOS33;
150 Net erx_col IOSTANDARD = LVCMOS33;
151 Net erx_er LOC=U14;
151 Net erx_er LOC=U14;
152 Net erx_er IOSTANDARD = LVCMOS33;
152 Net erx_er IOSTANDARD = LVCMOS33;
153 Net etx_en LOC=P16;
153 Net etx_en LOC=P16;
154 Net etx_en IOSTANDARD = LVCMOS33;
154 Net etx_en IOSTANDARD = LVCMOS33;
155 Net etxd(0) LOC=R11;
155 Net etxd(0) LOC=R11;
156 Net etxd(0) IOSTANDARD = LVCMOS33;
156 Net etxd(0) IOSTANDARD = LVCMOS33;
157 Net etxd(1) LOC=T15;
157 Net etxd(1) LOC=T15;
158 Net etxd(1) IOSTANDARD = LVCMOS33;
158 Net etxd(1) IOSTANDARD = LVCMOS33;
159 Net etxd(2) LOC=R5;
159 Net etxd(2) LOC=R5;
160 Net etxd(2) IOSTANDARD = LVCMOS33;
160 Net etxd(2) IOSTANDARD = LVCMOS33;
161 Net etxd(3) LOC=T5;
161 Net etxd(3) LOC=T5;
162 Net etxd(3) IOSTANDARD = LVCMOS33;
162 Net etxd(3) IOSTANDARD = LVCMOS33;
163 Net etx_er LOC=R6 | IOSTANDARD = LVCMOS33;
163 Net etx_er LOC=R6 | IOSTANDARD = LVCMOS33;
164 Net emdc LOC=P9;
164 Net emdc LOC=P9;
165 Net emdc IOSTANDARD = LVCMOS33;
165 Net emdc IOSTANDARD = LVCMOS33;
166 Net emdio LOC=U5;
166 Net emdio LOC=U5;
167 Net emdio IOSTANDARD = LVCMOS33;
167 Net emdio IOSTANDARD = LVCMOS33;
168
168
169 Net address(23) LOC=N11 | IOSTANDARD = LVCMOS33;
169 Net address(23) LOC=N11 | IOSTANDARD = LVCMOS33;
170 Net address(22) LOC=V12 | IOSTANDARD = LVCMOS33;
170 Net address(22) LOC=V12 | IOSTANDARD = LVCMOS33;
171 Net address(21) LOC=V13 | IOSTANDARD = LVCMOS33;
171 Net address(21) LOC=V13 | IOSTANDARD = LVCMOS33;
172 Net address(20) LOC=T12 | IOSTANDARD = LVCMOS33;
172 Net address(20) LOC=T12 | IOSTANDARD = LVCMOS33;
173 Net address(19) LOC=V15 | IOSTANDARD = LVCMOS33;
173 Net address(19) LOC=V15 | IOSTANDARD = LVCMOS33;
174 Net address(18) LOC=U15 | IOSTANDARD = LVCMOS33;
174 Net address(18) LOC=U15 | IOSTANDARD = LVCMOS33;
175 Net address(17) LOC=T16 | IOSTANDARD = LVCMOS33;
175 Net address(17) LOC=T16 | IOSTANDARD = LVCMOS33;
176 Net address(16) LOC=U18 | IOSTANDARD = LVCMOS33;
176 Net address(16) LOC=U18 | IOSTANDARD = LVCMOS33;
177 Net address(15) LOC=T17 | IOSTANDARD = LVCMOS33;
177 Net address(15) LOC=T17 | IOSTANDARD = LVCMOS33;
178 Net address(14) LOC=R18 | IOSTANDARD = LVCMOS33;
178 Net address(14) LOC=R18 | IOSTANDARD = LVCMOS33;
179 Net address(13) LOC=T18 | IOSTANDARD = LVCMOS33;
179 Net address(13) LOC=T18 | IOSTANDARD = LVCMOS33;
180 Net address(12) LOC=L16 | IOSTANDARD = LVCMOS33;
180 Net address(12) LOC=L16 | IOSTANDARD = LVCMOS33;
181 Net address(11) LOC=L15 | IOSTANDARD = LVCMOS33;
181 Net address(11) LOC=L15 | IOSTANDARD = LVCMOS33;
182 Net address(10) LOC=K13 | IOSTANDARD = LVCMOS33;
182 Net address(10) LOC=K13 | IOSTANDARD = LVCMOS33;
183 Net address(9) LOC=K12 | IOSTANDARD = LVCMOS33;
183 Net address(9) LOC=K12 | IOSTANDARD = LVCMOS33;
184 Net address(8) LOC=K15 | IOSTANDARD = LVCMOS33;
184 Net address(8) LOC=K15 | IOSTANDARD = LVCMOS33;
185 Net address(7) LOC=K14 | IOSTANDARD = LVCMOS33;
185 Net address(7) LOC=K14 | IOSTANDARD = LVCMOS33;
186 Net address(6) LOC=J17 | IOSTANDARD = LVCMOS33;
186 Net address(6) LOC=J17 | IOSTANDARD = LVCMOS33;
187 Net address(5) LOC=J16 | IOSTANDARD = LVCMOS33;
187 Net address(5) LOC=J16 | IOSTANDARD = LVCMOS33;
188 Net address(4) LOC=J15 | IOSTANDARD = LVCMOS33;
188 Net address(4) LOC=J15 | IOSTANDARD = LVCMOS33;
189 Net address(3) LOC=J14 | IOSTANDARD = LVCMOS33;
189 Net address(3) LOC=J14 | IOSTANDARD = LVCMOS33;
190 Net address(2) LOC=J12 | IOSTANDARD = LVCMOS33;
190 Net address(2) LOC=J12 | IOSTANDARD = LVCMOS33;
191 Net address(1) LOC=J13 | IOSTANDARD = LVCMOS33;
191 Net address(1) LOC=J13 | IOSTANDARD = LVCMOS33;
192 Net address(0) LOC=H17 | IOSTANDARD = LVCMOS33;
192 Net address(0) LOC=H17 | IOSTANDARD = LVCMOS33;
193
193
194 Net data(15) LOC=T8 | IOSTANDARD = LVCMOS33;
194 Net data(15) LOC=T8 | IOSTANDARD = LVCMOS33;
195 Net data(14) LOC=R8 | IOSTANDARD = LVCMOS33;
195 Net data(14) LOC=R8 | IOSTANDARD = LVCMOS33;
196 Net data(13) LOC=P6 | IOSTANDARD = LVCMOS33;
196 Net data(13) LOC=P6 | IOSTANDARD = LVCMOS33;
197 Net data(12) LOC=M16 | IOSTANDARD = LVCMOS33;
197 Net data(12) LOC=M16 | IOSTANDARD = LVCMOS33;
198 Net data(11) LOC=M15 | IOSTANDARD = LVCMOS33;
198 Net data(11) LOC=M15 | IOSTANDARD = LVCMOS33;
199 Net data(10) LOC=P17 | IOSTANDARD = LVCMOS33;
199 Net data(10) LOC=P17 | IOSTANDARD = LVCMOS33;
200 Net data(9) LOC=R16 | IOSTANDARD = LVCMOS33;
200 Net data(9) LOC=R16 | IOSTANDARD = LVCMOS33;
201 Net data(8) LOC=R15 | IOSTANDARD = LVCMOS33;
201 Net data(8) LOC=R15 | IOSTANDARD = LVCMOS33;
202 Net data(7) LOC=N9 | IOSTANDARD = LVCMOS33;
202 Net data(7) LOC=N9 | IOSTANDARD = LVCMOS33;
203 Net data(6) LOC=M9 | IOSTANDARD = LVCMOS33;
203 Net data(6) LOC=M9 | IOSTANDARD = LVCMOS33;
204 Net data(5) LOC=R9 | IOSTANDARD = LVCMOS33;
204 Net data(5) LOC=R9 | IOSTANDARD = LVCMOS33;
205 Net data(4) LOC=U9 | IOSTANDARD = LVCMOS33;
205 Net data(4) LOC=U9 | IOSTANDARD = LVCMOS33;
206 Net data(3) LOC=V9 | IOSTANDARD = LVCMOS33;
206 Net data(3) LOC=V9 | IOSTANDARD = LVCMOS33;
207 Net data(2) LOC=R10 | IOSTANDARD = LVCMOS33;
207 Net data(2) LOC=R10 | IOSTANDARD = LVCMOS33;
208 Net data(1) LOC=P10 | IOSTANDARD = LVCMOS33;
208 Net data(1) LOC=P10 | IOSTANDARD = LVCMOS33;
209 Net data(0) LOC=N10 | IOSTANDARD = LVCMOS33;
209 Net data(0) LOC=N10 | IOSTANDARD = LVCMOS33;
210 Net oen LOC=C18 | IOSTANDARD = LVCMOS33;
210 Net oen LOC=C18 | IOSTANDARD = LVCMOS33;
211 Net writen LOC=D17 | IOSTANDARD = LVCMOS33;
211 Net writen LOC=D17 | IOSTANDARD = LVCMOS33;
212 Net romsn LOC=D16 | IOSTANDARD = LVCMOS33;
212 Net romsn LOC=D16 | IOSTANDARD = LVCMOS33;
213 Net byten LOC=C17 | IOSTANDARD = LVCMOS33;
213 Net byten LOC=C17 | IOSTANDARD = LVCMOS33;
214 Net sts LOC=B18 ;
214 Net sts LOC=B18 ;
215
215
216 NET ps2data LOC = G13 | IOSTANDARD = LVCMOS33;
216 NET ps2data LOC = G13 | IOSTANDARD = LVCMOS33;
217 NET ps2clk LOC = G14 | IOSTANDARD = LVCMOS33;
217 NET ps2clk LOC = G14 | IOSTANDARD = LVCMOS33;
218
218
219 NET vid_r LOC = H14 | IOSTANDARD = LVCMOS33;
219 NET vid_r LOC = H14 | IOSTANDARD = LVCMOS33;
220 NET vid_g LOC = H15 | IOSTANDARD = LVCMOS33;
220 NET vid_g LOC = H15 | IOSTANDARD = LVCMOS33;
221 NET vid_b LOC = G15 | IOSTANDARD = LVCMOS33;
221 NET vid_b LOC = G15 | IOSTANDARD = LVCMOS33;
222 NET vid_hsync LOC = F15 | IOSTANDARD = LVCMOS33;
222 NET vid_hsync LOC = F15 | IOSTANDARD = LVCMOS33;
223 NET vid_vsync LOC = F14 | IOSTANDARD = LVCMOS33;
223 NET vid_vsync LOC = F14 | IOSTANDARD = LVCMOS33;
224
224
225 NET spi LOC=U3 | PULLUP; ## This is to force the SPI ROM to not be selected(drive high)
225 NET spi LOC=U3 | PULLUP; ## This is to force the SPI ROM to not be selected(drive high)
226 Net spi IOSTANDARD = LVCMOS33;
226 Net spi IOSTANDARD = LVCMOS33;
227
227
228
228
229 # Prohibit VREF pins
229 # Prohibit VREF pins
230 CONFIG PROHIBIT = D2;
230 CONFIG PROHIBIT = D2;
231 CONFIG PROHIBIT = G4;
231 CONFIG PROHIBIT = G4;
232 CONFIG PROHIBIT = J6;
232 CONFIG PROHIBIT = J6;
233 CONFIG PROHIBIT = L5;
233 CONFIG PROHIBIT = L5;
234 CONFIG PROHIBIT = R4;
234 CONFIG PROHIBIT = R4;
235
235
236 NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
236 NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
237 NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
237 NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
238 NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
238 NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
239 NET "LCD_RET" LOC = "E3" | IOSTANDARD = SSTL2_I ;
239 NET "LCD_RET" LOC = "E3" | IOSTANDARD = SSTL2_I ;
240 NET "LCD_CS1" LOC = "P3" | IOSTANDARD = SSTL2_I ;
240 NET "LCD_CS1" LOC = "P3" | IOSTANDARD = SSTL2_I ;
241 NET "LCD_CS2" LOC = "P4" | IOSTANDARD = SSTL2_I ;
241 NET "LCD_CS2" LOC = "P4" | IOSTANDARD = SSTL2_I ;
242 NET "ADC_SCK" LOC = "P13" | IOSTANDARD = LVTTL ;
243 NET "ADC_CNV" LOC = "T14" | IOSTANDARD = LVTTL ;
244 NET "ADC_SDI" LOC = "R13" | IOSTANDARD = LVTTL ;
242
245
246
247
248
249
250
251
252
253
254
255
Show file before | Show file after | Hide comments
@@ -1,590 +1,609
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
4 ------------------------------------------------------------------------------
4 ------------------------------------------------------------------------------
5 -- This file is a part of the GRLIB VHDL IP LIBRARY
5 -- This file is a part of the GRLIB VHDL IP LIBRARY
6 -- Copyright (C) 2003 - 2008, Gaisler Research
6 -- Copyright (C) 2003 - 2008, Gaisler Research
7 -- Copyright (C) 2008 - 2010, Aeroflex Gaisler
7 -- Copyright (C) 2008 - 2010, Aeroflex Gaisler
8 --
8 --
9 -- This program is free software; you can redistribute it and/or modify
9 -- This program is free software; you can redistribute it and/or modify
10 -- it under the terms of the GNU General Public License as published by
10 -- it under the terms of the GNU General Public License as published by
11 -- the Free Software Foundation; either version 2 of the License, or
11 -- the Free Software Foundation; either version 2 of the License, or
12 -- (at your option) any later version.
12 -- (at your option) any later version.
13 --
13 --
14 -- This program is distributed in the hope that it will be useful,
14 -- This program is distributed in the hope that it will be useful,
15 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
15 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
16 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 -- GNU General Public License for more details.
17 -- GNU General Public License for more details.
18 --
18 --
19 -- You should have received a copy of the GNU General Public License
19 -- You should have received a copy of the GNU General Public License
20 -- along with this program; if not, write to the Free Software
20 -- along with this program; if not, write to the Free Software
21 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 ------------------------------------------------------------------------------
22 ------------------------------------------------------------------------------
23
23
24 library ieee;
24 library ieee;
25 use ieee.std_logic_1164.all;
25 use ieee.std_logic_1164.all;
26 library grlib;
26 library grlib;
27 use grlib.amba.all;
27 use grlib.amba.all;
28 use grlib.stdlib.all;
28 use grlib.stdlib.all;
29 use grlib.devices.all;
29 use grlib.devices.all;
30 library techmap;
30 library techmap;
31 use techmap.gencomp.all;
31 use techmap.gencomp.all;
32 use techmap.allclkgen.all;
32 use techmap.allclkgen.all;
33 library gaisler;
33 library gaisler;
34 use gaisler.memctrl.all;
34 use gaisler.memctrl.all;
35 use gaisler.leon3.all;
35 use gaisler.leon3.all;
36 use gaisler.uart.all;
36 use gaisler.uart.all;
37 use gaisler.misc.all;
37 use gaisler.misc.all;
38 use gaisler.net.all;
38 use gaisler.net.all;
39 use gaisler.jtag.all;
39 use gaisler.jtag.all;
40 library esa;
40 library esa;
41 use esa.memoryctrl.all;
41 use esa.memoryctrl.all;
42 use work.config.all;
42 use work.config.all;
43 library lpp;
43 library lpp;
44 use lpp.amba_lcd_16x2_ctrlr.all;
44 use lpp.amba_lcd_16x2_ctrlr.all;
45 use lpp.LCD_16x2_CFG.all;
45 use lpp.LCD_16x2_CFG.all;
46 use lpp.lpp_ad_conv.all;
47
46
48
47 entity leon3mp is
49 entity leon3mp is
48 generic (
50 generic (
49 fabtech : integer := CFG_FABTECH;
51 fabtech : integer := CFG_FABTECH;
50 memtech : integer := CFG_MEMTECH;
52 memtech : integer := CFG_MEMTECH;
51 padtech : integer := CFG_PADTECH;
53 padtech : integer := CFG_PADTECH;
52 clktech : integer := CFG_CLKTECH;
54 clktech : integer := CFG_CLKTECH;
53 disas : integer := CFG_DISAS; -- Enable disassembly to console
55 disas : integer := CFG_DISAS; -- Enable disassembly to console
54 dbguart : integer := CFG_DUART; -- Print UART on console
56 dbguart : integer := CFG_DUART; -- Print UART on console
55 pclow : integer := CFG_PCLOW;
57 pclow : integer := CFG_PCLOW;
56 ddrfreq : integer := 100000 -- frequency of ddr clock in kHz
58 ddrfreq : integer := 100000 -- frequency of ddr clock in kHz
57 );
59 );
58 port (
60 port (
59 reset : in std_ulogic;
61 reset : in std_ulogic;
60 -- resoutn : out std_logic;
62 -- resoutn : out std_logic;
61 clk_50mhz : in std_ulogic;
63 clk_50mhz : in std_ulogic;
62 errorn : out std_ulogic;
64 errorn : out std_ulogic;
63
65
64 -- prom interface
66 -- prom interface
65 address : out std_logic_vector(23 downto 0);
67 address : out std_logic_vector(23 downto 0);
66 data : inout std_logic_vector(15 downto 0);
68 data : inout std_logic_vector(15 downto 0);
67 romsn : out std_ulogic;
69 romsn : out std_ulogic;
68 oen : out std_ulogic;
70 oen : out std_ulogic;
69 writen : out std_ulogic;
71 writen : out std_ulogic;
70 byten : out std_ulogic;
72 byten : out std_ulogic;
71 -- pragma translate_off
73 -- pragma translate_off
72 iosn : out std_ulogic;
74 iosn : out std_ulogic;
73 testdata : inout std_logic_vector(15 downto 0);
75 testdata : inout std_logic_vector(15 downto 0);
74 -- pragma translate_on
76 -- pragma translate_on
75
77
76 -- ddr memory
78 -- ddr memory
77 ddr_clk0 : out std_logic;
79 ddr_clk0 : out std_logic;
78 ddr_clk0b : out std_logic;
80 ddr_clk0b : out std_logic;
79 -- ddr_clk_fb_out : out std_logic;
81 -- ddr_clk_fb_out : out std_logic;
80 ddr_clk_fb : in std_logic;
82 ddr_clk_fb : in std_logic;
81 ddr_cke0 : out std_logic;
83 ddr_cke0 : out std_logic;
82 ddr_cs0b : out std_logic;
84 ddr_cs0b : out std_logic;
83 ddr_web : out std_ulogic; -- ddr write enable
85 ddr_web : out std_ulogic; -- ddr write enable
84 ddr_rasb : out std_ulogic; -- ddr ras
86 ddr_rasb : out std_ulogic; -- ddr ras
85 ddr_casb : out std_ulogic; -- ddr cas
87 ddr_casb : out std_ulogic; -- ddr cas
86 ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
88 ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
87 ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
89 ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
88 ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
90 ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
89 ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
91 ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
90 ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
92 ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
91
93
92 -- debug support unit
94 -- debug support unit
93 dsuen : in std_ulogic;
95 dsuen : in std_ulogic;
94 dsubre : in std_ulogic;
96 dsubre : in std_ulogic;
95 -- dsuact : out std_ulogic;
97 -- dsuact : out std_ulogic;
96 dsurx : in std_ulogic;
98 dsurx : in std_ulogic;
97 dsutx : out std_ulogic;
99 dsutx : out std_ulogic;
98
100
99 -- UART for serial console I/O
101 -- UART for serial console I/O
100 urxd1 : in std_ulogic;
102 urxd1 : in std_ulogic;
101 utxd1 : out std_ulogic;
103 utxd1 : out std_ulogic;
102
104
103 -- ethernet signals
105 -- ethernet signals
104 emdio : inout std_logic; -- ethernet PHY interface
106 emdio : inout std_logic; -- ethernet PHY interface
105 etx_clk : in std_ulogic;
107 etx_clk : in std_ulogic;
106 erx_clk : in std_ulogic;
108 erx_clk : in std_ulogic;
107 erxd : in std_logic_vector(3 downto 0);
109 erxd : in std_logic_vector(3 downto 0);
108 erx_dv : in std_ulogic;
110 erx_dv : in std_ulogic;
109 erx_er : in std_ulogic;
111 erx_er : in std_ulogic;
110 erx_col : in std_ulogic;
112 erx_col : in std_ulogic;
111 erx_crs : in std_ulogic;
113 erx_crs : in std_ulogic;
112 etxd : out std_logic_vector(3 downto 0);
114 etxd : out std_logic_vector(3 downto 0);
113 etx_en : out std_ulogic;
115 etx_en : out std_ulogic;
114 etx_er : out std_ulogic;
116 etx_er : out std_ulogic;
115 emdc : out std_ulogic;
117 emdc : out std_ulogic;
116
118
117 spi : out std_ulogic;
119 spi : out std_ulogic;
118
120
119 led : out std_logic_vector(5 downto 0);
121 led : out std_logic_vector(5 downto 0);
120 ps2clk : inout std_logic;
122 ps2clk : inout std_logic;
121 ps2data : inout std_logic;
123 ps2data : inout std_logic;
122
124
123 vid_hsync : out std_ulogic;
125 vid_hsync : out std_ulogic;
124 vid_vsync : out std_ulogic;
126 vid_vsync : out std_ulogic;
125 vid_r : out std_logic;
127 vid_r : out std_logic;
126 vid_g : out std_logic;
128 vid_g : out std_logic;
127 vid_b : out std_logic;
129 vid_b : out std_logic;
128 LCD_RS : out STD_LOGIC;
130 LCD_RS : out STD_LOGIC;
129 LCD_RW : out STD_LOGIC;
131 LCD_RW : out STD_LOGIC;
130 LCD_E : out STD_LOGIC;
132 LCD_E : out STD_LOGIC;
131 LCD_RET : out STD_LOGIC;
133 LCD_RET : out STD_LOGIC;
132 LCD_CS1 : out STD_LOGIC;
134 LCD_CS1 : out STD_LOGIC;
133 LCD_CS2 : out STD_LOGIC;
135 LCD_CS2 : out STD_LOGIC;
134 SF_CE0 : out std_logic;
136 SF_CE0 : out std_logic;
135 BTN_NORTH : in std_ulogic;
137 BTN_NORTH : in std_ulogic;
136 BTN_WEST : in std_ulogic
138 BTN_WEST : in std_ulogic;
139 ADC_SCK : out std_logic;
140 ADC_CNV : out std_logic;
141 ADC_SDI : in std_logic
137 );
142 );
138 end;
143 end;
139
144
140 architecture rtl of leon3mp is
145 architecture rtl of leon3mp is
141
146
142 constant blength : integer := 12;
147 constant blength : integer := 12;
143 constant fifodepth : integer := 8;
148 constant fifodepth : integer := 8;
144
149
145 signal vcc, gnd : std_logic_vector(4 downto 0);
150 signal vcc, gnd : std_logic_vector(4 downto 0);
146 signal memi : memory_in_type;
151 signal memi : memory_in_type;
147 signal memo : memory_out_type;
152 signal memo : memory_out_type;
148 signal wpo : wprot_out_type;
153 signal wpo : wprot_out_type;
149 signal sdi : sdctrl_in_type;
154 signal sdi : sdctrl_in_type;
150 signal sdo : sdctrl_out_type;
155 signal sdo : sdctrl_out_type;
151
156
152 signal gpioi : gpio_in_type;
157 signal gpioi : gpio_in_type;
153 signal gpioo : gpio_out_type;
158 signal gpioo : gpio_out_type;
154
159
155 signal apbi : apb_slv_in_type;
160 signal apbi : apb_slv_in_type;
156 signal apbo : apb_slv_out_vector := (others => apb_none);
161 signal apbo : apb_slv_out_vector := (others => apb_none);
157 signal ahbsi : ahb_slv_in_type;
162 signal ahbsi : ahb_slv_in_type;
158 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
163 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
159 signal ahbmi : ahb_mst_in_type;
164 signal ahbmi : ahb_mst_in_type;
160 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
165 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
161
166
162 signal lclk : std_ulogic;
167 signal lclk : std_ulogic;
163 signal ddrclk, ddrrst, ddrclkfb : std_ulogic;
168 signal ddrclk, ddrrst, ddrclkfb : std_ulogic;
164
169
165 signal clkm, rstn, clkml, clk2x : std_ulogic;
170 signal clkm, rstn, clkml, clk2x : std_ulogic;
166 signal cgi : clkgen_in_type;
171 signal cgi : clkgen_in_type;
167 signal cgo : clkgen_out_type;
172 signal cgo : clkgen_out_type;
168 signal u1i, dui : uart_in_type;
173 signal u1i, dui : uart_in_type;
169 signal u1o, duo : uart_out_type;
174 signal u1o, duo : uart_out_type;
170
175
171 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
176 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
172 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
177 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
173
178
174 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
179 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
175 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
180 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
176
181
177 signal dsui : dsu_in_type;
182 signal dsui : dsu_in_type;
178 signal dsuo : dsu_out_type;
183 signal dsuo : dsu_out_type;
179
184
180 signal ethi, ethi1, ethi2 : eth_in_type;
185 signal ethi, ethi1, ethi2 : eth_in_type;
181 signal etho, etho1, etho2 : eth_out_type;
186 signal etho, etho1, etho2 : eth_out_type;
182
187
183 signal gpti : gptimer_in_type;
188 signal gpti : gptimer_in_type;
184
189
185 signal tck, tms, tdi, tdo : std_ulogic;
190 signal tck, tms, tdi, tdo : std_ulogic;
186
191
187 signal kbdi : ps2_in_type;
192 signal kbdi : ps2_in_type;
188 signal kbdo : ps2_out_type;
193 signal kbdo : ps2_out_type;
189 signal vgao : apbvga_out_type;
194 signal vgao : apbvga_out_type;
190
195
191 signal ldsubre : std_logic;
196 signal ldsubre : std_logic;
192 signal duart, ldsuen : std_logic;
197 signal duart, ldsuen : std_logic;
193 signal rsertx, rserrx, rdsuen : std_logic;
198 signal rsertx, rserrx, rdsuen : std_logic;
194
199
195 signal rstraw : std_logic;
200 signal rstraw : std_logic;
196 signal rstneg : std_logic;
201 signal rstneg : std_logic;
197 signal rxd1, rxd2 : std_logic;
202 signal rxd1, rxd2 : std_logic;
198 signal txd1 : std_logic;
203 signal txd1 : std_logic;
199 signal lock : std_logic;
204 signal lock : std_logic;
200
205
201 signal ddr_clk : std_logic_vector(2 downto 0);
206 signal ddr_clk : std_logic_vector(2 downto 0);
202 signal ddr_clkb : std_logic_vector(2 downto 0);
207 signal ddr_clkb : std_logic_vector(2 downto 0);
203 signal ddr_cke : std_logic_vector(1 downto 0);
208 signal ddr_cke : std_logic_vector(1 downto 0);
204 signal ddr_csb : std_logic_vector(1 downto 0);
209 signal ddr_csb : std_logic_vector(1 downto 0);
205 signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address
210 signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address
206
211
212 signal AD_in : AD7688_in(0 downto 0);
213 signal AD_out : AD7688_out;
214
207 attribute keep : boolean;
215 attribute keep : boolean;
208 attribute syn_keep : boolean;
216 attribute syn_keep : boolean;
209 attribute syn_preserve : boolean;
217 attribute syn_preserve : boolean;
210 attribute syn_keep of lock : signal is true;
218 attribute syn_keep of lock : signal is true;
211 attribute syn_keep of clkml : signal is true;
219 attribute syn_keep of clkml : signal is true;
212 attribute syn_preserve of clkml : signal is true;
220 attribute syn_preserve of clkml : signal is true;
213 attribute keep of lock : signal is true;
221 attribute keep of lock : signal is true;
214 attribute keep of clkml : signal is true;
222 attribute keep of clkml : signal is true;
215 attribute keep of clkm : signal is true;
223 attribute keep of clkm : signal is true;
216
224
217
225
218 constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
226 constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
219 constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
227 constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
220
228
221 begin
229 begin
222
230
223 ----------------------------------------------------------------------
231 ----------------------------------------------------------------------
224 --- Reset and Clock generation -------------------------------------
232 --- Reset and Clock generation -------------------------------------
225 ----------------------------------------------------------------------
233 ----------------------------------------------------------------------
226
234
227 vcc <= (others => '1'); gnd <= (others => '0');
235 vcc <= (others => '1'); gnd <= (others => '0');
228 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
236 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
229 rstneg <= not reset; spi <= '1';
237 rstneg <= not reset; spi <= '1';
230
238
231 rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
239 rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
232 led(5) <= lock;
240 led(5) <= lock;
233
241
234 clk_pad : clkpad generic map (tech => padtech) port map (clk_50mhz, lclk);
242 clk_pad : clkpad generic map (tech => padtech) port map (clk_50mhz, lclk);
235
243
236 clkgen0 : clkgen -- clock generator
244 clkgen0 : clkgen -- clock generator
237 generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
245 generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
238 port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x);
246 port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x);
239
247
240 -- cgo.clklock <= '1';
248 -- cgo.clklock <= '1';
241
249
242 ----------------------------------------------------------------------
250 ----------------------------------------------------------------------
243 --- AHB CONTROLLER --------------------------------------------------
251 --- AHB CONTROLLER --------------------------------------------------
244 ----------------------------------------------------------------------
252 ----------------------------------------------------------------------
245
253
246 ahb0 : ahbctrl -- AHB arbiter/multiplexer
254 ahb0 : ahbctrl -- AHB arbiter/multiplexer
247 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
255 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
248 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
256 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
249 nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE,
257 nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE,
250 nahbs => 8)
258 nahbs => 8)
251 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
259 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
252
260
253 ----------------------------------------------------------------------
261 ----------------------------------------------------------------------
254 --- LEON3 processor and DSU -----------------------------------------
262 --- LEON3 processor and DSU -----------------------------------------
255 ----------------------------------------------------------------------
263 ----------------------------------------------------------------------
256
264
257 leon3gen : if CFG_LEON3 = 1 generate
265 leon3gen : if CFG_LEON3 = 1 generate
258 cpu : for i in 0 to CFG_NCPU-1 generate
266 cpu : for i in 0 to CFG_NCPU-1 generate
259 u0 : leon3s -- LEON3 processor
267 u0 : leon3s -- LEON3 processor
260 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
268 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
261 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
269 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
262 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
270 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
263 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
271 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
264 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
272 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
265 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
273 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
266 CFG_NCPU-1)
274 CFG_NCPU-1)
267 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
275 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
268 irqi(i), irqo(i), dbgi(i), dbgo(i));
276 irqi(i), irqo(i), dbgi(i), dbgo(i));
269 end generate;
277 end generate;
270 error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
278 error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
271
279
272 dsugen : if CFG_DSU = 1 generate
280 dsugen : if CFG_DSU = 1 generate
273 dsu0 : dsu3 -- LEON3 Debug Support Unit
281 dsu0 : dsu3 -- LEON3 Debug Support Unit
274 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
282 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
275 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
283 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
276 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
284 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
277 dsui.enable <= '1';
285 dsui.enable <= '1';
278 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, ldsubre);
286 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, ldsubre);
279 dsui.break <= ldsubre;
287 dsui.break <= ldsubre;
280 -- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
288 -- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
281 led(4) <= dsuo.active;
289 led(4) <= dsuo.active;
282 end generate;
290 end generate;
283 end generate;
291 end generate;
284 nodsu : if CFG_DSU = 0 generate
292 nodsu : if CFG_DSU = 0 generate
285 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
293 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
286 end generate;
294 end generate;
287
295
288 dcomgen : if CFG_AHB_UART = 1 generate
296 dcomgen : if CFG_AHB_UART = 1 generate
289 dcom0 : ahbuart -- Debug UART
297 dcom0 : ahbuart -- Debug UART
290 generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
298 generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
291 port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
299 port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
292 dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd2);
300 dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd2);
293 dui.rxd <= rxd2;
301 dui.rxd <= rxd2;
294 dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
302 dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
295 led(2) <= not rxd2; led(3) <= not duo.txd;
303 led(2) <= not rxd2; led(3) <= not duo.txd;
296 end generate;
304 end generate;
297 nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
305 nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
298
306
299 ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
307 ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
300 ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
308 ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
301 port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
309 port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
302 open, open, open, open, open, open, open, gnd(0));
310 open, open, open, open, open, open, open, gnd(0));
303 end generate;
311 end generate;
304
312
305 ----------------------------------------------------------------------
313 ----------------------------------------------------------------------
306 --- Memory controllers ----------------------------------------------
314 --- Memory controllers ----------------------------------------------
307 ----------------------------------------------------------------------
315 ----------------------------------------------------------------------
308
316
309 mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
317 mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
310 sr1 : mctrl generic map (hindex => 5, pindex => 0,
318 sr1 : mctrl generic map (hindex => 5, pindex => 0,
311 paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 )
319 paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 )
312 port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
320 port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
313 end generate;
321 end generate;
314
322
315 byten <= '1'; -- 16-bit flash
323 byten <= '1'; -- 16-bit flash
316 memi.brdyn <= '1'; memi.bexcn <= '1';
324 memi.brdyn <= '1'; memi.bexcn <= '1';
317 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
325 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
318
326
319 mg0 : if (CFG_MCTRL_LEON2 = 0) generate
327 mg0 : if (CFG_MCTRL_LEON2 = 0) generate
320 apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
328 apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
321 roms_pad : outpad generic map (tech => padtech)
329 roms_pad : outpad generic map (tech => padtech)
322 port map (romsn, vcc(0));
330 port map (romsn, vcc(0));
323 end generate;
331 end generate;
324
332
325 mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
333 mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
326 addr_pad : outpadv generic map (width => 24, tech => padtech)
334 addr_pad : outpadv generic map (width => 24, tech => padtech)
327 port map (address, memo.address(23 downto 0));
335 port map (address, memo.address(23 downto 0));
328 roms_pad : outpad generic map (tech => padtech)
336 roms_pad : outpad generic map (tech => padtech)
329 port map (romsn, memo.romsn(0));
337 port map (romsn, memo.romsn(0));
330 oen_pad : outpad generic map (tech => padtech)
338 oen_pad : outpad generic map (tech => padtech)
331 port map (oen, memo.oen);
339 port map (oen, memo.oen);
332 wri_pad : outpad generic map (tech => padtech)
340 wri_pad : outpad generic map (tech => padtech)
333 port map (writen, memo.writen);
341 port map (writen, memo.writen);
334
342
335 -- pragma translate_off
343 -- pragma translate_off
336 iosn_pad : outpad generic map (tech => padtech)
344 iosn_pad : outpad generic map (tech => padtech)
337 port map (iosn, memo.iosn);
345 port map (iosn, memo.iosn);
338 tbdr : for i in 0 to 1 generate
346 tbdr : for i in 0 to 1 generate
339 data_pad : iopadv generic map (tech => padtech, width => 8)
347 data_pad : iopadv generic map (tech => padtech, width => 8)
340 port map (testdata(15-i*8 downto 8-i*8), memo.data(15-i*8 downto 8-i*8),
348 port map (testdata(15-i*8 downto 8-i*8), memo.data(15-i*8 downto 8-i*8),
341 memo.bdrive(i+2), memi.data(15-i*8 downto 8-i*8));
349 memo.bdrive(i+2), memi.data(15-i*8 downto 8-i*8));
342 end generate;
350 end generate;
343 -- pragma translate_on
351 -- pragma translate_on
344
352
345 -- bdr : for i in 0 to 1 generate
353 -- bdr : for i in 0 to 1 generate
346 -- data_pad : iopadv generic map (tech => padtech, width => 8)
354 -- data_pad : iopadv generic map (tech => padtech, width => 8)
347 -- port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8),
355 -- port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8),
348 -- memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
356 -- memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
349 -- end generate;
357 -- end generate;
350 end generate;
358 end generate;
351
359
352 ----------------------------------------------------------------------
360 ----------------------------------------------------------------------
353 --- DDR memory controller -------------------------------------------
361 --- DDR memory controller -------------------------------------------
354 ----------------------------------------------------------------------
362 ----------------------------------------------------------------------
355
363
356 ddrsp0 : if (CFG_DDRSP /= 0) generate
364 ddrsp0 : if (CFG_DDRSP /= 0) generate
357
365
358 ddrc : ddrspa generic map ( fabtech => spartan3e, memtech => memtech,
366 ddrc : ddrspa generic map ( fabtech => spartan3e, memtech => memtech,
359 hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
367 hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
360 pwron => CFG_DDRSP_INIT, MHz => 2*BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW,
368 pwron => CFG_DDRSP_INIT, MHz => 2*BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW,
361 clkmul => CFG_DDRSP_FREQ/10, clkdiv => 2*5, col => CFG_DDRSP_COL,
369 clkmul => CFG_DDRSP_FREQ/10, clkdiv => 2*5, col => CFG_DDRSP_COL,
362 Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16)
370 Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16)
363 port map (
371 port map (
364 cgo.clklock, rstn, clk2x, clkm, lock, clkml, clkml, ahbsi, ahbso(4),
372 cgo.clklock, rstn, clk2x, clkm, lock, clkml, clkml, ahbsi, ahbso(4),
365 ddr_clk, ddr_clkb, open, ddr_clk_fb,
373 ddr_clk, ddr_clkb, open, ddr_clk_fb,
366 ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
374 ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
367 ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
375 ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
368
376
369 ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
377 ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
370 ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0);
378 ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0);
371 ddr_ad <= ddr_adl(12 downto 0);
379 ddr_ad <= ddr_adl(12 downto 0);
372 end generate;
380 end generate;
373
381
374 noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
382 noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
375
383
376 ----------------------------------------------------------------------
384 ----------------------------------------------------------------------
377 --- APB Bridge and various periherals -------------------------------
385 --- APB Bridge and various periherals -------------------------------
378 ----------------------------------------------------------------------
386 ----------------------------------------------------------------------
379
387
380 apb0 : apbctrl -- AHB/APB bridge
388 apb0 : apbctrl -- AHB/APB bridge
381 generic map (hindex => 1, haddr => CFG_APBADDR)
389 generic map (hindex => 1, haddr => CFG_APBADDR)
382 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
390 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
383
391
384 ua1 : if CFG_UART1_ENABLE /= 0 generate
392 ua1 : if CFG_UART1_ENABLE /= 0 generate
385 uart1 : apbuart -- UART 1
393 uart1 : apbuart -- UART 1
386 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
394 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
387 fifosize => CFG_UART1_FIFO)
395 fifosize => CFG_UART1_FIFO)
388 port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
396 port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
389 u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
397 u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
390 serrx_pad : inpad generic map (tech => padtech) port map (urxd1, rxd1);
398 serrx_pad : inpad generic map (tech => padtech) port map (urxd1, rxd1);
391 sertx_pad : outpad generic map (tech => padtech) port map (utxd1, txd1);
399 sertx_pad : outpad generic map (tech => padtech) port map (utxd1, txd1);
392 led(0) <= not rxd1; led(1) <= not txd1;
400 led(0) <= not rxd1; led(1) <= not txd1;
393 end generate;
401 end generate;
394 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
402 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
395
403
396 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
404 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
397 irqctrl0 : irqmp -- interrupt controller
405 irqctrl0 : irqmp -- interrupt controller
398 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
406 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
399 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
407 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
400 end generate;
408 end generate;
401 irq3 : if CFG_IRQ3_ENABLE = 0 generate
409 irq3 : if CFG_IRQ3_ENABLE = 0 generate
402 x : for i in 0 to CFG_NCPU-1 generate
410 x : for i in 0 to CFG_NCPU-1 generate
403 irqi(i).irl <= "0000";
411 irqi(i).irl <= "0000";
404 end generate;
412 end generate;
405 apbo(2) <= apb_none;
413 apbo(2) <= apb_none;
406 end generate;
414 end generate;
407
415
408 gpt : if CFG_GPT_ENABLE /= 0 generate
416 gpt : if CFG_GPT_ENABLE /= 0 generate
409 timer0 : gptimer -- timer unit
417 timer0 : gptimer -- timer unit
410 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
418 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
411 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
419 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
412 nbits => CFG_GPT_TW)
420 nbits => CFG_GPT_TW)
413 port map (rstn, clkm, apbi, apbo(3), gpti, open);
421 port map (rstn, clkm, apbi, apbo(3), gpti, open);
414 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
422 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
415 end generate;
423 end generate;
416 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
424 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
417
425
418 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
426 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
419 grgpio0: grgpio
427 grgpio0: grgpio
420 generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
428 generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
421 nbits => 12 --CFG_GRGPIO_WIDTH
429 nbits => 12 --CFG_GRGPIO_WIDTH
422 )
430 )
423 port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
431 port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
424
432
425 end generate;
433 end generate;
426
434
427 kbd : if CFG_KBD_ENABLE /= 0 generate
435 kbd : if CFG_KBD_ENABLE /= 0 generate
428 ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
436 ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
429 port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
437 port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
430 kbdclk_pad : iopad generic map (tech => padtech)
438 kbdclk_pad : iopad generic map (tech => padtech)
431 port map (ps2clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
439 port map (ps2clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
432 kbdata_pad : iopad generic map (tech => padtech)
440 kbdata_pad : iopad generic map (tech => padtech)
433 port map (ps2data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
441 port map (ps2data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
434 end generate;
442 end generate;
435 nokbd : if CFG_KBD_ENABLE = 0 generate
443 nokbd : if CFG_KBD_ENABLE = 0 generate
436 apbo(5) <= apb_none; kbdo <= ps2o_none;
444 apbo(5) <= apb_none; kbdo <= ps2o_none;
437 end generate;
445 end generate;
438
446
439 -- vga : if CFG_VGA_ENABLE /= 0 generate
447 -- vga : if CFG_VGA_ENABLE /= 0 generate
440 -- vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
448 -- vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
441 -- port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
449 -- port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
442 -- video_clock_pad : outpad generic map ( tech => padtech)
450 -- video_clock_pad : outpad generic map ( tech => padtech)
443 -- port map (vid_clock, dac_clk);
451 -- port map (vid_clock, dac_clk);
444 -- dac_clk <= not clkm;
452 -- dac_clk <= not clkm;
445 -- end generate;
453 -- end generate;
446
454
447 svga : if CFG_SVGA_ENABLE /= 0 generate
455 svga : if CFG_SVGA_ENABLE /= 0 generate
448 svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
456 svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
449 hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
457 hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
450 clk0 => 1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
458 clk0 => 1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
451 clk1 => 0, clk2 => 0, burstlen => 5)
459 clk1 => 0, clk2 => 0, burstlen => 5)
452 port map(rstn, clkm, clkm, apbi, apbo(6), vgao, ahbmi,
460 port map(rstn, clkm, clkm, apbi, apbo(6), vgao, ahbmi,
453 ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
461 ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
454 end generate;
462 end generate;
455
463
456 -- blank_pad : outpad generic map (tech => padtech)
464 -- blank_pad : outpad generic map (tech => padtech)
457 -- port map (vid_blankn, vgao.blank);
465 -- port map (vid_blankn, vgao.blank);
458 -- comp_sync_pad : outpad generic map (tech => padtech)
466 -- comp_sync_pad : outpad generic map (tech => padtech)
459 -- port map (vid_syncn, vgao.comp_sync);
467 -- port map (vid_syncn, vgao.comp_sync);
460 vert_sync_pad : outpad generic map (tech => padtech)
468 vert_sync_pad : outpad generic map (tech => padtech)
461 port map (vid_vsync, vgao.vsync);
469 port map (vid_vsync, vgao.vsync);
462 horiz_sync_pad : outpad generic map (tech => padtech)
470 horiz_sync_pad : outpad generic map (tech => padtech)
463 port map (vid_hsync, vgao.hsync);
471 port map (vid_hsync, vgao.hsync);
464 video_out_r_pad : outpad generic map (tech => padtech)
472 video_out_r_pad : outpad generic map (tech => padtech)
465 port map (vid_r, vgao.video_out_r(7));
473 port map (vid_r, vgao.video_out_r(7));
466 video_out_g_pad : outpad generic map (tech => padtech)
474 video_out_g_pad : outpad generic map (tech => padtech)
467 port map (vid_g, vgao.video_out_g(7));
475 port map (vid_g, vgao.video_out_g(7));
468 video_out_b_pad : outpad generic map (tech => padtech)
476 video_out_b_pad : outpad generic map (tech => padtech)
469 port map (vid_b, vgao.video_out_b(7));
477 port map (vid_b, vgao.video_out_b(7));
470
478
471
479
472 -----------------------------------------------------------------------
480 -----------------------------------------------------------------------
473 --- LCD CONTROLER ----------------------------------------------------
481 --- LCD CONTROLER ----------------------------------------------------
474 -----------------------------------------------------------------------
482 -----------------------------------------------------------------------
475
483
476 LCD0 : apb_lcd_ctrlr
484 LCD0 : apb_lcd_ctrlr
477 generic map( 8, 8,16#fff#,0,8)
485 generic map( 8, 8,16#fff#,0,8)
478 Port map( rstn,clkm,apbi, apbo(8),data(15 downto 8),LCD_RS,LCD_RW,LCD_E,LCD_RET,LCD_CS1,LCD_CS2,SF_CE0);
486 Port map( rstn,clkm,apbi, apbo(8),data(15 downto 8),LCD_RS,LCD_RW,LCD_E,LCD_RET,LCD_CS1,LCD_CS2,SF_CE0);
479
487
480 -----------------------------------------------------------------------
488 -----------------------------------------------------------------------
489 --- ADS7886 ----------------------------------------------------
490 -----------------------------------------------------------------------
491
492 ADC0 : lpp_apb_ad_conv
493 generic map(9,9,16#fff#,0,8,1,50000,100,ADS7886)
494 Port map(clkm,rstn,apbi, apbo(9),AD_in,AD_out);
495
496 AD_in(0).SDI <= ADC_SDI;
497 ADC_CNV <= AD_out.CNV;
498 ADC_SCK <= AD_out.SCK;
499 -----------------------------------------------------------------------
481 --- ETHERNET ---------------------------------------------------------
500 --- ETHERNET ---------------------------------------------------------
482 -----------------------------------------------------------------------
501 -----------------------------------------------------------------------
483
502
484 eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
503 eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
485 e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
504 e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
486 pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
505 pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
487 mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
506 mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
488 nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
507 nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
489 macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
508 macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
490 ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
509 ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
491 phyrstadr => 31, giga => CFG_GRETH1G)
510 phyrstadr => 31, giga => CFG_GRETH1G)
492 port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
511 port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
493 ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
512 ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
494 apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
513 apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
495
514
496 emdio_pad : iopad generic map (tech => padtech)
515 emdio_pad : iopad generic map (tech => padtech)
497 port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
516 port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
498 etxc_pad : inpad generic map (tech => padtech)
517 etxc_pad : inpad generic map (tech => padtech)
499 port map (etx_clk, ethi.tx_clk);
518 port map (etx_clk, ethi.tx_clk);
500 erxc_pad : inpad generic map (tech => padtech)
519 erxc_pad : inpad generic map (tech => padtech)
501 port map (erx_clk, ethi.rx_clk);
520 port map (erx_clk, ethi.rx_clk);
502 erxd_pad : inpadv generic map (tech => padtech, width => 4)
521 erxd_pad : inpadv generic map (tech => padtech, width => 4)
503 port map (erxd, ethi.rxd(3 downto 0));
522 port map (erxd, ethi.rxd(3 downto 0));
504 erxdv_pad : inpad generic map (tech => padtech)
523 erxdv_pad : inpad generic map (tech => padtech)
505 port map (erx_dv, ethi.rx_dv);
524 port map (erx_dv, ethi.rx_dv);
506 erxer_pad : inpad generic map (tech => padtech)
525 erxer_pad : inpad generic map (tech => padtech)
507 port map (erx_er, ethi.rx_er);
526 port map (erx_er, ethi.rx_er);
508 erxco_pad : inpad generic map (tech => padtech)
527 erxco_pad : inpad generic map (tech => padtech)
509 port map (erx_col, ethi.rx_col);
528 port map (erx_col, ethi.rx_col);
510 erxcr_pad : inpad generic map (tech => padtech)
529 erxcr_pad : inpad generic map (tech => padtech)
511 port map (erx_crs, ethi.rx_crs);
530 port map (erx_crs, ethi.rx_crs);
512
531
513 etxd_pad : outpadv generic map (tech => padtech, width => 4)
532 etxd_pad : outpadv generic map (tech => padtech, width => 4)
514 port map (etxd, etho.txd(3 downto 0));
533 port map (etxd, etho.txd(3 downto 0));
515 etxen_pad : outpad generic map (tech => padtech)
534 etxen_pad : outpad generic map (tech => padtech)
516 port map (etx_en, etho.tx_en);
535 port map (etx_en, etho.tx_en);
517 etxer_pad : outpad generic map (tech => padtech)
536 etxer_pad : outpad generic map (tech => padtech)
518 port map (etx_er, etho.tx_er);
537 port map (etx_er, etho.tx_er);
519 emdc_pad : outpad generic map (tech => padtech)
538 emdc_pad : outpad generic map (tech => padtech)
520 port map (emdc, etho.mdc);
539 port map (emdc, etho.mdc);
521
540
522 end generate;
541 end generate;
523
542
524 -----------------------------------------------------------------------
543 -----------------------------------------------------------------------
525 --- AHB DMA ----------------------------------------------------------
544 --- AHB DMA ----------------------------------------------------------
526 -----------------------------------------------------------------------
545 -----------------------------------------------------------------------
527
546
528 -- dma0 : ahbdma
547 -- dma0 : ahbdma
529 -- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH,
548 -- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH,
530 -- pindex => 12, paddr => 12, dbuf => 32)
549 -- pindex => 12, paddr => 12, dbuf => 32)
531 -- port map (rstn, clkm, apbi, apbo(12), ahbmi,
550 -- port map (rstn, clkm, apbi, apbo(12), ahbmi,
532 -- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH));
551 -- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH));
533 --
552 --
534 -- at0 : ahbtrace
553 -- at0 : ahbtrace
535 -- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
554 -- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
536 -- tech => memtech, irq => 0, kbytes => 8)
555 -- tech => memtech, irq => 0, kbytes => 8)
537 -- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
556 -- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
538
557
539 -----------------------------------------------------------------------
558 -----------------------------------------------------------------------
540 --- AHB ROM ----------------------------------------------------------
559 --- AHB ROM ----------------------------------------------------------
541 -----------------------------------------------------------------------
560 -----------------------------------------------------------------------
542
561
543 bpromgen : if CFG_AHBROMEN /= 0 generate
562 bpromgen : if CFG_AHBROMEN /= 0 generate
544 brom : entity work.ahbrom
563 brom : entity work.ahbrom
545 generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
564 generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
546 port map ( rstn, clkm, ahbsi, ahbso(6));
565 port map ( rstn, clkm, ahbsi, ahbso(6));
547 end generate;
566 end generate;
548 nobpromgen : if CFG_AHBROMEN = 0 generate
567 nobpromgen : if CFG_AHBROMEN = 0 generate
549 ahbso(6) <= ahbs_none;
568 ahbso(6) <= ahbs_none;
550 end generate;
569 end generate;
551
570
552 -----------------------------------------------------------------------
571 -----------------------------------------------------------------------
553 --- AHB RAM ----------------------------------------------------------
572 --- AHB RAM ----------------------------------------------------------
554 -----------------------------------------------------------------------
573 -----------------------------------------------------------------------
555
574
556 ahbramgen : if CFG_AHBRAMEN = 1 generate
575 ahbramgen : if CFG_AHBRAMEN = 1 generate
557 ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
576 ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
558 tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
577 tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
559 port map (rstn, clkm, ahbsi, ahbso(3));
578 port map (rstn, clkm, ahbsi, ahbso(3));
560 end generate;
579 end generate;
561 nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
580 nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
562
581
563 -----------------------------------------------------------------------
582 -----------------------------------------------------------------------
564 --- Drive unused bus elements ---------------------------------------
583 --- Drive unused bus elements ---------------------------------------
565 -----------------------------------------------------------------------
584 -----------------------------------------------------------------------
566
585
567 nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE+1) to NAHBMST-1 generate
586 nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE+1) to NAHBMST-1 generate
568 ahbmo(i) <= ahbm_none;
587 ahbmo(i) <= ahbm_none;
569 end generate;
588 end generate;
570 -- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
589 -- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
571 -- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
590 -- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
572
591
573 -- resoutn <= rstn;
592 -- resoutn <= rstn;
574
593
575 -----------------------------------------------------------------------
594 -----------------------------------------------------------------------
576 --- Boot message ----------------------------------------------------
595 --- Boot message ----------------------------------------------------
577 -----------------------------------------------------------------------
596 -----------------------------------------------------------------------
578
597
579 -- pragma translate_off
598 -- pragma translate_off
580 x : report_version
599 x : report_version
581 generic map (
600 generic map (
582 msg1 => "LEON3 Demonstration design for Digilent Spartan3E Eval board",
601 msg1 => "LEON3 Demonstration design for Digilent Spartan3E Eval board",
583 msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
602 msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
584 & "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
603 & "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
585 msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
604 msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
586 mdel => 1
605 mdel => 1
587 );
606 );
588 -- pragma translate_on
607 -- pragma translate_on
589
608
590 end rtl;
609 end rtl;
Show file before | Show file after | Hide comments
@@ -1,54 +1,55
1 <?xml version="1.0" encoding="UTF-8" ?>
1 <?xml version="1.0" encoding="UTF-8" ?>
2 <document>
2 <document>
3 <!--The data in this file is primarily intended for consumption by Xilinx tools.
3 <!--The data in this file is primarily intended for consumption by Xilinx tools.
4 The structure and the elements are likely to change over the next few releases.
4 The structure and the elements are likely to change over the next few releases.
5 This means code written to parse this file will need to be revisited each subsequent release.-->
5 This means code written to parse this file will need to be revisited each subsequent release.-->
6 <application name="pn" timeStamp="Fri Nov 19 17:53:38 2010">
6 <application name="pn" timeStamp="Wed Dec 1 15:45:26 2010">
7 <section name="Project Information" visible="false">
7 <section name="Project Information" visible="false">
8 <property name="ProjectID" value="214AC12F50044F7DCEADE307DAD17AB8" type="project"/>
8 <property name="ProjectID" value="144BAC8BCC020358A10E3C9EB2A797A8" type="project"/>
9 <property name="ProjectIteration" value="5" type="project"/>
9 <property name="ProjectIteration" value="9" type="project"/>
10 <property name="ProjectFile" value="/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-digilent-xc3s1600e/leon3mp.xise" type="project"/>
10 <property name="ProjectFile" value="/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp.xise" type="project"/>
11 <property name="ProjectCreationTimestamp" value="2010-11-19T09:49:20" type="project"/>
11 <property name="ProjectCreationTimestamp" value="2010-12-01T11:32:09" type="project"/>
12 </section>
12 </section>
13 <section name="Project Statistics" visible="true">
13 <section name="Project Statistics" visible="true">
14 <property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
14 <property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
15 <property name="PROP_FitterReportFormat" value="HTML" type="process"/>
15 <property name="PROP_FitterReportFormat" value="HTML" type="process"/>
16 <property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
16 <property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
17 <property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
17 <property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
18 <property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
18 <property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
19 <property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
19 <property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
20 <property name="PROP_Simulator" value="Modelsim-SE Mixed" type="design"/>
20 <property name="PROP_Simulator" value="Modelsim-SE Mixed" type="design"/>
21 <property name="PROP_SynthFsmEncode" value="None" type="process"/>
21 <property name="PROP_SynthFsmEncode" value="None" type="process"/>
22 <property name="PROP_SynthTopFile" value="changed" type="process"/>
22 <property name="PROP_SynthTopFile" value="changed" type="process"/>
23 <property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
23 <property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
24 <property name="PROP_UseSmartGuide" value="false" type="design"/>
24 <property name="PROP_UseSmartGuide" value="false" type="design"/>
25 <property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
25 <property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
26 <property name="PROP_intProjectCreationTimestamp" value="2010-11-19T09:49:20" type="design"/>
26 <property name="PROP_intProjectCreationTimestamp" value="2010-12-01T11:32:09" type="design"/>
27 <property name="PROP_intWbtProjectID" value="214AC12F50044F7DCEADE307DAD17AB8" type="design"/>
27 <property name="PROP_intWbtProjectID" value="144BAC8BCC020358A10E3C9EB2A797A8" type="design"/>
28 <property name="PROP_intWbtProjectIteration" value="5" type="process"/>
28 <property name="PROP_intWbtProjectIteration" value="9" type="process"/>
29 <property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
29 <property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
30 <property name="PROP_intWorkingDirUsed" value="No" type="design"/>
30 <property name="PROP_intWorkingDirUsed" value="No" type="design"/>
31 <property name="PROP_map_otherCmdLineOptions" value="-timing" type="process"/>
31 <property name="PROP_map_otherCmdLineOptions" value="-timing" type="process"/>
32 <property name="PROP_xilxBitgCfg_GenOpt_DRC" value="false" type="process"/>
32 <property name="PROP_xilxBitgCfg_GenOpt_DRC" value="false" type="process"/>
33 <property name="PROP_xilxBitgCfg_GenOpt_ReadBack" value="true" type="process"/>
33 <property name="PROP_xilxBitgCfg_GenOpt_ReadBack" value="true" type="process"/>
34 <property name="PROP_xilxBitgStart_Clk_DriveDone" value="true" type="process"/>
34 <property name="PROP_xilxBitgStart_Clk_DriveDone" value="true" type="process"/>
35 <property name="PROP_xilxMapPackRegInto" value="For Inputs and Outputs" type="process"/>
35 <property name="PROP_xilxMapPackRegInto" value="For Inputs and Outputs" type="process"/>
36 <property name="PROP_xilxNgdbldMacro" value="changed" type="process"/>
36 <property name="PROP_xilxNgdbldMacro" value="changed" type="process"/>
37 <property name="PROP_xilxNgdbld_AUL" value="true" type="process"/>
37 <property name="PROP_xilxNgdbld_AUL" value="true" type="process"/>
38 <property name="PROP_xstBusDelimiter" value="()" type="process"/>
38 <property name="PROP_xstBusDelimiter" value="()" type="process"/>
39 <property name="PROP_xstPackIORegister" value="Yes" type="process"/>
39 <property name="PROP_xstPackIORegister" value="Yes" type="process"/>
40 <property name="PROP_xst_otherCmdLineOptions" value="-uc leon3mp.xcf" type="process"/>
40 <property name="PROP_xst_otherCmdLineOptions" value="-uc leon3mp.xcf" type="process"/>
41 <property name="PROP_AutoTop" value="false" type="design"/>
41 <property name="PROP_AutoTop" value="false" type="design"/>
42 <property name="PROP_DevFamily" value="Spartan3E" type="design"/>
42 <property name="PROP_DevFamily" value="Spartan3E" type="design"/>
43 <property name="PROP_WriteDefaultPropToSourceProject" value="false" type="process"/>
43 <property name="PROP_xilxBitgCfg_GenOpt_MaskFile" value="true" type="process"/>
44 <property name="PROP_xilxBitgCfg_GenOpt_MaskFile" value="true" type="process"/>
44 <property name="PROP_DevDevice" value="xc3s1600e" type="design"/>
45 <property name="PROP_DevDevice" value="xc3s1600e" type="design"/>
45 <property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/>
46 <property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/>
46 <property name="PROP_DevPackage" value="fg320" type="design"/>
47 <property name="PROP_DevPackage" value="fg320" type="design"/>
47 <property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
48 <property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
48 <property name="PROP_DevSpeed" value="-4" type="design"/>
49 <property name="PROP_DevSpeed" value="-4" type="design"/>
49 <property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
50 <property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
50 <property name="FILE_UCF" value="1" type="source"/>
51 <property name="FILE_UCF" value="1" type="source"/>
51 <property name="FILE_VHDL" value="284" type="source"/>
52 <property name="FILE_VHDL" value="302" type="source"/>
52 </section>
53 </section>
53 </application>
54 </application>
54 </document>
55 </document>
Show file before | Show file after | Hide comments
@@ -1,54 +1,98
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 library IEEE;
19 library IEEE;
20 use IEEE.STD_LOGIC_1164.ALL;
20 use IEEE.STD_LOGIC_1164.ALL;
21
21 library lpp;
22
22 use lpp.lpp_ad_conv.all;
23 use lpp.general_purpose.Clk_divider;
23
24
24 entity AD7688_drvr is
25 entity AD7688_drvr is
25 generic(ChanelCount : integer;
26 generic(ChanelCount : integer;
26 clkkHz : integer);
27 clkkHz : integer);
27 Port ( clk : in STD_LOGIC;
28 Port ( clk : in STD_LOGIC;
28 reset : in STD_LOGIC;
29 reset : in STD_LOGIC;
29 smplClk: in STD_LOGIC;
30 smplClk: in STD_LOGIC;
31 DataReady : out std_logic;
30 smpout : out Samples_out(ChanelCount-1 downto 0);
32 smpout : out Samples_out(ChanelCount-1 downto 0);
31 AD_in : in AD7688_in(ChanelCount-1 downto 0);
33 AD_in : in AD7688_in(ChanelCount-1 downto 0);
32 AD_out : out AD7688_out);
34 AD_out : out AD7688_out);
33 end AD7688_drvr;
35 end AD7688_drvr;
34
36
35 architecture ar_AD7688_drvr of AD7688_drvr is
37 architecture ar_AD7688_drvr of AD7688_drvr is
36
38
37 constant convTrigger : integer:= clkkHz*1.6/1000; --tconv = 1.6µs
39 constant convTrigger : integer:= clkkHz*16/10000; --tconv = 1.6µs
38
40
39 signal i : integer range 0 to convTrigger :=0;
41 signal i : integer range 0 to convTrigger :=0;
42 signal clk_int : std_logic;
43 signal smplClk_reg : std_logic;
44 signal cnv_int : std_logic;
40
45
41 begin
46 begin
42
47
48 clkdiv: if clkkHz>=66000 generate
49 clkdivider: Clk_divider
50 generic map(clkkHz*1000,60000000)
51 Port map( clk ,reset,clk_int);
52 end generate;
53
54 clknodiv: if clkkHz<66000 generate
55 nodiv: clk_int <= clk;
56 end generate;
57
58 AD_out.CNV <= cnv_int;
59 AD_out.SCK <= clk_int;
60
61
43 sckgen: process(clk,reset)
62 sckgen: process(clk,reset)
44 begin
63 begin
45 if reset = '0' then
64 if reset = '0' then
46 i <= 0;
65 i <= 0;
47 AD_out.CNV <= '0';
66 cnv_int <= '0';
67 smplClk_reg <= '0';
48 elsif clk'event and clk = '1' then
68 elsif clk'event and clk = '1' then
69 if smplClk = '1' and smplClk_reg = '0' then
70 if i = convTrigger then
71 smplClk_reg <= '1';
72 i <= 0;
73 cnv_int <= '0';
74 else
75 i <= i+1;
76 cnv_int <= '1';
77 end if;
78 elsif smplClk = '0' and smplClk_reg = '1' then
79 smplClk_reg <= '0';
80 end if;
49 end if;
81 end if;
50 end process;
82 end process;
51
83
52
84
85
86 spidrvr: AD7688_spi_if
87 generic map(ChanelCount)
88 Port map(clk_int,reset,cnv_int,DataReady,AD_in,smpout);
89
90
91
53 end ar_AD7688_drvr;
92 end ar_AD7688_drvr;
54
93
94
95
96
97
98
Show file before | Show file after | Hide comments
@@ -1,59 +1,112
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19
19 library IEEE;
20 library IEEE;
20 use IEEE.STD_LOGIC_1164.all;
21 use IEEE.STD_LOGIC_1164.all;
21
22 library grlib;
23 use grlib.amba.all;
24 use grlib.stdlib.all;
25 use grlib.devices.all;
22
26
23
27
24 package lpp_ad_conv is
28 package lpp_ad_conv is
25
29
30
31 constant AD7688 : integer := 0;
32 constant ADS7886 : integer := 1;
33
26
34
27 type AD7688_out is
35 type AD7688_out is
28 record
36 record
29 CNV : std_logic;
37 CNV : std_logic;
30 SCK : std_logic;
38 SCK : std_logic;
31 end record;
39 end record;
32
40
33 type AD7688_in_element is
41 type AD7688_in_element is
34 record
42 record
35 SDI : std_logic;
43 SDI : std_logic;
36 end record;
44 end record;
37
45
38 type AD7688_in is array(natural range <>) of AD7688_in_element;
46 type AD7688_in is array(natural range <>) of AD7688_in_element;
39
47
40 type Samples_out is array(natural range <>) of std_logic_vector(15 downto 0);
48 type Samples_out is array(natural range <>) of std_logic_vector(15 downto 0);
41
49
42 component AD7688_drvr is
50 component AD7688_drvr is
43 generic(ChanelCount : integer;
51 generic(ChanelCount : integer;
44 clkkHz : integer);
52 clkkHz : integer);
45 Port ( clk : in STD_LOGIC;
53 Port ( clk : in STD_LOGIC;
46 reset : in STD_LOGIC;
54 reset : in STD_LOGIC;
47 smplClk: in STD_LOGIC;
55 smplClk: in STD_LOGIC;
56 DataReady : out std_logic;
48 smpout : out Samples_out(ChanelCount-1 downto 0);
57 smpout : out Samples_out(ChanelCount-1 downto 0);
49 AD_in : in AD7688_in(ChanelCount-1 downto 0);
58 AD_in : in AD7688_in(ChanelCount-1 downto 0);
50 AD_out : out AD7688_out);
59 AD_out : out AD7688_out);
51 end component;
60 end component;
52
61
53
62
63 component AD7688_spi_if is
64 generic(ChanelCount : integer);
65 Port( clk : in STD_LOGIC;
66 reset : in STD_LOGIC;
67 cnv : in STD_LOGIC;
68 DataReady: out std_logic;
69 sdi : in AD7688_in(ChanelCount-1 downto 0);
70 smpout : out Samples_out(ChanelCount-1 downto 0)
71 );
72 end component;
54
73
55
74
75 component lpp_apb_ad_conv
76 generic(
77 pindex : integer := 0;
78 paddr : integer := 0;
79 pmask : integer := 16#fff#;
80 pirq : integer := 0;
81 abits : integer := 8;
82 ChanelCount : integer := 1;
83 clkkHz : integer := 50000;
84 smpClkHz : integer := 100;
85 ADCref : integer := AD7688);
86 Port (
87 clk : in STD_LOGIC;
88 reset : in STD_LOGIC;
89 apbi : in apb_slv_in_type;
90 apbo : out apb_slv_out_type;
91 AD_in : in AD7688_in(ChanelCount-1 downto 0);
92 AD_out : out AD7688_out);
93 end component;
94
95 component ADS7886_drvr is
96 generic(ChanelCount : integer;
97 clkkHz : integer);
98 Port (
99 clk : in STD_LOGIC;
100 reset : in STD_LOGIC;
101 smplClk : in STD_LOGIC;
102 DataReady : out std_logic;
103 smpout : out Samples_out(ChanelCount-1 downto 0);
104 AD_in : in AD7688_in(ChanelCount-1 downto 0);
105 AD_out : out AD7688_out
106 );
107 end component;
108
56
109
57 end lpp_ad_conv;
110 end lpp_ad_conv;
58
111
59
112
Show file before | Show file after | Hide comments
@@ -1,77 +1,77
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 library ieee;
19 library ieee;
20 use ieee.std_logic_1164.all;
20 use ieee.std_logic_1164.all;
21 library grlib;
21 library grlib;
22 use grlib.amba.all;
22 use grlib.amba.all;
23 -- pragma translate_off
23 -- pragma translate_off
24 use std.textio.all;
24 use std.textio.all;
25 -- pragma translate_on
25 -- pragma translate_on
26
26
27
27
28
28
29 package lpp_amba is
29 package lpp_amba is
30
30
31 constant VENDOR_LPP : amba_vendor_type := 16#19#;
31 constant VENDOR_LPP : amba_vendor_type := 16#19#;
32
32
33 -- LPP device ids
33 -- LPP device ids
34
34
35 constant ROCKET_TM : amba_device_type := 16#001#;
35 constant ROCKET_TM : amba_device_type := 16#001#;
36 constant otherCore : amba_device_type := 16#002#;
36 constant otherCore : amba_device_type := 16#002#;
37 constant LPP_SIMPLE_DIODE : amba_device_type := 16#003#;
37 constant LPP_SIMPLE_DIODE : amba_device_type := 16#003#;
38 constant LPP_MULTI_DIODE : amba_device_type := 16#004#;
38 constant LPP_MULTI_DIODE : amba_device_type := 16#004#;
39 constant LPP_LCD_CTRLR : amba_device_type := 16#005#;
39 constant LPP_LCD_CTRLR : amba_device_type := 16#005#;
40 constant LPP_UART : amba_device_type := 16#006#;
40 constant LPP_UART : amba_device_type := 16#006#;
41 constant LPP_CNA : amba_device_type := 16#007#;
41 constant LPP_CNA : amba_device_type := 16#007#;
42
42 constant LPP_ADC_7688 : amba_device_type := 16#008#;
43
43
44 component APB_SIMPLE_DIODE is
44 component APB_SIMPLE_DIODE is
45 generic (
45 generic (
46 pindex : integer := 0;
46 pindex : integer := 0;
47 paddr : integer := 0;
47 paddr : integer := 0;
48 pmask : integer := 16#fff#;
48 pmask : integer := 16#fff#;
49 pirq : integer := 0;
49 pirq : integer := 0;
50 abits : integer := 8);
50 abits : integer := 8);
51 port (
51 port (
52 rst : in std_ulogic;
52 rst : in std_ulogic;
53 clk : in std_ulogic;
53 clk : in std_ulogic;
54 apbi : in apb_slv_in_type;
54 apbi : in apb_slv_in_type;
55 apbo : out apb_slv_out_type;
55 apbo : out apb_slv_out_type;
56 LED : out std_ulogic
56 LED : out std_ulogic
57 );
57 );
58 end component;
58 end component;
59
59
60
60
61 component APB_MULTI_DIODE is
61 component APB_MULTI_DIODE is
62 generic (
62 generic (
63 pindex : integer := 0;
63 pindex : integer := 0;
64 paddr : integer := 0;
64 paddr : integer := 0;
65 pmask : integer := 16#fff#;
65 pmask : integer := 16#fff#;
66 pirq : integer := 0;
66 pirq : integer := 0;
67 abits : integer := 8);
67 abits : integer := 8);
68 port (
68 port (
69 rst : in std_ulogic;
69 rst : in std_ulogic;
70 clk : in std_ulogic;
70 clk : in std_ulogic;
71 apbi : in apb_slv_in_type;
71 apbi : in apb_slv_in_type;
72 apbo : out apb_slv_out_type;
72 apbo : out apb_slv_out_type;
73 LED : out std_logic_vector(2 downto 0)
73 LED : out std_logic_vector(2 downto 0)
74 );
74 );
75 end component;
75 end component;
76
76
77 end;
77 end;
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
This diff has been collapsed as it changes many lines, (854 lines changed) Show them Hide them
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
This diff has been collapsed as it changes many lines, (1719 lines changed) Show them Hide them
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
General Comments 0
You need to be logged in to leave comments. Login now