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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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package lpp_ad_conv is
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type AD7688_out is
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record
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CNV : std_logic;
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SCK : std_logic;
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end record;
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type AD7688_in_element is
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record
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SDI : std_logic;
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end record;
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type AD7688_in is array(natural range <>) of AD7688_in_element;
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type Samples_out is array(natural range <>) of std_logic_vector(15 downto 0);
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component AD7688_drvr is
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generic(ChanelCount : integer;
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clkkHz : integer);
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Port ( clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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smplClk: in STD_LOGIC;
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smpout : out Samples_out(ChanelCount-1 downto 0);
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AD_in : in AD7688_in(ChanelCount-1 downto 0);
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AD_out : out AD7688_out);
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end component;
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end lpp_ad_conv;
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