HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r85:439b6d5bebcc

/!\ Unstable LFR-142200-DM-LEON3-BASE design /!\

jeandet@PC-DE-JEANDET.lpp.polytechnique.fr -

r85:439b6d5bebcc alexis

parent child

Context file:

r85:439b6d5bebcc

Collapse all files

LPP_drivers/exemples/hello/Makefile created 644 +44 0

@@ -0,0 +1,44
	1	#------------------------------------------------------------------------------
	2	#-- This file is a part of the LPP VHDL IP LIBRARY
	3	#-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
	4	#--
	5	#-- This program is free software; you can redistribute it and/or modify
	6	#-- it under the terms of the GNU General Public License as published by
	7	#-- the Free Software Foundation; either version 3 of the License, or
	8	#-- (at your option) any later version.
	9	#--
	10	#-- This program is distributed in the hope that it will be useful,
	11	#-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	#-- GNU General Public License for more details.
	14	#--
	15	#-- You should have received a copy of the GNU General Public License
	16	#-- along with this program; if not, write to the Free Software
	17	#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	#------------------------------------------------------------------------------
	19
	20	include ../../rules.mk
	21	LIBDIR=
	22	INCPATH = ../../includes
	23	SCRIPTDIR=../../scripts/
	24	LIBS=
	25	INPUTFILE=main.c
	26	EXEC=hello.bin
	27	OUTBINDIR=bin/
	28
	29
	30	.PHONY:bin
	31
	32	all:bin
	33	@echo $(EXEC)" file created"
	34
	35	clean:
	36	rm -f *.{o,a}
	37
	38
	39
	40	help:ruleshelp
	41	@echo " all : makes an executable file called "$(EXEC)
	42	@echo " in "$(OUTBINDIR)
	43	@echo " clean : removes temporary files"
	44

LPP_drivers/exemples/hello/main.c created 644 +26 0

@@ -0,0 +1,26
	1	/*------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------*/
	19	#include "stdio.h"
	20
	21
	22	int main()
	23	{
	24	printf("hello World\n");
	25	return 0;
	26	}

LPP_drivers/Doxyfile +12 -12

             # The PROJECT_NAME tag is a single word (or a sequence of words surrounded
             # by quotes) that should identify the project.
-            PROJECT_NAME           = "VHDL lib Drivers"
+            PROJECT_NAME           = "apb lcd driver"
             # The PROJECT_NUMBER tag can be used to enter a project or revision number.
             # This could be handy for archiving the generated documentation or
             # if some version control system is used.
-            PROJECT_NUMBER         = 0.4
+            PROJECT_NUMBER         = 0.1
             # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
             # base path where the generated documentation will be put.
             # name of the file that contains the anonymous namespace. By default
             # anonymous namespace are hidden.
-            EXTRACT_ANON_NSPACES   = YES
+            EXTRACT_ANON_NSPACES   = NO
             # If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all
             # undocumented members of documented classes, files or namespaces.
             # then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy
             # in the documentation. The default is NO.
-            SHOW_DIRECTORIES       = YES
+            SHOW_DIRECTORIES       = NO
             # Set the SHOW_FILES tag to NO to disable the generation of the Files page.
             # This will remove the Files entry from the Quick Index and from the
             # directories that contain example code fragments that are included (see
             # the \include command).
-            EXAMPLE_PATH           = Doc/ressources/examples
+            EXAMPLE_PATH           =
             # If the value of the EXAMPLE_PATH tag contains directories, you can use the
             # EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
             # each generated HTML page. If it is left blank doxygen will generate a
             # standard header.
-            HTML_HEADER            = Doc/ressources/Header
+            HTML_HEADER            =
             # The HTML_FOOTER tag can be used to specify a personal HTML footer for
             # each generated HTML page. If it is left blank doxygen will generate a
             # standard footer.
-            HTML_FOOTER            = Doc/ressources/Footer
+            HTML_FOOTER            =
             # The HTML_STYLESHEET tag can be used to specify a user-defined cascading
             # style sheet that is used by each HTML page. It can be used to
             # the style sheet file to the HTML output directory, so don't put your own
             # stylesheet in the HTML output directory as well, or it will be erased!
-            HTML_STYLESHEET        = Doc/ressources/doxygen.css
+            HTML_STYLESHEET        =
             # The HTML_COLORSTYLE_HUE tag controls the color of the HTML output.
             # Doxygen will adjust the colors in the stylesheet and background images
             # 180 is cyan, 240 is blue, 300 purple, and 360 is red again.
             # The allowed range is 0 to 359.
-            HTML_COLORSTYLE_HUE    = 218
+            HTML_COLORSTYLE_HUE    = 220
             # The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of
             # the colors in the HTML output. For a value of 0 the output will use
             # JavaScript, DHTML, CSS and frames is required (i.e. any modern browser).
             # Windows users are probably better off using the HTML help feature.
-            GENERATE_TREEVIEW      = YES
+            GENERATE_TREEVIEW      = NO
             # By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories,
             # and Class Hierarchy pages using a tree view instead of an ordered list.
             # toolkit from AT&T and Lucent Bell Labs. The other options in this section
             # have no effect if this option is set to NO (the default)
-            HAVE_DOT               = YES
+            HAVE_DOT               = NO
             # The DOT_NUM_THREADS specifies the number of dot invocations doxygen is
             # allowed to run in parallel. When set to 0 (the default) doxygen will
             # collaboration diagrams in a style similar to the OMG's Unified Modeling
             # Language.
-            UML_LOOK               = YES
+            UML_LOOK               = NO
             # If set to YES, the inheritance and collaboration graphs will show the
             # relations between templates and their instances.

LPP_drivers/exemples/ScanAPB/bin/ScanAPB.bin binary modified 0 0

NO CONTENT: modified file, binary diff hidden

LPP_drivers/scripts/load.txt +1 -1

	@@ -1,1 +1,1
	1	load bin/~~BenchFIFO~~.bin		1	load bin/hello.bin

Makefile +1 0

             doc:
+            	mkdir -p doc/html/
             	cp doc/ressources/*.jpg doc/html/
             	cp doc/ressources/doxygen.css doc/html/
             	make -C lib/lpp doc

designs/LFR-142200-DM-LEON3-BASE/config.vhd +4 -4

             -- Clock generator
               constant CFG_CLKTECH : integer := inferred;
-              constant CFG_CLKMUL : integer := (45);
+              constant CFG_CLKMUL : integer := (5);
-              constant CFG_CLKDIV : integer := (9);
+              constant CFG_CLKDIV : integer := (10);
-              constant CFG_OCLKDIV : integer := (8);
+              constant CFG_OCLKDIV : integer := (1);
               constant CFG_PCIDLL : integer := 0;
               constant CFG_PCISYSCLK: integer := 0;
               constant CFG_CLK_NOFB : integer := 0;
               constant CFG_DUART : integer := 0;
-            end;
  No newline at end of file
+            end;

designs/LFR-142200-DM-LEON3-BASE/leon3mp.vhd +244 -212

@@ -1,22 +1,23
1	-----------------------------------------------------------------------------~~-----~~	1	-----------------------------------------------------------------------------
2	-- Company:	2	-- LEON3 Demonstration design
3	-- Engineer:	3	-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4	--	4	--
5	-- Create Date: 17:16:12 03/29/2011	5	-- This program is free software; you can redistribute it and/or modify
6	-- Design Name:	6	-- it under the terms of the GNU General Public License as published by
7	-- Module Name: top - Behavioral	7	-- the Free Software Foundation; either version 2 of the License, or
8	-- Project Name:	8	-- (at your option) any later version.
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	--	9	--
13	-- Dependencies:	10	-- This program is distributed in the hope that it will be useful,
		11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		13	-- GNU General Public License for more details.
14	--	14	--
15	-- Revision:	15	-- You should have received a copy of the GNU General Public License
16	-- Revision 0.01 - File Created	16	-- along with this program; if not, write to the Free Software
17	-- Additional Comments:	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18	--	18	------------------------------------------------------------------------------
19	----------------------------------------------------------------------------------	19
		20
20	library ieee;	21	library ieee;
21	use ieee.std_logic_1164.all;	22	use ieee.std_logic_1164.all;
22	library grlib;	23	library grlib;
@@ -34,193 +35,157 use esa.memoryctrl.all;
34	use work.config.all;	35	use work.config.all;
35	library lpp;	36	library lpp;
36	use lpp.lpp_amba.all;	37	use lpp.lpp_amba.all;
37	use lpp.lpp_uart.all;
38	use lpp.lpp_memory.all;	38	use lpp.lpp_memory.all;
39	use lpp.general_purpose.all;	39	--use lpp.lpp_uart.all;
		40	--use lpp.lpp_matrix.all;
		41	--use lpp.lpp_usb.all;
		42
		43	entity leon3mp is
		44	generic (
		45	fabtech : integer := CFG_FABTECH;
		46	memtech : integer := CFG_MEMTECH;
		47	padtech : integer := CFG_PADTECH;
		48	clktech : integer := CFG_CLKTECH;
		49	disas : integer := CFG_DISAS; -- Enable disassembly to console
		50	dbguart : integer := CFG_DUART; -- Print UART on console
		51	pclow : integer := CFG_PCLOW
		52	);
		53	port (
		54	clk50MHz : in std_ulogic;
		55	reset : in std_ulogic;
		56	ramclk : out std_logic;
		57
		58	ahbrxd : in std_ulogic; -- DSU rx data
		59	ahbtxd : out std_ulogic; -- DSU tx data
		60	dsubre : in std_ulogic;
		61	dsuact : out std_ulogic;
		62	urxd1 : in std_ulogic; -- UART1 rx data
		63	utxd1 : out std_ulogic; -- UART1 tx data
		64	errorn : out std_ulogic;
		65
		66	address : out std_logic_vector(18 downto 0);
		67	data : inout std_logic_vector(31 downto 0);
40		68
41	entity miniamba is	69	nBWa : out std_logic;
42	generic (	70	nBWb : out std_logic;
43	fabtech : integer := CFG_FABTECH;	71	nBWc : out std_logic;
44	memtech : integer := CFG_MEMTECH;	72	nBWd : out std_logic;
45	padtech : integer := CFG_PADTECH;	73	nBWE : out std_logic;
46	clktech : integer := CFG_CLKTECH;	74	nADSC : out std_logic;
47	disas : integer := CFG_DISAS; -- Enable disassembly to console	75	nADSP : out std_logic;
48	dbguart : integer := CFG_DUART; -- Print UART on console	76	nADV : out std_logic;
49	pclow : integer := CFG_PCLOW);	77	nGW : out std_logic;
50	Port (	78	nCE1 : out std_logic;
51	clk50MHz : in STD_LOGIC;	79	CE2 : out std_logic;
52	reset : in STD_LOGIC;	80	nCE3 : out std_logic;
53	led : out std_logic_vector(1 downto 0);	81	nOE : out std_logic;
54	~~errorn~~ : out std_ulogic;	82	MODE : out std_logic;
55	~~dsubre~~ : in std_ulogic;	83	SSRAM_CLK : out std_logic;
56	~~dsuact~~ : out std_ulogic;	84	ZZ : out std_logic;
57	ahbrxd : in std_ulogic;	85	led : out std_logic_vector(1 downto 0)
58	ahbtxd : out std_ulogic;	86	);
59	urxd1 : in std_ulogic;	87	end;
60	utxd1 : out std_ulogic;
61	data : inout std_logic_vector(31 downto 0);
62	address : out std_logic_vector(18 downto 0);
63	nBWa : out std_logic;
64	nBWb : out std_logic;
65	nBWc : out std_logic;
66	nBWd : out std_logic;
67	nBWE : out std_logic;
68	nADSC : out std_logic;
69	nADSP : out std_logic;
70	nADV : out std_logic;
71	nGW : out std_logic;
72	nCE1 : out std_logic;
73	CE2 : out std_logic;
74	nCE3 : out std_logic;
75	nOE : out std_logic;
76	MODE : out std_logic;
77	SSRAM_CLK : out std_logic;
78	ZZ : out std_logic
79	);
80	end miniamba;
81		88
82	architecture Behavioral of ~~miniamba~~ is	89	architecture Behavioral of leon3mp is
		90
		91	constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
		92	CFG_GRETH+CFG_AHB_JTAG;
		93	constant maxahbm : integer := maxahbmsp;
83		94
		95	--Clk & Rst g�n�
		96	signal vcc : std_logic_vector(4 downto 0);
		97	signal gnd : std_logic_vector(4 downto 0);
		98	signal resetnl : std_ulogic;
		99	signal clk2x : std_ulogic;
		100	signal lclk : std_ulogic;
		101	signal lclk2x : std_ulogic;
		102	signal clkm : std_ulogic;
		103	signal rstn : std_ulogic;
		104	signal rstraw : std_ulogic;
		105	signal pciclk : std_ulogic;
		106	signal sdclkl : std_ulogic;
		107	signal cgi : clkgen_in_type;
		108	signal cgo : clkgen_out_type;
84	--- AHB / APB	109	--- AHB / APB
85	signal apbi : apb_slv_in_type;	110	signal apbi : apb_slv_in_type;
86	signal apbo : apb_slv_out_vector := (others => apb_none);	111	signal apbo : apb_slv_out_vector := (others => apb_none);
87	signal ahbsi : ahb_slv_in_type;	112	signal ahbsi : ahb_slv_in_type;
88	signal ahbso : ahb_slv_out_vector := (others => ahbs_none);	113	signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
89	signal ahbmi : ahb_mst_in_type;	114	signal ahbmi : ahb_mst_in_type;
90	signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);	115	signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
91	-- ~~AHB~~UART	116	--UART
92	signal ahbuarti: uart_in_type;	117	signal ahbuarti : uart_in_type;
93	signal ahbuarto: uart_out_type;	118	signal ahbuarto : uart_out_type;
94	signal apbuarti: uart_in_type;	119	signal apbuarti : uart_in_type;
95	signal apbuarto: uart_out_type;	120	signal apbuarto : uart_out_type;
96	signal rxd2 : std_ulogic;	121	--MEM CTRLR
97	signal rxd1 : std_ulogic;	122	signal memi : memory_in_type;
98	signal txd1 : std_ulogic;	123	signal memo : memory_out_type;
99		124	signal wpo : wprot_out_type;
100	signal vcc : std_logic_vector(4 downto 0);	125	signal sdo : sdram_out_type;
101	signal gnd : std_logic_vector(4 downto 0);	126	--IRQ
102		127	signal irqi : irq_in_vector(0 to CFG_NCPU-1);
103	-- MEM CTRLR	128	signal irqo : irq_out_vector(0 to CFG_NCPU-1);
104	signal memi : memory_in_type;	129	--Timer
105	signal ~~memo~~ : ~~memory_out~~_type;	130	signal gpti : gptimer_in_type;
106	signal ~~sdo~~ : ~~sdram~~_out_type;	131	signal gpto : gptimer_out_type;
107	signal sdo3 : sdctrl_out_type;	132	--GPIO
108	signal ~~wpo~~ : ~~wprot_out~~_type;	133	signal gpioi : gpio_in_type;
		134	signal gpioo : gpio_out_type;
		135	--DSU
		136	signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
		137	signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
		138	signal dsui : dsu_in_type;
		139	signal dsuo : dsu_out_type;
		140	----------------------------------------------------------------------
		141	--- AJOUT TEST ------------------------Signaux----------------------
		142	----------------------------------------------------------------------
		143	-- TEST USB
		144	--signal USB_Read : std_logic;
		145	--signal USB_Write : std_logic;
109		146
110	signal clkm : std_ulogic;	147	-- MATRICE SPECTRALE
111	signal ~~resetnl~~ : std_ulogic;	148	--signal Matrix_Write : std_logic;
112	signal sdclkl : std_ulogic;	149	--signal Matrix_Read : std_logic_vector(1 downto 0);
113	signal pciclk : std_ulogic;	150	--signal Matrix_Full : std_logic_vector(1 downto 0);
114	signal lclk : std_ulogic;	151	--signal Matrix_Empty : std_logic_vector(1 downto 0);
115	signal rstn : std_ulogic;	152	--signal Matrix_Data1 : std_logic_vector(15 downto 0);
116	signal clk2x : std_ulogic;	153	--signal Matrix_Data2 : std_logic_vector(15 downto 0);
117	signal rstraw : std_logic;	154	--signal Matrix_Result : std_logic_vector(31 downto 0);
118	signal rstneg : std_logic;
119	signal lock : std_logic;
120	signal cgi : clkgen_in_type;
121	signal cgo : clkgen_out_type;
122		155
123	-- LEON3	156	---------------------------------------------------------------------
124	signal irqi : irq_in_vector(0 to CFG_NCPU-1);	157	constant IOAEN : integer := CFG_CAN;
125	signal irqo : irq_out_vector(0 to CFG_NCPU-1);	158	constant boardfreq : integer := 50000;
126	signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
127	signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
128
129	signal dsui : dsu_in_type;
130	signal dsuo : dsu_out_type;
131	signal dui : uart_in_type;
132	signal duo : uart_out_type;
133
134
135	constant boardfreq : integer := 50000; -- input frequency in KHz
136		159
137	begin	160	begin
138		161
139	----------------------------------------------------------------------	162	----------------------------------------------------------------------
140	--- Reset and Clock generation -------------------------------------	163	--- Reset and Clock generation -------------------------------------
141	----------------------------------------------------------------------	164	----------------------------------------------------------------------
142		165
143	-- vcc <= (others => '1'); gnd <= (others => '0');
144	-- cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
145	-- rstneg <= reset;
146	--
147	-- rst0 : rstgen port map (rstneg, clkm, '1', rstn, rstraw);
148	-- lock <= cgo.clklock;
149	--
150	-- clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk);
151	----
152	---- clkgen0 : clkgen -- clock generator MUL 4, DIV 5
153	---- generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
154	---- port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x);
155	--
156	--process(lclk)
157	--begin
158	-- if lclk'event and lclk = '1' then
159	-- clkm <= not clkm;
160	-- end if;
161	--end process;
162	vcc <= (others => '1'); gnd <= (others => '0');	166	vcc <= (others => '1'); gnd <= (others => '0');
163	cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;	167	cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
		168
		169	rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
164		170
165	clk_pad : inpad generic map (tech => 0) port map (clk50MHz, lclk);	171
		172	clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
166		173
167	clkgen0 : clkgen -- clock generator	174	clkgen0 : clkgen -- clock generator
168	generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,	175	generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
169	CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)	176	CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
170	port map (lclk, lclk, clkm, open, ~~open~~, ~~open~~, ~~open~~, cgi, cgo);	177	port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
171		178
172	resetn_pad : inpad generic map (tech => padtech) port map (reset, resetnl);	179	ramclk <= clkm;
173	rst0 : rstgen -- reset generator	180	process(lclk2x)
174	port map (resetnl, clkm, cgo.clklock, rstn, rstraw);	181	begin
175	--led(5) <= cgo.clklock;	182	if lclk2x'event and lclk2x = '1' then
176		183	lclk <= not lclk;
177		184	end if;
178	--------------------------------------	185	end process;
179	--- CLK_DIVIDER ----------------------
180	--------------------------------------
181	clk_divider0 : Clk_divider
182	generic map (OSC_freqHz => 50000000, TargetFreq_Hz => 5)
183	Port map( clkm, rstn, led(1));
184
185	-------------------------------
186	--- AHB CONTROLLER ------------
187	-------------------------------
188	ahb0 : ahbctrl -- AHB arbiter/multiplexer
189	generic map (defmast => 0, --AHB_UART default master
190	split => CFG_SPLIT,
191	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
192	nahbm => 3,
193	nahbs => 2)
194	port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
195
196
197	-------------------------------
198	--- MEMORY CONTROLLER ---------
199	-------------------------------
200	memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
201	port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
202
203
204	bdr : for i in 0 to 3 generate
205	data_pad : iopadv generic map (tech => padtech, width => 8)
206	port map (data(31-i8 downto 24-i8), memo.data(31-i8 downto 24-i8),
207	memo.bdrive(i), memi.data(31-i8 downto 24-i8));
208	end generate;
209
210
211
212	addr_pad : outpadv generic map (width => 19, tech => padtech)
213	port map (address, memo.address(18 downto 0));
214
215
216
217	SSRAM_0:entity ssram_plugin
218	generic map (tech => padtech)
219	port map
220	(clkm,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
221		186
222	----------------------------------------------------------------------	187	----------------------------------------------------------------------
223	--- LEON3 processor ~~and DSU -----~~------------------------------------	188	--- LEON3 processor / DSU / IRQ ------------------------------------
224	----------------------------------------------------------------------	189	----------------------------------------------------------------------
225		190
226	l3 : if CFG_LEON3 = 1 generate	191	l3 : if CFG_LEON3 = 1 generate
@@ -252,43 +217,110 port map
252	nodsu : if CFG_DSU = 0 generate	217	nodsu : if CFG_DSU = 0 generate
253	ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';	218	ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
254	end generate;	219	end generate;
255	nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;	220
		221	irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
		222	irqctrl0 : irqmp -- interrupt controller
		223	generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
		224	port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
		225	end generate;
		226	irq3 : if CFG_IRQ3_ENABLE = 0 generate
		227	x : for i in 0 to CFG_NCPU-1 generate
		228	irqi(i).irl <= "0000";
		229	end generate;
		230	apbo(2) <= apb_none;
		231	end generate;
		232
		233	----------------------------------------------------------------------
		234	--- Memory controllers ---------------------------------------------
		235	----------------------------------------------------------------------
		236
		237	memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
		238	port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
		239
		240	memi.brdyn <= '1'; memi.bexcn <= '1';
		241	memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
		242
		243	bdr : for i in 0 to 3 generate
		244	data_pad : iopadv generic map (tech => padtech, width => 8)
		245	port map (data(31-i8 downto 24-i8), memo.data(31-i8 downto 24-i8),
		246	memo.bdrive(i), memi.data(31-i8 downto 24-i8));
		247	end generate;
256		248
257		249
258	-------------------------------	250	addr_pad : outpadv generic map (width => 19, tech => padtech)
259	--- AHBUART -------------------	251	port map (address, memo.address(20 downto 2));
260	-------------------------------	252
261	dcom0 : ahbuart -- AMBA AHB Serial Debug Interface	253
262	generic map (hindex => 1, pindex => 2, paddr => 2)	254	SSRAM_0:entity ssram_plugin
263	port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(2), ahbmi, ahbmo(1));	255	generic map (tech => padtech)
264	dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, rxd2);	256	port map
265	dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);	257	(clkm,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
266	ahbuarti.rxd <= rxd2;	258
		259	----------------------------------------------------------------------
		260	--- AHB CONTROLLER -------------------------------------------------
		261	----------------------------------------------------------------------
		262
		263	ahb0 : ahbctrl -- AHB arbiter/multiplexer
		264	generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
		265	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
		266	ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
		267	port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
267		268
268	----------------------------------------------------------------------	269	----------------------------------------------------------------------
269	--- APB Bridge and various periherals --------------------------------	270	--- AHB UART -------------------------------------------------------
270	----------------------------------------------------------------------	271	----------------------------------------------------------------------
271	apb0 : apbctrl -- AHB/APB bridge	272	dcomgen : if CFG_AHB_UART = 1 generate
272	generic map (hindex => 3, haddr => CFG_APBADDR)	273	dcom0: ahbuart -- Debug UART
273	port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo);	274	generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
		275	port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
		276	dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
		277	dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
		278	-- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
		279	end generate;
		280	nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
		281
		282	----------------------------------------------------------------------
		283	--- APB Bridge -----------------------------------------------------
		284	----------------------------------------------------------------------
274		285
275	uart1 : APB_UART	286	apb0 : apbctrl -- AHB/APB bridge
276	generic map(	287	generic map (hindex => 1, haddr => CFG_APBADDR)
277	pindex => 1,	288	port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
278	paddr => 1)	289
279	port map(	290	----------------------------------------------------------------------
280	clk => clkm, --! Horloge du composant	291	--- GPT Timer ------------------------------------------------------
281	rst => rstn, --! Reset general du composant	292	----------------------------------------------------------------------
282	apbi => apbi, --! Registre de gestion des entr�es du bus	293
283	apbo => apbo(1), --! Registre de gestion des sorties du bus	294	gpt : if CFG_GPT_ENABLE /= 0 generate
284	TXD => utxd1, --! Transmission s�rie, c�t� composant	295	timer0 : gptimer -- timer unit
285	RXD => urxd1 --! Reception s�rie, c�t� composant	296	generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
286	);	297	sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
		298	nbits => CFG_GPT_TW)
		299	port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
		300	gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
		301	-- led(4) <= gpto.wdog;
		302	end generate;
		303	notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
287		304
288		305
289	----------------------------------	306	----------------------------------------------------------------------
290	--- LED --------------------------	307	--- APB UART -------------------------------------------------------
291	----------------------------------	308	----------------------------------------------------------------------
292	led(0) <= not rxd1;	309
		310	ua1 : if CFG_UART1_ENABLE /= 0 generate
		311	uart1 : apbuart -- UART 1
		312	generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
		313	fifosize => CFG_UART1_FIFO)
		314	port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
		315	apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
		316	apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
		317	led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
		318	end generate;
		319	noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
		320
		321	---------------------------------------------------------------------
		322	--- AJOUT TEST -------------------------------------IPs------------
		323	---------------------------------------------------------------------
		324
293		325
294	end Behavioral; No newline at end of file	326	end Behavioral;

designs/LFR-142200-DM-MINIAMBA/leon3mp.vhd +176 -84

@@ -17,55 +17,78
17	-- Additional Comments:	17	-- Additional Comments:
18	--	18	--
19	----------------------------------------------------------------------------------	19	----------------------------------------------------------------------------------
20	library ~~IEEE~~;	20	library ieee;
21	use IEEE.STD_LOGIC_1164.ALL;	21	use ieee.std_logic_1164.all;
22	library grlib;	22	library grlib;
23	use grlib.amba.all;	23	use grlib.amba.all;
24	use work.config.all;	24	use grlib.stdlib.all;
		25	library techmap;
		26	use techmap.gencomp.all;
25	library gaisler;	27	library gaisler;
		28	use gaisler.memctrl.all;
		29	use gaisler.leon3.all;
26	use gaisler.uart.all;	30	use gaisler.uart.all;
27	use gaisler.misc.all;	31	use gaisler.misc.all;
28	use gaisler.leon3.all;	32	library esa;
29	library techmap;	33	use esa.memoryctrl.all;
30	use techmap.gencomp.all;	34	use work.config.all;
31	use techmap.allclkgen.all;
32	library lpp;	35	library lpp;
33	use lpp.general_purpose.all;	36	use lpp.lpp_amba.all;
34	use lpp.lpp_uart.all;	37	use lpp.lpp_uart.all;
		38	use lpp.lpp_memory.all;
		39	use lpp.general_purpose.all;
35		40
36	entity ~~top~~ is	41	entity miniamba is
37	generic (	42	generic (
38	fabtech : integer := CFG_FABTECH;	43	fabtech : integer := CFG_FABTECH;
39	memtech : integer := CFG_MEMTECH;	44	memtech : integer := CFG_MEMTECH;
40	padtech : integer := CFG_PADTECH;	45	padtech : integer := CFG_PADTECH;
41	clktech : integer := CFG_CLKTECH;	46	clktech : integer := CFG_CLKTECH;
42	disas : integer := CFG_DISAS; -- Enable disassembly to console	47	disas : integer := CFG_DISAS; -- Enable disassembly to console
43	dbguart : integer := CFG_DUART; -- Print UART on console	48	dbguart : integer := CFG_DUART; -- Print UART on console
44	pclow : integer := CFG_PCLOW);	49	pclow : integer := CFG_PCLOW);
45	Port ( clk50MHz : in STD_LOGIC;	50	Port (
		51	clk50MHz : in STD_LOGIC;
46	reset : in STD_LOGIC;	52	reset : in STD_LOGIC;
47	led : out std_logic_vector(1 downto 0);	53	led : out std_logic_vector(1 downto 0);
48	--	54	ahbrxd : in std_ulogic;
49	ahbrxd : in std_ulogic;
50	ahbtxd : out std_ulogic;	55	ahbtxd : out std_ulogic;
51	urxd1 : in std_ulogic;	56	urxd1 : in std_ulogic;
52	utxd1 : out std_ulogic	57	utxd1 : out std_ulogic;
53	);	58	data : inout std_logic_vector(31 downto 0);
54	end top;	59	address : out std_logic_vector(18 downto 0);
		60	nBWa : out std_logic;
		61	nBWb : out std_logic;
		62	nBWc : out std_logic;
		63	nBWd : out std_logic;
		64	nBWE : out std_logic;
		65	nADSC : out std_logic;
		66	nADSP : out std_logic;
		67	nADV : out std_logic;
		68	nGW : out std_logic;
		69	nCE1 : out std_logic;
		70	CE2 : out std_logic;
		71	nCE3 : out std_logic;
		72	nOE : out std_logic;
		73	MODE : out std_logic;
		74	SSRAM_CLK : out std_logic;
		75	ZZ : out std_logic
		76	);
		77	end miniamba;
55		78
56	architecture Behavioral of ~~top~~ is	79	architecture Behavioral of miniamba is
57		80
58	--- AHB / APB	81	--- AHB / APB
59	signal apbi : apb_slv_in_type;	82	signal apbi : apb_slv_in_type;
60	signal apbo : apb_slv_out_vector := (others => apb_none);	83	signal apbo : apb_slv_out_vector := (others => apb_none);
61	signal ahbsi : ahb_slv_in_type;	84	signal ahbsi : ahb_slv_in_type;
62	signal ahbso : ahb_slv_out_vector := (others => ahbs_none);	85	signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
63	signal ahbmi : ahb_mst_in_type;	86	signal ahbmi : ahb_mst_in_type;
64	signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);	87	signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
65	-- AHBUART	88	-- AHBUART
66	signal ahbuarti: uart_in_type;	89	signal ahbuarti: uart_in_type;
67	signal ahbuarto: uart_out_type;	90	signal ahbuarto: uart_out_type;
68	signal apbuarti: uart_in_type;	91	signal apbuarti: uart_in_type;
69	signal apbuarto: uart_out_type;	92	signal apbuarto: uart_out_type;
70	signal rxd2 : std_ulogic;	93	signal rxd2 : std_ulogic;
71	signal rxd1 : std_ulogic;	94	signal rxd1 : std_ulogic;
@@ -73,85 +96,155 signal txd1 : std_ulogic;
73		96
74	signal vcc : std_logic_vector(4 downto 0);	97	signal vcc : std_logic_vector(4 downto 0);
75	signal gnd : std_logic_vector(4 downto 0);	98	signal gnd : std_logic_vector(4 downto 0);
76	--signal LED_rotary : std_logic_vector(7 downto 0);	99
		100	-- MEM CTRLR
		101	signal memi : memory_in_type;
		102	signal memo : memory_out_type;
		103	signal sdo : sdram_out_type;
		104	signal sdo3 : sdctrl_out_type;
		105	signal wpo : wprot_out_type;
77		106
78	signal clkm : std_ulogic;	107	signal clkm : std_ulogic;
		108	signal resetnl : std_ulogic;
		109	signal sdclkl : std_ulogic;
		110	signal pciclk : std_ulogic;
79	signal lclk : std_ulogic;	111	signal lclk : std_ulogic;
80	signal rstn : std_ulogic;	112	signal rstn : std_ulogic;
81	signal clk2x : std_ulogic;	113	signal clk2x : std_ulogic;
82	signal rstraw : std_logic;	114	signal rstraw : std_logic;
83	signal rstneg : std_logic;	115	signal rstneg : std_logic;
84	signal lock : std_logic;	116	signal lock : std_logic;
85	signal cgi : clkgen_in_type;	117	signal cgi : clkgen_in_type;
86	signal cgo : clkgen_out_type;	118	signal cgo : clkgen_out_type;
87		119
88	constant BOARD_FREQ : integer := 50000; -- input frequency in KHz	120	-- LEON3
		121	signal irqi : irq_in_vector(0 to CFG_NCPU-1);
		122	signal irqo : irq_out_vector(0 to CFG_NCPU-1);
		123	signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
		124	signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
		125
		126	signal dsui : dsu_in_type;
		127	signal dsuo : dsu_out_type;
		128	signal dui : uart_in_type;
		129	signal duo : uart_out_type;
		130
		131
		132	constant boardfreq : integer := 50000; -- input frequency in KHz
89		133
90	begin	134	begin
91		135
92	----------------------------------------------------------------------	136	----------------------------------------------------------------------
93	--- Reset and Clock generation -------------------------------------	137	--- Reset and Clock generation -------------------------------------
94	----------------------------------------------------------------------	138	----------------------------------------------------------------------
95		139
96	vcc <= (others => '1'); gnd <= (others => '0');	140	-- vcc <= (others => '1'); gnd <= (others => '0');
97	cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;	141	-- cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
98	rstneg <= reset;	142	-- rstneg <= reset;
99		143	--
100	~~rst0~~ : ~~rstgen~~ ~~port~~ ~~map~~ (~~rstneg~~, ~~clkm~~, ~~lock~~, ~~rstn~~, ~~rstraw~~);	144	-- rst0 : rstgen port map (rstneg, clkm, '1', rstn, rstraw);
101	lock <= cgo.clklock;	145	-- lock <= cgo.clklock;
102		146	--
103	clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk);	147	-- clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk);
104		148	----
105	~~clkgen0~~ : ~~clkgen~~ ~~-- clock generator MUL 4, DIV 5~~	149	---- clkgen0 : clkgen -- clock generator MUL 4, DIV 5
106	generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)	150	---- generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
107	port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x);	151	---- port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x);
		152	--
		153	--process(lclk)
		154	--begin
		155	-- if lclk'event and lclk = '1' then
		156	-- clkm <= not clkm;
		157	-- end if;
		158	--end process;
		159	vcc <= (others => '1'); gnd <= (others => '0');
		160	cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
		161
		162	clk_pad : inpad generic map (tech => 0) port map (clk50MHz, lclk);
		163
		164	clkgen0 : clkgen -- clock generator
		165	generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
		166	CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
		167	port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo);
		168
		169	resetn_pad : inpad generic map (tech => padtech) port map (reset, resetnl);
		170	rst0 : rstgen -- reset generator
		171	port map (resetnl, clkm, cgo.clklock, rstn, rstraw);
		172	--led(5) <= cgo.clklock;
		173
108		174
109	--------------------------------------	175	--------------------------------------
110	--- CLK_DIVIDER ----------------------	176	--- CLK_DIVIDER ----------------------
111	--------------------------------------	177	--------------------------------------
112	clk_divider0 : Clk_divider	178	clk_divider0 : Clk_divider
113	generic map (OSC_freqHz => 50000000, TargetFreq_Hz => 5)	179	generic map (OSC_freqHz => 50000000, TargetFreq_Hz => 5)
114	Port map( clkm, rstn, led(1));	180	Port map( clkm, rstn, led(1));
115		181
116	-------------------------------	182	-------------------------------
117	--- AHB CONTROLLER ------------	183	--- AHB CONTROLLER ------------
118	-------------------------------	184	-------------------------------
119	ahb0 : ahbctrl -- AHB arbiter/multiplexer	185	ahb0 : ahbctrl -- AHB arbiter/multiplexer
120	generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,	186	generic map (defmast => 0, --AHB_UART default master
121	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,	187	split => CFG_SPLIT,
122	nahbm => CFG_NCPU+CFG_AHB_UART,	188	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
123	nahbs => 2)	189	nahbm => 3,
		190	nahbs => 2)
124	port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);	191	port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
125		192
		193
		194	-------------------------------
		195	--- MEMORY CONTROLLER ---------
		196	-------------------------------
		197	memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
		198	port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
		199
		200
		201	bdr : for i in 0 to 3 generate
		202	data_pad : iopadv generic map (tech => padtech, width => 8)
		203	port map (data(31-i8 downto 24-i8), memo.data(31-i8 downto 24-i8),
		204	memo.bdrive(i), memi.data(31-i8 downto 24-i8));
		205	end generate;
		206
		207
		208
		209	addr_pad : outpadv generic map (width => 19, tech => padtech)
		210	port map (address, memo.address(18 downto 0));
		211
		212
		213
		214	SSRAM_0:entity ssram_plugin
		215	generic map (tech => padtech)
		216	port map
		217	(clkm,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
		218
126	-------------------------------	219	-------------------------------
127	--- AHBUART -------------------	220	--- AHBUART -------------------
128	-------------------------------	221	-------------------------------
129	dcom0 : ahbuart -- AMBA AHB Serial Debug Interface	222	dcom0 : ahbuart -- AMBA AHB Serial Debug Interface
130	generic map (hindex => ~~CFG_NCPU~~, pindex => 4, paddr => 7)	223	generic map (hindex => 1, pindex => 2, paddr => 2)
131	port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(~~CFG_NCPU~~));	224	port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(2), ahbmi, ahbmo(1));
132	dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, rxd2);	225	dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, rxd2);
133	dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);	226	dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
134	ahbuarti.rxd <= rxd2;	227	ahbuarti.rxd <= rxd2;
135		228
136	----------------------------------------------------------------------	229	----------------------------------------------------------------------
137	--- APB Bridge and various periherals --------------------------------	230	--- APB Bridge and various periherals --------------------------------
138	----------------------------------------------------------------------	231	----------------------------------------------------------------------
139	apb0 : apbctrl -- AHB/APB bridge	232	apb0 : apbctrl -- AHB/APB bridge
140	generic map (hindex => 1, haddr => CFG_APBADDR,~~nslaves~~ => 1)	233	generic map (hindex => 3, haddr => CFG_APBADDR)
141	port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);	234	port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo);
142		235
143	uart1 : APB_UART	236	uart1 : APB_UART
144	generic map(	237	generic map(
145	pindex => 0,	238	pindex => 1,
146	paddr => 0)	239	paddr => 1)
147	port map(	240	port map(
148	clk => clkm, --! Horloge du composant	241	clk => clkm, --! Horloge du composant
149	rst => rstn, --! Reset general du composant	242	rst => rstn, --! Reset general du composant
150	apbi => apbi, --! Registre de gestion des entr�es du bus	243	apbi => apbi, --! Registre de gestion des entr�es du bus
151	apbo => apbo(0), --! Registre de gestion des sorties du bus	244	apbo => apbo(1), --! Registre de gestion des sorties du bus
152	TXD => utxd1, --! Transmission s�rie, c�t� composant	245	TXD => utxd1, --! Transmission s�rie, c�t� composant
153	RXD => urxd1 --! Reception s�rie, c�t� composant	246	RXD => urxd1 --! Reception s�rie, c�t� composant
154	);	247	);
155		248
156		249
157	----------------------------------	250	----------------------------------
@@ -159,5 +252,4 uart1 : APB_UART
159	----------------------------------	252	----------------------------------
160	led(0) <= not rxd1;	253	led(0) <= not rxd1;
161		254
162	end Behavioral;	255	end Behavioral; No newline at end of file
163

designs/LFR-142200-DM-MINIAMBA/top_libero.prj.convert.8.6.bak +243 -10

@@ -14,6 +14,7 CURREV=1
14	ENDLIST	14	ENDLIST
15	LIST LIBRARIES	15	LIST LIBRARIES
16	grlib	16	grlib
		17	dw02
17	synplify	18	synplify
18	techmap	19	techmap
19	spw	20	spw
@@ -32,6 +33,10 LIST LIBRARIES_grlib
32	ALIAS=grlib	33	ALIAS=grlib
33	COMPILE_OPTION=COMPILE	34	COMPILE_OPTION=COMPILE
34	ENDLIST	35	ENDLIST
		36	LIST LIBRARIES_dw02
		37	ALIAS=dw02
		38	COMPILE_OPTION=COMPILE
		39	ENDLIST
35	LIST LIBRARIES_synplify	40	LIST LIBRARIES_synplify
36	ALIAS=synplify	41	ALIAS=synplify
37	COMPILE_OPTION=COMPILE	42	COMPILE_OPTION=COMPILE
@@ -165,6 +170,10 VALUE "<project>/../../lib/grlib/amba/am
165	STATE="utd"	170	STATE="utd"
166	LIBRARY="grlib"	171	LIBRARY="grlib"
167	ENDFILE	172	ENDFILE
		173	VALUE "<project>/../../lib/tech/dw02/comp/DW02_components.vhd,hdl"
		174	STATE="utd"
		175	LIBRARY="dw02"
		176	ENDFILE
168	VALUE "<project>/../../lib/synplify/sim/synplify.vhd,hdl"	177	VALUE "<project>/../../lib/synplify/sim/synplify.vhd,hdl"
169	STATE="utd"	178	STATE="utd"
170	LIBRARY="synplify"	179	LIBRARY="synplify"
@@ -185,6 +194,10 VALUE "<project>/../../lib/techmap/infer
185	STATE="utd"	194	STATE="utd"
186	LIBRARY="techmap"	195	LIBRARY="techmap"
187	ENDFILE	196	ENDFILE
		197	VALUE "<project>/../../lib/techmap/inferred/tap_inferred.vhd,hdl"
		198	STATE="utd"
		199	LIBRARY="techmap"
		200	ENDFILE
188	VALUE "<project>/../../lib/techmap/inferred/ddr_inferred.vhd,hdl"	201	VALUE "<project>/../../lib/techmap/inferred/ddr_inferred.vhd,hdl"
189	STATE="utd"	202	STATE="utd"
190	LIBRARY="techmap"	203	LIBRARY="techmap"
@@ -197,6 +210,62 VALUE "<project>/../../lib/techmap/infer
197	STATE="utd"	210	STATE="utd"
198	LIBRARY="techmap"	211	LIBRARY="techmap"
199	ENDFILE	212	ENDFILE
		213	VALUE "<project>/../../lib/techmap/dw02/mul_dw_gen.vhd,hdl"
		214	STATE="utd"
		215	LIBRARY="techmap"
		216	ENDFILE
		217	VALUE "<project>/../../lib/techmap/proasic3/a3pacomp.vhd,hdl"
		218	STATE="utd"
		219	LIBRARY="techmap"
		220	ENDFILE
		221	VALUE "<project>/../../lib/techmap/proasic3/memory_apa3.vhd,hdl"
		222	STATE="utd"
		223	LIBRARY="techmap"
		224	ENDFILE
		225	VALUE "<project>/../../lib/techmap/proasic3/buffer_apa3.vhd,hdl"
		226	STATE="utd"
		227	LIBRARY="techmap"
		228	ENDFILE
		229	VALUE "<project>/../../lib/techmap/proasic3/pads_apa3.vhd,hdl"
		230	STATE="utd"
		231	LIBRARY="techmap"
		232	ENDFILE
		233	VALUE "<project>/../../lib/techmap/proasic3/clkgen_proasic3.vhd,hdl"
		234	STATE="utd"
		235	LIBRARY="techmap"
		236	ENDFILE
		237	VALUE "<project>/../../lib/techmap/proasic3/ddr_proasic3.vhd,hdl"
		238	STATE="utd"
		239	LIBRARY="techmap"
		240	ENDFILE
		241	VALUE "<project>/../../lib/techmap/proasic3/tap_proasic3.vhd,hdl"
		242	STATE="utd"
		243	LIBRARY="techmap"
		244	ENDFILE
		245	VALUE "<project>/../../lib/techmap/proasic3/grspwc_proasic3.vhd,hdl"
		246	STATE="utd"
		247	LIBRARY="techmap"
		248	ENDFILE
		249	VALUE "<project>/../../lib/techmap/proasic3/leon3ft_proasic3.vhd,hdl"
		250	STATE="utd"
		251	LIBRARY="techmap"
		252	ENDFILE
		253	VALUE "<project>/../../lib/techmap/proasic3/leon3ft_proasic3_8_4_v8.vhd,hdl"
		254	STATE="utd"
		255	LIBRARY="techmap"
		256	ENDFILE
		257	VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3.vhd,hdl"
		258	STATE="utd"
		259	LIBRARY="techmap"
		260	ENDFILE
		261	VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap0.vhd,hdl"
		262	STATE="utd"
		263	LIBRARY="techmap"
		264	ENDFILE
		265	VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap1.vhd,hdl"
		266	STATE="utd"
		267	LIBRARY="techmap"
		268	ENDFILE
200	VALUE "<project>/../../lib/techmap/maps/allclkgen.vhd,hdl"	269	VALUE "<project>/../../lib/techmap/maps/allclkgen.vhd,hdl"
201	STATE="utd"	270	STATE="utd"
202	LIBRARY="techmap"	271	LIBRARY="techmap"
@@ -1085,6 +1154,10 VALUE "<project>/../../lib/lpp/./dsp/lpp
1085	STATE="utd"	1154	STATE="utd"
1086	LIBRARY="lpp"	1155	LIBRARY="lpp"
1087	ENDFILE	1156	ENDFILE
		1157	VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd,hdl"
		1158	STATE="utd"
		1159	LIBRARY="lpp"
		1160	ENDFILE
1088	VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl"	1161	VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl"
1089	STATE="utd"	1162	STATE="utd"
1090	LIBRARY="lpp"	1163	LIBRARY="lpp"
@@ -1181,6 +1254,38 VALUE "<project>/../../lib/lpp/./lpp_amb
1181	STATE="utd"	1254	STATE="utd"
1182	LIBRARY="lpp"	1255	LIBRARY="lpp"
1183	ENDFILE	1256	ENDFILE
		1257	VALUE "<project>/../../lib/lpp/./lpp_AMR/APB_AMR.vhd,hdl"
		1258	STATE="utd"
		1259	LIBRARY="lpp"
		1260	ENDFILE
		1261	VALUE "<project>/../../lib/lpp/./lpp_AMR/Clock_multi.vhd,hdl"
		1262	STATE="utd"
		1263	LIBRARY="lpp"
		1264	ENDFILE
		1265	VALUE "<project>/../../lib/lpp/./lpp_AMR/Dephaseur.vhd,hdl"
		1266	STATE="utd"
		1267	LIBRARY="lpp"
		1268	ENDFILE
		1269	VALUE "<project>/../../lib/lpp/./lpp_AMR/Gene_Rz.vhd,hdl"
		1270	STATE="utd"
		1271	LIBRARY="lpp"
		1272	ENDFILE
		1273	VALUE "<project>/../../lib/lpp/./lpp_AMR/bclk_reg.vhd,hdl"
		1274	STATE="utd"
		1275	LIBRARY="lpp"
		1276	ENDFILE
		1277	VALUE "<project>/../../lib/lpp/./lpp_AMR/lpp_AMR.vhd,hdl"
		1278	STATE="utd"
		1279	LIBRARY="lpp"
		1280	ENDFILE
		1281	VALUE "<project>/../../lib/lpp/./lpp_balise/APB_Balise.vhd,hdl"
		1282	STATE="utd"
		1283	LIBRARY="lpp"
		1284	ENDFILE
		1285	VALUE "<project>/../../lib/lpp/./lpp_balise/lpp_balise.vhd,hdl"
		1286	STATE="utd"
		1287	LIBRARY="lpp"
		1288	ENDFILE
1184	VALUE "<project>/../../lib/lpp/./lpp_cna/APB_CNA.vhd,hdl"	1289	VALUE "<project>/../../lib/lpp/./lpp_cna/APB_CNA.vhd,hdl"
1185	STATE="utd"	1290	STATE="utd"
1186	LIBRARY="lpp"	1291	LIBRARY="lpp"
@@ -1209,6 +1314,54 VALUE "<project>/../../lib/lpp/./lpp_cna
1209	STATE="utd"	1314	STATE="utd"
1210	LIBRARY="lpp"	1315	LIBRARY="lpp"
1211	ENDFILE	1316	ENDFILE
		1317	VALUE "<project>/../../lib/lpp/./lpp_matrix/ALU_Driver.vhd,hdl"
		1318	STATE="utd"
		1319	LIBRARY="lpp"
		1320	ENDFILE
		1321	VALUE "<project>/../../lib/lpp/./lpp_matrix/ALU_v2.vhd,hdl"
		1322	STATE="utd"
		1323	LIBRARY="lpp"
		1324	ENDFILE
		1325	VALUE "<project>/../../lib/lpp/./lpp_matrix/APB_Matrix.vhd,hdl"
		1326	STATE="utd"
		1327	LIBRARY="lpp"
		1328	ENDFILE
		1329	VALUE "<project>/../../lib/lpp/./lpp_matrix/DriveInputs.vhd,hdl"
		1330	STATE="utd"
		1331	LIBRARY="lpp"
		1332	ENDFILE
		1333	VALUE "<project>/../../lib/lpp/./lpp_matrix/GetResult.vhd,hdl"
		1334	STATE="utd"
		1335	LIBRARY="lpp"
		1336	ENDFILE
		1337	VALUE "<project>/../../lib/lpp/./lpp_matrix/MAC_v2.vhd,hdl"
		1338	STATE="utd"
		1339	LIBRARY="lpp"
		1340	ENDFILE
		1341	VALUE "<project>/../../lib/lpp/./lpp_matrix/Matrix.vhd,hdl"
		1342	STATE="utd"
		1343	LIBRARY="lpp"
		1344	ENDFILE
		1345	VALUE "<project>/../../lib/lpp/./lpp_matrix/SelectInputs.vhd,hdl"
		1346	STATE="utd"
		1347	LIBRARY="lpp"
		1348	ENDFILE
		1349	VALUE "<project>/../../lib/lpp/./lpp_matrix/SpectralMatrix.vhd,hdl"
		1350	STATE="utd"
		1351	LIBRARY="lpp"
		1352	ENDFILE
		1353	VALUE "<project>/../../lib/lpp/./lpp_matrix/Starter.vhd,hdl"
		1354	STATE="utd"
		1355	LIBRARY="lpp"
		1356	ENDFILE
		1357	VALUE "<project>/../../lib/lpp/./lpp_matrix/TwoComplementer.vhd,hdl"
		1358	STATE="utd"
		1359	LIBRARY="lpp"
		1360	ENDFILE
		1361	VALUE "<project>/../../lib/lpp/./lpp_matrix/lpp_matrix.vhd,hdl"
		1362	STATE="utd"
		1363	LIBRARY="lpp"
		1364	ENDFILE
1212	VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl"	1365	VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl"
1213	STATE="utd"	1366	STATE="utd"
1214	LIBRARY="lpp"	1367	LIBRARY="lpp"
@@ -1237,15 +1390,11 VALUE "<project>/../../lib/lpp/./lpp_mem
1237	STATE="utd"	1390	STATE="utd"
1238	LIBRARY="lpp"	1391	LIBRARY="lpp"
1239	ENDFILE	1392	ENDFILE
1240	VALUE "<project>/../../lib/lpp/./lpp_memory/~~Top_FIFO~~.vhd,hdl"	1393	VALUE "<project>/../../lib/lpp/./lpp_memory/SSRAM_plugin.vhd,hdl"
1241	STATE="utd"	1394	STATE="utd"
1242	LIBRARY="lpp"	1395	LIBRARY="lpp"
1243	ENDFILE	1396	ENDFILE
1244	VALUE "<project>/../../lib/lpp/./lpp_memory/Top_F~~ifoRead~~.vhd,hdl"	1397	VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl"
1245	STATE="utd"
1246	LIBRARY="lpp"
1247	ENDFILE
1248	VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FifoWrite.vhd,hdl"
1249	STATE="utd"	1398	STATE="utd"
1250	LIBRARY="lpp"	1399	LIBRARY="lpp"
1251	ENDFILE	1400	ENDFILE
@@ -1273,6 +1422,14 VALUE "<project>/../../lib/lpp/./lpp_uar
1273	STATE="utd"	1422	STATE="utd"
1274	LIBRARY="lpp"	1423	LIBRARY="lpp"
1275	ENDFILE	1424	ENDFILE
		1425	VALUE "<project>/../../lib/lpp/./lpp_usb/RWbuf.vhd,hdl"
		1426	STATE="utd"
		1427	LIBRARY="lpp"
		1428	ENDFILE
		1429	VALUE "<project>/../../lib/lpp/./lpp_usb/lpp_usb.vhd,hdl"
		1430	STATE="utd"
		1431	LIBRARY="lpp"
		1432	ENDFILE
1276	VALUE "<project>/../../lib/cypress/ssram/components.vhd,hdl"	1433	VALUE "<project>/../../lib/cypress/ssram/components.vhd,hdl"
1277	STATE="utd"	1434	STATE="utd"
1278	LIBRARY="cypress"	1435	LIBRARY="cypress"
@@ -1332,6 +1489,7 VALUE "<project>/../../lib/grlib/sparc/s
1332	VALUE "<project>/../../lib/grlib/sparc/cpu_disas.vhd,hdl"	1489	VALUE "<project>/../../lib/grlib/sparc/cpu_disas.vhd,hdl"
1333	VALUE "<project>/../../lib/grlib/amba/dma2ahb_tp.vhd,hdl"	1490	VALUE "<project>/../../lib/grlib/amba/dma2ahb_tp.vhd,hdl"
1334	VALUE "<project>/../../lib/grlib/amba/amba_tp.vhd,hdl"	1491	VALUE "<project>/../../lib/grlib/amba/amba_tp.vhd,hdl"
		1492	VALUE "<project>/../../lib/tech/dw02/comp/DW02_components.vhd,hdl"
1335	VALUE "<project>/../../lib/synplify/sim/synplify.vhd,hdl"	1493	VALUE "<project>/../../lib/synplify/sim/synplify.vhd,hdl"
1336	VALUE "<project>/../../lib/synplify/sim/synattr.vhd,hdl"	1494	VALUE "<project>/../../lib/synplify/sim/synattr.vhd,hdl"
1337	VALUE "<project>/../../lib/gaisler/ambatest/ahbtbp.vhd,hdl"	1495	VALUE "<project>/../../lib/gaisler/ambatest/ahbtbp.vhd,hdl"
@@ -1395,9 +1553,24 VALUE "<project>/../../lib/grlib/amba/dm
1395	VALUE "<project>/../../lib/techmap/gencomp/gencomp.vhd,hdl"	1553	VALUE "<project>/../../lib/techmap/gencomp/gencomp.vhd,hdl"
1396	VALUE "<project>/../../lib/techmap/gencomp/netcomp.vhd,hdl"	1554	VALUE "<project>/../../lib/techmap/gencomp/netcomp.vhd,hdl"
1397	VALUE "<project>/../../lib/techmap/inferred/memory_inferred.vhd,hdl"	1555	VALUE "<project>/../../lib/techmap/inferred/memory_inferred.vhd,hdl"
		1556	VALUE "<project>/../../lib/techmap/inferred/tap_inferred.vhd,hdl"
1398	VALUE "<project>/../../lib/techmap/inferred/ddr_inferred.vhd,hdl"	1557	VALUE "<project>/../../lib/techmap/inferred/ddr_inferred.vhd,hdl"
1399	VALUE "<project>/../../lib/techmap/inferred/mul_inferred.vhd,hdl"	1558	VALUE "<project>/../../lib/techmap/inferred/mul_inferred.vhd,hdl"
1400	VALUE "<project>/../../lib/techmap/inferred/ddr_phy_inferred.vhd,hdl"	1559	VALUE "<project>/../../lib/techmap/inferred/ddr_phy_inferred.vhd,hdl"
		1560	VALUE "<project>/../../lib/techmap/dw02/mul_dw_gen.vhd,hdl"
		1561	VALUE "<project>/../../lib/techmap/proasic3/a3pacomp.vhd,hdl"
		1562	VALUE "<project>/../../lib/techmap/proasic3/memory_apa3.vhd,hdl"
		1563	VALUE "<project>/../../lib/techmap/proasic3/buffer_apa3.vhd,hdl"
		1564	VALUE "<project>/../../lib/techmap/proasic3/pads_apa3.vhd,hdl"
		1565	VALUE "<project>/../../lib/techmap/proasic3/clkgen_proasic3.vhd,hdl"
		1566	VALUE "<project>/../../lib/techmap/proasic3/ddr_proasic3.vhd,hdl"
		1567	VALUE "<project>/../../lib/techmap/proasic3/tap_proasic3.vhd,hdl"
		1568	VALUE "<project>/../../lib/techmap/proasic3/grspwc_proasic3.vhd,hdl"
		1569	VALUE "<project>/../../lib/techmap/proasic3/leon3ft_proasic3.vhd,hdl"
		1570	VALUE "<project>/../../lib/techmap/proasic3/leon3ft_proasic3_8_4_v8.vhd,hdl"
		1571	VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3.vhd,hdl"
		1572	VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap0.vhd,hdl"
		1573	VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap1.vhd,hdl"
1401	VALUE "<project>/../../lib/techmap/maps/allclkgen.vhd,hdl"	1574	VALUE "<project>/../../lib/techmap/maps/allclkgen.vhd,hdl"
1402	VALUE "<project>/../../lib/techmap/maps/allddr.vhd,hdl"	1575	VALUE "<project>/../../lib/techmap/maps/allddr.vhd,hdl"
1403	VALUE "<project>/../../lib/techmap/maps/allmem.vhd,hdl"	1576	VALUE "<project>/../../lib/techmap/maps/allmem.vhd,hdl"
@@ -1595,6 +1768,7 VALUE "<project>/../../lib/lpp/./dsp/iir
1595	VALUE "<project>/../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd,hdl"	1768	VALUE "<project>/../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd,hdl"
1596	VALUE "<project>/../../lib/lpp/./dsp/iir_filter/iir_filter.vhd,hdl"	1769	VALUE "<project>/../../lib/lpp/./dsp/iir_filter/iir_filter.vhd,hdl"
1597	VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl"	1770	VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl"
		1771	VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd,hdl"
1598	VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl"	1772	VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl"
1599	VALUE "<project>/../../lib/lpp/./general_purpose/ADDRcntr.vhd,hdl"	1773	VALUE "<project>/../../lib/lpp/./general_purpose/ADDRcntr.vhd,hdl"
1600	VALUE "<project>/../../lib/lpp/./general_purpose/ALU.vhd,hdl"	1774	VALUE "<project>/../../lib/lpp/./general_purpose/ALU.vhd,hdl"
@@ -1619,6 +1793,14 VALUE "<project>/../../lib/lpp/./lpp_amb
1619	VALUE "<project>/../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl"	1793	VALUE "<project>/../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl"
1620	VALUE "<project>/../../lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl"	1794	VALUE "<project>/../../lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl"
1621	VALUE "<project>/../../lib/lpp/./lpp_amba/lpp_amba.vhd,hdl"	1795	VALUE "<project>/../../lib/lpp/./lpp_amba/lpp_amba.vhd,hdl"
		1796	VALUE "<project>/../../lib/lpp/./lpp_AMR/APB_AMR.vhd,hdl"
		1797	VALUE "<project>/../../lib/lpp/./lpp_AMR/Clock_multi.vhd,hdl"
		1798	VALUE "<project>/../../lib/lpp/./lpp_AMR/Dephaseur.vhd,hdl"
		1799	VALUE "<project>/../../lib/lpp/./lpp_AMR/Gene_Rz.vhd,hdl"
		1800	VALUE "<project>/../../lib/lpp/./lpp_AMR/bclk_reg.vhd,hdl"
		1801	VALUE "<project>/../../lib/lpp/./lpp_AMR/lpp_AMR.vhd,hdl"
		1802	VALUE "<project>/../../lib/lpp/./lpp_balise/APB_Balise.vhd,hdl"
		1803	VALUE "<project>/../../lib/lpp/./lpp_balise/lpp_balise.vhd,hdl"
1622	VALUE "<project>/../../lib/lpp/./lpp_cna/APB_CNA.vhd,hdl"	1804	VALUE "<project>/../../lib/lpp/./lpp_cna/APB_CNA.vhd,hdl"
1623	VALUE "<project>/../../lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl"	1805	VALUE "<project>/../../lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl"
1624	VALUE "<project>/../../lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl"	1806	VALUE "<project>/../../lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl"
@@ -1626,6 +1808,18 VALUE "<project>/../../lib/lpp/./lpp_cna
1626	VALUE "<project>/../../lib/lpp/./lpp_cna/Serialize.vhd,hdl"	1808	VALUE "<project>/../../lib/lpp/./lpp_cna/Serialize.vhd,hdl"
1627	VALUE "<project>/../../lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl"	1809	VALUE "<project>/../../lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl"
1628	VALUE "<project>/../../lib/lpp/./lpp_cna/lpp_cna.vhd,hdl"	1810	VALUE "<project>/../../lib/lpp/./lpp_cna/lpp_cna.vhd,hdl"
		1811	VALUE "<project>/../../lib/lpp/./lpp_matrix/ALU_Driver.vhd,hdl"
		1812	VALUE "<project>/../../lib/lpp/./lpp_matrix/ALU_v2.vhd,hdl"
		1813	VALUE "<project>/../../lib/lpp/./lpp_matrix/APB_Matrix.vhd,hdl"
		1814	VALUE "<project>/../../lib/lpp/./lpp_matrix/DriveInputs.vhd,hdl"
		1815	VALUE "<project>/../../lib/lpp/./lpp_matrix/GetResult.vhd,hdl"
		1816	VALUE "<project>/../../lib/lpp/./lpp_matrix/MAC_v2.vhd,hdl"
		1817	VALUE "<project>/../../lib/lpp/./lpp_matrix/Matrix.vhd,hdl"
		1818	VALUE "<project>/../../lib/lpp/./lpp_matrix/SelectInputs.vhd,hdl"
		1819	VALUE "<project>/../../lib/lpp/./lpp_matrix/SpectralMatrix.vhd,hdl"
		1820	VALUE "<project>/../../lib/lpp/./lpp_matrix/Starter.vhd,hdl"
		1821	VALUE "<project>/../../lib/lpp/./lpp_matrix/TwoComplementer.vhd,hdl"
		1822	VALUE "<project>/../../lib/lpp/./lpp_matrix/lpp_matrix.vhd,hdl"
1629	VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl"	1823	VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl"
1630	VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl"	1824	VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl"
1631	VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl"	1825	VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl"
@@ -1633,15 +1827,16 VALUE "<project>/../../lib/lpp/./lpp_mem
1633	VALUE "<project>/../../lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl"	1827	VALUE "<project>/../../lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl"
1634	VALUE "<project>/../../lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl"	1828	VALUE "<project>/../../lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl"
1635	VALUE "<project>/../../lib/lpp/./lpp_memory/Link_Reg.vhd,hdl"	1829	VALUE "<project>/../../lib/lpp/./lpp_memory/Link_Reg.vhd,hdl"
		1830	VALUE "<project>/../../lib/lpp/./lpp_memory/SSRAM_plugin.vhd,hdl"
1636	VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl"	1831	VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl"
1637	VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FifoRead.vhd,hdl"
1638	VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FifoWrite.vhd,hdl"
1639	VALUE "<project>/../../lib/lpp/./lpp_memory/lpp_memory.vhd,hdl"	1832	VALUE "<project>/../../lib/lpp/./lpp_memory/lpp_memory.vhd,hdl"
1640	VALUE "<project>/../../lib/lpp/./lpp_uart/APB_UART.vhd,hdl"	1833	VALUE "<project>/../../lib/lpp/./lpp_uart/APB_UART.vhd,hdl"
1641	VALUE "<project>/../../lib/lpp/./lpp_uart/BaudGen.vhd,hdl"	1834	VALUE "<project>/../../lib/lpp/./lpp_uart/BaudGen.vhd,hdl"
1642	VALUE "<project>/../../lib/lpp/./lpp_uart/Shift_REG.vhd,hdl"	1835	VALUE "<project>/../../lib/lpp/./lpp_uart/Shift_REG.vhd,hdl"
1643	VALUE "<project>/../../lib/lpp/./lpp_uart/UART.vhd,hdl"	1836	VALUE "<project>/../../lib/lpp/./lpp_uart/UART.vhd,hdl"
1644	VALUE "<project>/../../lib/lpp/./lpp_uart/lpp_uart.vhd,hdl"	1837	VALUE "<project>/../../lib/lpp/./lpp_uart/lpp_uart.vhd,hdl"
		1838	VALUE "<project>/../../lib/lpp/./lpp_usb/RWbuf.vhd,hdl"
		1839	VALUE "<project>/../../lib/lpp/./lpp_usb/lpp_usb.vhd,hdl"
1645	VALUE "<project>/config.vhd,hdl"	1840	VALUE "<project>/config.vhd,hdl"
1646	VALUE "<project>/ahbrom.vhd,hdl"	1841	VALUE "<project>/ahbrom.vhd,hdl"
1647	VALUE "<project>/leon3mp.vhd,hdl"	1842	VALUE "<project>/leon3mp.vhd,hdl"
@@ -1670,14 +1865,30 VALUE "<project>/../../lib/grlib/amba/dm
1670	VALUE "<project>/../../lib/grlib/amba/dma2ahb.vhd,hdl"	1865	VALUE "<project>/../../lib/grlib/amba/dma2ahb.vhd,hdl"
1671	VALUE "<project>/../../lib/grlib/amba/dma2ahb_tp.vhd,hdl"	1866	VALUE "<project>/../../lib/grlib/amba/dma2ahb_tp.vhd,hdl"
1672	VALUE "<project>/../../lib/grlib/amba/amba_tp.vhd,hdl"	1867	VALUE "<project>/../../lib/grlib/amba/amba_tp.vhd,hdl"
		1868	VALUE "<project>/../../lib/tech/dw02/comp/DW02_components.vhd,hdl"
1673	VALUE "<project>/../../lib/synplify/sim/synplify.vhd,hdl"	1869	VALUE "<project>/../../lib/synplify/sim/synplify.vhd,hdl"
1674	VALUE "<project>/../../lib/synplify/sim/synattr.vhd,hdl"	1870	VALUE "<project>/../../lib/synplify/sim/synattr.vhd,hdl"
1675	VALUE "<project>/../../lib/techmap/gencomp/gencomp.vhd,hdl"	1871	VALUE "<project>/../../lib/techmap/gencomp/gencomp.vhd,hdl"
1676	VALUE "<project>/../../lib/techmap/gencomp/netcomp.vhd,hdl"	1872	VALUE "<project>/../../lib/techmap/gencomp/netcomp.vhd,hdl"
1677	VALUE "<project>/../../lib/techmap/inferred/memory_inferred.vhd,hdl"	1873	VALUE "<project>/../../lib/techmap/inferred/memory_inferred.vhd,hdl"
		1874	VALUE "<project>/../../lib/techmap/inferred/tap_inferred.vhd,hdl"
1678	VALUE "<project>/../../lib/techmap/inferred/ddr_inferred.vhd,hdl"	1875	VALUE "<project>/../../lib/techmap/inferred/ddr_inferred.vhd,hdl"
1679	VALUE "<project>/../../lib/techmap/inferred/mul_inferred.vhd,hdl"	1876	VALUE "<project>/../../lib/techmap/inferred/mul_inferred.vhd,hdl"
1680	VALUE "<project>/../../lib/techmap/inferred/ddr_phy_inferred.vhd,hdl"	1877	VALUE "<project>/../../lib/techmap/inferred/ddr_phy_inferred.vhd,hdl"
		1878	VALUE "<project>/../../lib/techmap/dw02/mul_dw_gen.vhd,hdl"
		1879	VALUE "<project>/../../lib/techmap/proasic3/a3pacomp.vhd,hdl"
		1880	VALUE "<project>/../../lib/techmap/proasic3/memory_apa3.vhd,hdl"
		1881	VALUE "<project>/../../lib/techmap/proasic3/buffer_apa3.vhd,hdl"
		1882	VALUE "<project>/../../lib/techmap/proasic3/pads_apa3.vhd,hdl"
		1883	VALUE "<project>/../../lib/techmap/proasic3/clkgen_proasic3.vhd,hdl"
		1884	VALUE "<project>/../../lib/techmap/proasic3/ddr_proasic3.vhd,hdl"
		1885	VALUE "<project>/../../lib/techmap/proasic3/tap_proasic3.vhd,hdl"
		1886	VALUE "<project>/../../lib/techmap/proasic3/grspwc_proasic3.vhd,hdl"
		1887	VALUE "<project>/../../lib/techmap/proasic3/leon3ft_proasic3.vhd,hdl"
		1888	VALUE "<project>/../../lib/techmap/proasic3/leon3ft_proasic3_8_4_v8.vhd,hdl"
		1889	VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3.vhd,hdl"
		1890	VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap0.vhd,hdl"
		1891	VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap1.vhd,hdl"
1681	VALUE "<project>/../../lib/techmap/maps/allclkgen.vhd,hdl"	1892	VALUE "<project>/../../lib/techmap/maps/allclkgen.vhd,hdl"
1682	VALUE "<project>/../../lib/techmap/maps/allddr.vhd,hdl"	1893	VALUE "<project>/../../lib/techmap/maps/allddr.vhd,hdl"
1683	VALUE "<project>/../../lib/techmap/maps/allmem.vhd,hdl"	1894	VALUE "<project>/../../lib/techmap/maps/allmem.vhd,hdl"
@@ -1900,6 +2111,7 VALUE "<project>/../../lib/lpp/./dsp/iir
1900	VALUE "<project>/../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd,hdl"	2111	VALUE "<project>/../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd,hdl"
1901	VALUE "<project>/../../lib/lpp/./dsp/iir_filter/iir_filter.vhd,hdl"	2112	VALUE "<project>/../../lib/lpp/./dsp/iir_filter/iir_filter.vhd,hdl"
1902	VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl"	2113	VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl"
		2114	VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd,hdl"
1903	VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl"	2115	VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl"
1904	VALUE "<project>/../../lib/lpp/./general_purpose/ADDRcntr.vhd,hdl"	2116	VALUE "<project>/../../lib/lpp/./general_purpose/ADDRcntr.vhd,hdl"
1905	VALUE "<project>/../../lib/lpp/./general_purpose/ALU.vhd,hdl"	2117	VALUE "<project>/../../lib/lpp/./general_purpose/ALU.vhd,hdl"
@@ -1924,6 +2136,14 VALUE "<project>/../../lib/lpp/./lpp_amb
1924	VALUE "<project>/../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl"	2136	VALUE "<project>/../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl"
1925	VALUE "<project>/../../lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl"	2137	VALUE "<project>/../../lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl"
1926	VALUE "<project>/../../lib/lpp/./lpp_amba/lpp_amba.vhd,hdl"	2138	VALUE "<project>/../../lib/lpp/./lpp_amba/lpp_amba.vhd,hdl"
		2139	VALUE "<project>/../../lib/lpp/./lpp_AMR/APB_AMR.vhd,hdl"
		2140	VALUE "<project>/../../lib/lpp/./lpp_AMR/Clock_multi.vhd,hdl"
		2141	VALUE "<project>/../../lib/lpp/./lpp_AMR/Dephaseur.vhd,hdl"
		2142	VALUE "<project>/../../lib/lpp/./lpp_AMR/Gene_Rz.vhd,hdl"
		2143	VALUE "<project>/../../lib/lpp/./lpp_AMR/bclk_reg.vhd,hdl"
		2144	VALUE "<project>/../../lib/lpp/./lpp_AMR/lpp_AMR.vhd,hdl"
		2145	VALUE "<project>/../../lib/lpp/./lpp_balise/APB_Balise.vhd,hdl"
		2146	VALUE "<project>/../../lib/lpp/./lpp_balise/lpp_balise.vhd,hdl"
1927	VALUE "<project>/../../lib/lpp/./lpp_cna/APB_CNA.vhd,hdl"	2147	VALUE "<project>/../../lib/lpp/./lpp_cna/APB_CNA.vhd,hdl"
1928	VALUE "<project>/../../lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl"	2148	VALUE "<project>/../../lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl"
1929	VALUE "<project>/../../lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl"	2149	VALUE "<project>/../../lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl"
@@ -1931,6 +2151,18 VALUE "<project>/../../lib/lpp/./lpp_cna
1931	VALUE "<project>/../../lib/lpp/./lpp_cna/Serialize.vhd,hdl"	2151	VALUE "<project>/../../lib/lpp/./lpp_cna/Serialize.vhd,hdl"
1932	VALUE "<project>/../../lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl"	2152	VALUE "<project>/../../lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl"
1933	VALUE "<project>/../../lib/lpp/./lpp_cna/lpp_cna.vhd,hdl"	2153	VALUE "<project>/../../lib/lpp/./lpp_cna/lpp_cna.vhd,hdl"
		2154	VALUE "<project>/../../lib/lpp/./lpp_matrix/ALU_Driver.vhd,hdl"
		2155	VALUE "<project>/../../lib/lpp/./lpp_matrix/ALU_v2.vhd,hdl"
		2156	VALUE "<project>/../../lib/lpp/./lpp_matrix/APB_Matrix.vhd,hdl"
		2157	VALUE "<project>/../../lib/lpp/./lpp_matrix/DriveInputs.vhd,hdl"
		2158	VALUE "<project>/../../lib/lpp/./lpp_matrix/GetResult.vhd,hdl"
		2159	VALUE "<project>/../../lib/lpp/./lpp_matrix/MAC_v2.vhd,hdl"
		2160	VALUE "<project>/../../lib/lpp/./lpp_matrix/Matrix.vhd,hdl"
		2161	VALUE "<project>/../../lib/lpp/./lpp_matrix/SelectInputs.vhd,hdl"
		2162	VALUE "<project>/../../lib/lpp/./lpp_matrix/SpectralMatrix.vhd,hdl"
		2163	VALUE "<project>/../../lib/lpp/./lpp_matrix/Starter.vhd,hdl"
		2164	VALUE "<project>/../../lib/lpp/./lpp_matrix/TwoComplementer.vhd,hdl"
		2165	VALUE "<project>/../../lib/lpp/./lpp_matrix/lpp_matrix.vhd,hdl"
1934	VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl"	2166	VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl"
1935	VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl"	2167	VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl"
1936	VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl"	2168	VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl"
@@ -1938,15 +2170,16 VALUE "<project>/../../lib/lpp/./lpp_mem
1938	VALUE "<project>/../../lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl"	2170	VALUE "<project>/../../lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl"
1939	VALUE "<project>/../../lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl"	2171	VALUE "<project>/../../lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl"
1940	VALUE "<project>/../../lib/lpp/./lpp_memory/Link_Reg.vhd,hdl"	2172	VALUE "<project>/../../lib/lpp/./lpp_memory/Link_Reg.vhd,hdl"
		2173	VALUE "<project>/../../lib/lpp/./lpp_memory/SSRAM_plugin.vhd,hdl"
1941	VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl"	2174	VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl"
1942	VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FifoRead.vhd,hdl"
1943	VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FifoWrite.vhd,hdl"
1944	VALUE "<project>/../../lib/lpp/./lpp_memory/lpp_memory.vhd,hdl"	2175	VALUE "<project>/../../lib/lpp/./lpp_memory/lpp_memory.vhd,hdl"
1945	VALUE "<project>/../../lib/lpp/./lpp_uart/APB_UART.vhd,hdl"	2176	VALUE "<project>/../../lib/lpp/./lpp_uart/APB_UART.vhd,hdl"
1946	VALUE "<project>/../../lib/lpp/./lpp_uart/BaudGen.vhd,hdl"	2177	VALUE "<project>/../../lib/lpp/./lpp_uart/BaudGen.vhd,hdl"
1947	VALUE "<project>/../../lib/lpp/./lpp_uart/Shift_REG.vhd,hdl"	2178	VALUE "<project>/../../lib/lpp/./lpp_uart/Shift_REG.vhd,hdl"
1948	VALUE "<project>/../../lib/lpp/./lpp_uart/UART.vhd,hdl"	2179	VALUE "<project>/../../lib/lpp/./lpp_uart/UART.vhd,hdl"
1949	VALUE "<project>/../../lib/lpp/./lpp_uart/lpp_uart.vhd,hdl"	2180	VALUE "<project>/../../lib/lpp/./lpp_uart/lpp_uart.vhd,hdl"
		2181	VALUE "<project>/../../lib/lpp/./lpp_usb/RWbuf.vhd,hdl"
		2182	VALUE "<project>/../../lib/lpp/./lpp_usb/lpp_usb.vhd,hdl"
1950	VALUE "<project>/../../lib/cypress/ssram/components.vhd,hdl"	2183	VALUE "<project>/../../lib/cypress/ssram/components.vhd,hdl"
1951	VALUE "<project>/../../lib/cypress/ssram/package_utility.vhd,hdl"	2184	VALUE "<project>/../../lib/cypress/ssram/package_utility.vhd,hdl"
1952	VALUE "<project>/../../lib/cypress/ssram/cy7c1354b.vhd,hdl"	2185	VALUE "<project>/../../lib/cypress/ssram/cy7c1354b.vhd,hdl"

lib/lpp/Doxyfile +184 -57

-            # Doxyfile 1.7.1
+            # Doxyfile 1.7.5.1
             # This file describes the settings to be used by the documentation system
             # doxygen (www.doxygen.org) for a project
             DOXYFILE_ENCODING      = UTF-8
-            # The PROJECT_NAME tag is a single word (or a sequence of words surrounded
+            # The PROJECT_NAME tag is a single word (or sequence of words) that should
-            # by quotes) that should identify the project.
+            # identify the project. Note that if you do not use Doxywizard you need
+            # to put quotes around the project name if it contains spaces.
             PROJECT_NAME           = lib-lpp
             # This could be handy for archiving the generated documentation or
             # if some version control system is used.
-            PROJECT_NUMBER         = 0.4
+            PROJECT_NUMBER         = 1.0
+            # Using the PROJECT_BRIEF tag one can provide an optional one line description
+            # for a project that appears at the top of each page and should give viewer
+            # a quick idea about the purpose of the project. Keep the description short.
+            PROJECT_BRIEF          =
+            # With the PROJECT_LOGO tag one can specify an logo or icon that is
+            # included in the documentation. The maximum height of the logo should not
+            # exceed 55 pixels and the maximum width should not exceed 200 pixels.
+            # Doxygen will copy the logo to the output directory.
+            PROJECT_LOGO           =
             # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
             # base path where the generated documentation will be put.
             # Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German,
             # Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English
             # messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian,
-            # Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak,
+            # Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak,
             # Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.
             OUTPUT_LANGUAGE        = English
             STRIP_FROM_INC_PATH    =
             # If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter
-            # (but less readable) file names. This can be useful is your file systems
+            # (but less readable) file names. This can be useful if your file system
             # doesn't support long names like on DOS, Mac, or CD-ROM.
             SHORT_NAMES            = NO
             # to include (a tag file for) the STL sources as input, then you should
             # set this tag to YES in order to let doxygen match functions declarations and
             # definitions whose arguments contain STL classes (e.g. func(std::string); v.s.
-            # func(std::string) {}). This also make the inheritance and collaboration
+            # func(std::string) {}). This also makes the inheritance and collaboration
             # diagrams that involve STL classes more complete and accurate.
             BUILTIN_STL_SUPPORT    = NO
             # For Microsoft's IDL there are propget and propput attributes to indicate getter
             # and setter methods for a property. Setting this option to YES (the default)
-            # will make doxygen to replace the get and set methods by a property in the
+            # will make doxygen replace the get and set methods by a property in the
             # documentation. This will only work if the methods are indeed getting or
             # setting a simple type. If this is not the case, or you want to show the
             # methods anyway, you should set this option to NO.
             SUBGROUPING            = YES
+            # When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and
+            # unions are shown inside the group in which they are included (e.g. using
+            # @ingroup) instead of on a separate page (for HTML and Man pages) or
+            # section (for LaTeX and RTF).
+            INLINE_GROUPED_CLASSES = NO
+            # When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and
+            # unions with only public data fields will be shown inline in the documentation
+            # of the scope in which they are defined (i.e. file, namespace, or group
+            # documentation), provided this scope is documented. If set to NO (the default),
+            # structs, classes, and unions are shown on a separate page (for HTML and Man
+            # pages) or section (for LaTeX and RTF).
+            INLINE_SIMPLE_STRUCTS  = NO
             # When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum
             # is documented as struct, union, or enum with the name of the typedef. So
             # typedef struct TypeS {} TypeT, will appear in the documentation as a struct
             # For small to medium size projects (<1000 input files) the default value is
             # probably good enough. For larger projects a too small cache size can cause
             # doxygen to be busy swapping symbols to and from disk most of the time
-            # causing a significant performance penality.
+            # causing a significant performance penalty.
             # If the system has enough physical memory increasing the cache will improve the
             # performance by keeping more symbols in memory. Note that the value works on
-            # a logarithmic scale so increasing the size by one will rougly double the
+            # a logarithmic scale so increasing the size by one will roughly double the
             # memory usage. The cache size is given by this formula:
             # 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0,
             # corresponding to a cache size of 2^16 = 65536 symbols
             # extracted and appear in the documentation as a namespace called
             # 'anonymous_namespace{file}', where file will be replaced with the base
             # name of the file that contains the anonymous namespace. By default
-            # anonymous namespace are hidden.
+            # anonymous namespaces are hidden.
             EXTRACT_ANON_NSPACES   = NO
             SORT_BY_SCOPE_NAME     = NO
+            # If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to
+            # do proper type resolution of all parameters of a function it will reject a
+            # match between the prototype and the implementation of a member function even
+            # if there is only one candidate or it is obvious which candidate to choose
+            # by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen
+            # will still accept a match between prototype and implementation in such cases.
+            STRICT_PROTO_MATCHING  = NO
             # The GENERATE_TODOLIST tag can be used to enable (YES) or
             # disable (NO) the todo list. This list is created by putting \todo
             # commands in the documentation.
             ENABLED_SECTIONS       =
             # The MAX_INITIALIZER_LINES tag determines the maximum number of lines
-            # the initial value of a variable or define consists of for it to appear in
+            # the initial value of a variable or macro consists of for it to appear in
             # the documentation. If the initializer consists of more lines than specified
             # here it will be hidden. Use a value of 0 to hide initializers completely.
-            # The appearance of the initializer of individual variables and defines in the
+            # The appearance of the initializer of individual variables and macros in the
             # documentation can be controlled using \showinitializer or \hideinitializer
             # command in the documentation regardless of this setting.
             LAYOUT_FILE            =
+            # The CITE_BIB_FILES tag can be used to specify one or more bib files
+            # containing the references data. This must be a list of .bib files. The
+            # .bib extension is automatically appended if omitted. Using this command
+            # requires the bibtex tool to be installed. See also
+            # http://en.wikipedia.org/wiki/BibTeX for more info. For LaTeX the style
+            # of the bibliography can be controlled using LATEX_BIB_STYLE.
+            CITE_BIB_FILES         =
             #---------------------------------------------------------------------------
             # configuration options related to warning and progress messages
             #---------------------------------------------------------------------------
             WARN_IF_DOC_ERROR      = YES
-            # This WARN_NO_PARAMDOC option can be abled to get warnings for
+            # The WARN_NO_PARAMDOC option can be enabled to get warnings for
             # functions that are documented, but have no documentation for their parameters
             # or return value. If set to NO (the default) doxygen will only warn about
             # wrong or incomplete parameter documentation, but not about the absence of
             # FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
             # and *.h) to filter out the source-files in the directories. If left
             # blank the following patterns are tested:
-            # *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx
+            # *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh
-            # *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90
+            # *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py
+            # *.f90 *.f *.for *.vhd *.vhdl
             FILE_PATTERNS          = *.c \
                                      *.cc \
             # The EXCLUDE tag can be used to specify files and/or directories that should
             # excluded from the INPUT source files. This way you can easily exclude a
             # subdirectory from a directory tree whose root is specified with the INPUT tag.
+            # Note that relative paths are relative to directory from which doxygen is run.
             EXCLUDE                =
             # The EXCLUDE_SYMLINKS tag can be used select whether or not files or
-            # directories that are symbolic links (a Unix filesystem feature) are excluded
+            # directories that are symbolic links (a Unix file system feature) are excluded
             # from the input.
             EXCLUDE_SYMLINKS       = NO
             # basis.  Doxygen will compare the file name with each pattern and apply the
             # filter if there is a match.  The filters are a list of the form:
             # pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further
-            # info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER
+            # info on how filters are used. If FILTER_PATTERNS is empty or if
-            # is applied to all files.
+            # non of the patterns match the file name, INPUT_FILTER is applied.
             FILTER_PATTERNS        =
             FILTER_SOURCE_FILES    = NO
+            # The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file
+            # pattern. A pattern will override the setting for FILTER_PATTERN (if any)
+            # and it is also possible to disable source filtering for a specific pattern
+            # using *.ext= (so without naming a filter). This option only has effect when
+            # FILTER_SOURCE_FILES is enabled.
+            FILTER_SOURCE_PATTERNS =
             #---------------------------------------------------------------------------
             # configuration options related to source browsing
             #---------------------------------------------------------------------------
             # Note: To get rid of all source code in the generated output, make sure also
             # VERBATIM_HEADERS is set to NO.
-            SOURCE_BROWSER         = YES
+            SOURCE_BROWSER         = NO
             # Setting the INLINE_SOURCES tag to YES will include the body
             # of functions and classes directly in the documentation.
             # The HTML_HEADER tag can be used to specify a personal HTML header for
             # each generated HTML page. If it is left blank doxygen will generate a
-            # standard header.
+            # standard header. Note that when using a custom header you are responsible
+            # for the proper inclusion of any scripts and style sheets that doxygen
+            # needs, which is dependent on the configuration options used.
+            # It is adviced to generate a default header using "doxygen -w html
+            # header.html footer.html stylesheet.css YourConfigFile" and then modify
+            # that header. Note that the header is subject to change so you typically
+            # have to redo this when upgrading to a newer version of doxygen or when
+            # changing the value of configuration settings such as GENERATE_TREEVIEW!
-            HTML_HEADER            = ../../doc/ressources/Header
+            HTML_HEADER            =
             # The HTML_FOOTER tag can be used to specify a personal HTML footer for
             # each generated HTML page. If it is left blank doxygen will generate a
             # standard footer.
-            HTML_FOOTER            = ../../doc/ressources/Footer
+            HTML_FOOTER            =
             # The HTML_STYLESHEET tag can be used to specify a user-defined cascading
             # style sheet that is used by each HTML page. It can be used to
             # the style sheet file to the HTML output directory, so don't put your own
             # stylesheet in the HTML output directory as well, or it will be erased!
-            HTML_STYLESHEET        = ../../doc/ressources/doxygen.css
+            HTML_STYLESHEET        =
+            # The HTML_EXTRA_FILES tag can be used to specify one or more extra images or
+            # other source files which should be copied to the HTML output directory. Note
+            # that these files will be copied to the base HTML output directory. Use the
+            # $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these
+            # files. In the HTML_STYLESHEET file, use the file name only. Also note that
+            # the files will be copied as-is; there are no commands or markers available.
+            HTML_EXTRA_FILES       =
             # The HTML_COLORSTYLE_HUE tag controls the color of the HTML output.
             # Doxygen will adjust the colors in the stylesheet and background images
             DISABLE_INDEX          = NO
-            # This tag can be used to set the number of enum values (range [1..20])
+            # The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values
-            # that doxygen will group on one line in the generated HTML documentation.
+            # (range [0,1..20]) that doxygen will group on one line in the generated HTML
+            # documentation. Note that a value of 0 will completely suppress the enum
+            # values from appearing in the overview section.
             ENUM_VALUES_PER_LINE   = 4
             FORMULA_TRANSPARENT    = YES
+            # Enable the USE_MATHJAX option to render LaTeX formulas using MathJax
+            # (see http://www.mathjax.org) which uses client side Javascript for the
+            # rendering instead of using prerendered bitmaps. Use this if you do not
+            # have LaTeX installed or if you want to formulas look prettier in the HTML
+            # output. When enabled you also need to install MathJax separately and
+            # configure the path to it using the MATHJAX_RELPATH option.
+            USE_MATHJAX            = NO
+            # When MathJax is enabled you need to specify the location relative to the
+            # HTML output directory using the MATHJAX_RELPATH option. The destination
+            # directory should contain the MathJax.js script. For instance, if the mathjax
+            # directory is located at the same level as the HTML output directory, then
+            # MATHJAX_RELPATH should be ../mathjax. The default value points to the
+            # mathjax.org site, so you can quickly see the result without installing
+            # MathJax, but it is strongly recommended to install a local copy of MathJax
+            # before deployment.
+            MATHJAX_RELPATH        = http://www.mathjax.org/mathjax
+            # The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension
+            # names that should be enabled during MathJax rendering.
+            MATHJAX_EXTENSIONS     =
             # When the SEARCHENGINE tag is enabled doxygen will generate a search box
             # for the HTML output. The underlying search engine uses javascript
             # and DHTML and should work on any modern browser. Note that when using
             # using Javascript. Doxygen will generate the search PHP script and index
             # file to put on the web server. The advantage of the server
             # based approach is that it scales better to large projects and allows
-            # full text search. The disadvances is that it is more difficult to setup
+            # full text search. The disadvantages are that it is more difficult to setup
             # and does not have live searching capabilities.
             SERVER_BASED_SEARCH    = NO
             # LaTeX documents. This may be useful for small projects and may help to
             # save some trees in general.
-            COMPACT_LATEX          = YES
+            COMPACT_LATEX          = NO
             # The PAPER_TYPE tag can be used to set the paper type that is used
-            # by the printer. Possible values are: a4, a4wide, letter, legal and
+            # by the printer. Possible values are: a4, letter, legal and
             # executive. If left blank a4wide will be used.
-            PAPER_TYPE             = letter
+            PAPER_TYPE             = a4wide
             # The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX
             # packages that should be included in the LaTeX output.
             LATEX_HEADER           =
+            # The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for
+            # the generated latex document. The footer should contain everything after
+            # the last chapter. If it is left blank doxygen will generate a
+            # standard footer. Notice: only use this tag if you know what you are doing!
+            LATEX_FOOTER           =
             # If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated
             # is prepared for conversion to pdf (using ps2pdf). The pdf file will
             # contain links (just like the HTML output) instead of page references
             LATEX_SOURCE_CODE      = NO
+            # The LATEX_BIB_STYLE tag can be used to specify the style to use for the
+            # bibliography, e.g. plainnat, or ieeetr. The default style is "plain". See
+            # http://en.wikipedia.org/wiki/BibTeX for more info.
+            LATEX_BIB_STYLE        = plain
             #---------------------------------------------------------------------------
             # configuration options related to the RTF output
             #---------------------------------------------------------------------------
             EXPAND_ONLY_PREDEF     = NO
             # If the SEARCH_INCLUDES tag is set to YES (the default) the includes files
-            # in the INCLUDE_PATH (see below) will be search if a #include is found.
+            # pointed to by INCLUDE_PATH will be searched when a #include is found.
             SEARCH_INCLUDES        = YES
             # If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then
             # this tag can be used to specify a list of macro names that should be expanded.
             # The macro definition that is found in the sources will be used.
-            # Use the PREDEFINED tag if you want to use a different macro definition.
+            # Use the PREDEFINED tag if you want to use a different macro definition that
+            # overrules the definition found in the source code.
             EXPAND_AS_DEFINED      =
             # If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then
-            # doxygen's preprocessor will remove all function-like macros that are alone
+            # doxygen's preprocessor will remove all references to function-like macros
-            # on a line, have an all uppercase name, and do not end with a semicolon. Such
+            # that are alone on a line, have an all uppercase name, and do not end with a
-            # function macros are typically used for boiler-plate code, and will confuse
+            # semicolon, because these will confuse the parser if not removed.
-            # the parser if not removed.
             SKIP_FUNCTION_MACROS   = YES
             # If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will
             # generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base
             # or super classes. Setting the tag to NO turns the diagrams off. Note that
-            # this option is superseded by the HAVE_DOT option below. This is only a
+            # this option also works with HAVE_DOT disabled, but it is recommended to
-            # fallback. It is recommended to install and use dot, since it yields more
+            # install and use dot, since it yields more powerful graphs.
-            # powerful graphs.
-            CLASS_DIAGRAMS         = NO
+            CLASS_DIAGRAMS         = YES
             # You can define message sequence charts within doxygen comments using the \msc
             # command. Doxygen will then run the mscgen tool (see
             DOT_NUM_THREADS        = 0
-            # By default doxygen will write a font called FreeSans.ttf to the output
+            # By default doxygen will use the Helvetica font for all dot files that
-            # directory and reference it in all dot files that doxygen generates. This
+            # doxygen generates. When you want a differently looking font you can specify
-            # font does not include all possible unicode characters however, so when you need
+            # the font name using DOT_FONTNAME. You need to make sure dot is able to find
-            # these (or just want a differently looking font) you can specify the font name
+            # the font, which can be done by putting it in a standard location or by setting
-            # using DOT_FONTNAME. You need need to make sure dot is able to find the font,
+            # the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the
-            # which can be done by putting it in a standard location or by setting the
+            # directory containing the font.
-            # DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory
-            # containing the font.
             DOT_FONTNAME           = FreeSans.ttf
             DOT_FONTSIZE           = 10
-            # By default doxygen will tell dot to use the output directory to look for the
+            # By default doxygen will tell dot to use the Helvetica font.
-            # FreeSans.ttf font (which doxygen will put there itself). If you specify a
+            # If you specify a different font using DOT_FONTNAME you can use DOT_FONTPATH to
-            # different font using DOT_FONTNAME you can set the path where dot
+            # set the path where dot can find it.
-            # can find it using this tag.
             DOT_FONTPATH           =
             # collaboration diagrams in a style similar to the OMG's Unified Modeling
             # Language.
-            UML_LOOK               = YES
+            UML_LOOK               = NO
             # If set to YES, the inheritance and collaboration graphs will show the
             # relations between templates and their instances.
             CALLER_GRAPH           = NO
             # If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen
-            # will graphical hierarchy of all classes instead of a textual one.
+            # will generate a graphical hierarchy of all classes instead of a textual one.
             GRAPHICAL_HIERARCHY    = YES
             DIRECTORY_GRAPH        = YES
             # The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
-            # generated by dot. Possible values are png, jpg, or gif
+            # generated by dot. Possible values are svg, png, jpg, or gif.
-            # If left blank png will be used.
+            # If left blank png will be used. If you choose svg you need to set
+            # HTML_FILE_EXTENSION to xhtml in order to make the SVG files
+            # visible in IE 9+ (other browsers do not have this requirement).
             DOT_IMAGE_FORMAT       = png
+            # If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to
+            # enable generation of interactive SVG images that allow zooming and panning.
+            # Note that this requires a modern browser other than Internet Explorer.
+            # Tested and working are Firefox, Chrome, Safari, and Opera. For IE 9+ you
+            # need to set HTML_FILE_EXTENSION to xhtml in order to make the SVG files
+            # visible. Older versions of IE do not have SVG support.
+            INTERACTIVE_SVG        = NO
             # The tag DOT_PATH can be used to specify the path where the dot tool can be
             # found. If left blank, it is assumed the dot tool can be found in the path.
             DOTFILE_DIRS           =
+            # The MSCFILE_DIRS tag can be used to specify one or more directories that
+            # contain msc files that are included in the documentation (see the
+            # \mscfile command).
+            MSCFILE_DIRS           =
             # The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of
             # nodes that will be shown in the graph. If the number of nodes in a graph
             # becomes larger than this value, doxygen will truncate the graph, which is

lib/lpp/lpp_memory/lpp_memory.vhd +3 0

             use std.textio.all;
             library lpp;
             use lpp.lpp_amba.all;
+            library gaisler;
+            use gaisler.misc.all;
+            use gaisler.memctrl.all;
             --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on

General Comments 0

Write
Preview

You need to be logged in to leave comments. Login now

No TODOs yet

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages