diff --git a/LPP_drivers/Doxyfile b/LPP_drivers/Doxyfile --- a/LPP_drivers/Doxyfile +++ b/LPP_drivers/Doxyfile @@ -25,13 +25,13 @@ DOXYFILE_ENCODING = UTF-8 # The PROJECT_NAME tag is a single word (or a sequence of words surrounded # by quotes) that should identify the project. -PROJECT_NAME = "VHDL lib Drivers" +PROJECT_NAME = "apb lcd driver" # The PROJECT_NUMBER tag can be used to enter a project or revision number. # This could be handy for archiving the generated documentation or # if some version control system is used. -PROJECT_NUMBER = 0.4 +PROJECT_NUMBER = 0.1 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) # base path where the generated documentation will be put. @@ -339,7 +339,7 @@ EXTRACT_LOCAL_METHODS = YES # name of the file that contains the anonymous namespace. By default # anonymous namespace are hidden. -EXTRACT_ANON_NSPACES = YES +EXTRACT_ANON_NSPACES = NO # If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all # undocumented members of documented classes, files or namespaces. @@ -497,7 +497,7 @@ SHOW_USED_FILES = YES # then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy # in the documentation. The default is NO. -SHOW_DIRECTORIES = YES +SHOW_DIRECTORIES = NO # Set the SHOW_FILES tag to NO to disable the generation of the Files page. # This will remove the Files entry from the Quick Index and from the @@ -677,7 +677,7 @@ EXCLUDE_SYMBOLS = # directories that contain example code fragments that are included (see # the \include command). -EXAMPLE_PATH = Doc/ressources/examples +EXAMPLE_PATH = # If the value of the EXAMPLE_PATH tag contains directories, you can use the # EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp @@ -827,13 +827,13 @@ HTML_FILE_EXTENSION = .html # each generated HTML page. If it is left blank doxygen will generate a # standard header. -HTML_HEADER = Doc/ressources/Header +HTML_HEADER = # The HTML_FOOTER tag can be used to specify a personal HTML footer for # each generated HTML page. If it is left blank doxygen will generate a # standard footer. -HTML_FOOTER = Doc/ressources/Footer +HTML_FOOTER = # The HTML_STYLESHEET tag can be used to specify a user-defined cascading # style sheet that is used by each HTML page. It can be used to @@ -842,7 +842,7 @@ HTML_FOOTER = Doc/ressources/ # the style sheet file to the HTML output directory, so don't put your own # stylesheet in the HTML output directory as well, or it will be erased! -HTML_STYLESHEET = Doc/ressources/doxygen.css +HTML_STYLESHEET = # The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. # Doxygen will adjust the colors in the stylesheet and background images @@ -852,7 +852,7 @@ HTML_STYLESHEET = Doc/ressources/ # 180 is cyan, 240 is blue, 300 purple, and 360 is red again. # The allowed range is 0 to 359. -HTML_COLORSTYLE_HUE = 218 +HTML_COLORSTYLE_HUE = 220 # The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of # the colors in the HTML output. For a value of 0 the output will use @@ -1059,7 +1059,7 @@ ENUM_VALUES_PER_LINE = 4 # JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). # Windows users are probably better off using the HTML help feature. -GENERATE_TREEVIEW = YES +GENERATE_TREEVIEW = NO # By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, # and Class Hierarchy pages using a tree view instead of an ordered list. @@ -1491,7 +1491,7 @@ HIDE_UNDOC_RELATIONS = YES # toolkit from AT&T and Lucent Bell Labs. The other options in this section # have no effect if this option is set to NO (the default) -HAVE_DOT = YES +HAVE_DOT = NO # The DOT_NUM_THREADS specifies the number of dot invocations doxygen is # allowed to run in parallel. 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zb@^D0Q}j?o1I#9L?=v~{IRhaG-{%RWI=XsLVBo$^3>mp#(Pwamy9D79TfC@4D_z>8 z=du;Ht7!0;?{mNmD1vdZKI$c7c|^p-hhNS#w$ofH6D6893rD6kfHS{VZ%Y)tGsw*& Kv<9Xz9RI)L6{9c! diff --git a/LPP_drivers/exemples/hello/Makefile b/LPP_drivers/exemples/hello/Makefile new file mode 100644 --- /dev/null +++ b/LPP_drivers/exemples/hello/Makefile @@ -0,0 +1,44 @@ +#------------------------------------------------------------------------------ +#-- This file is a part of the LPP VHDL IP LIBRARY +#-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS +#-- +#-- This program is free software; you can redistribute it and/or modify +#-- it under the terms of the GNU General Public License as published by +#-- the Free Software Foundation; either version 3 of the License, or +#-- (at your option) any later version. +#-- +#-- This program is distributed in the hope that it will be useful, +#-- but WITHOUT ANY WARRANTY; without even the implied warranty of +#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +#-- GNU General Public License for more details. +#-- +#-- You should have received a copy of the GNU General Public License +#-- along with this program; if not, write to the Free Software +#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +#------------------------------------------------------------------------------ + +include ../../rules.mk +LIBDIR= +INCPATH = ../../includes +SCRIPTDIR=../../scripts/ +LIBS= +INPUTFILE=main.c +EXEC=hello.bin +OUTBINDIR=bin/ + + +.PHONY:bin + +all:bin + @echo $(EXEC)" file created" + +clean: + rm -f *.{o,a} + + + +help:ruleshelp + @echo " all : makes an executable file called "$(EXEC) + @echo " in "$(OUTBINDIR) + @echo " clean : removes temporary files" + diff --git a/LPP_drivers/exemples/hello/main.c b/LPP_drivers/exemples/hello/main.c new file mode 100644 --- /dev/null +++ b/LPP_drivers/exemples/hello/main.c @@ -0,0 +1,26 @@ +/*------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------------*/ +#include "stdio.h" + + +int main() +{ + printf("hello World\n"); + return 0; +} diff --git a/LPP_drivers/scripts/load.txt b/LPP_drivers/scripts/load.txt --- a/LPP_drivers/scripts/load.txt +++ b/LPP_drivers/scripts/load.txt @@ -1,1 +1,1 @@ -load bin/BenchFIFO.bin +load bin/hello.bin diff --git a/Makefile b/Makefile --- a/Makefile +++ b/Makefile @@ -61,6 +61,7 @@ Patched-dist: Patch-GRLIB doc: + mkdir -p doc/html/ cp doc/ressources/*.jpg doc/html/ cp doc/ressources/doxygen.css doc/html/ make -C lib/lpp doc diff --git a/designs/LFR-142200-DM-LEON3-BASE/config.vhd b/designs/LFR-142200-DM-LEON3-BASE/config.vhd --- a/designs/LFR-142200-DM-LEON3-BASE/config.vhd +++ b/designs/LFR-142200-DM-LEON3-BASE/config.vhd @@ -29,9 +29,9 @@ package config is -- Clock generator constant CFG_CLKTECH : integer := inferred; - constant CFG_CLKMUL : integer := (45); - constant CFG_CLKDIV : integer := (9); - constant CFG_OCLKDIV : integer := (8); + constant CFG_CLKMUL : integer := (5); + constant CFG_CLKDIV : integer := (10); + constant CFG_OCLKDIV : integer := (1); constant CFG_PCIDLL : integer := 0; constant CFG_PCISYSCLK: integer := 0; constant CFG_CLK_NOFB : integer := 0; @@ -177,4 +177,4 @@ package config is constant CFG_DUART : integer := 0; -end; \ No newline at end of file +end; diff --git a/designs/LFR-142200-DM-LEON3-BASE/leon3mp.vhd b/designs/LFR-142200-DM-LEON3-BASE/leon3mp.vhd --- a/designs/LFR-142200-DM-LEON3-BASE/leon3mp.vhd +++ b/designs/LFR-142200-DM-LEON3-BASE/leon3mp.vhd @@ -1,22 +1,23 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:12 03/29/2011 --- Design Name: --- Module Name: top - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: +----------------------------------------------------------------------------- +-- LEON3 Demonstration design +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. -- --- Dependencies: +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. -- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ + + library ieee; use ieee.std_logic_1164.all; library grlib; @@ -34,193 +35,157 @@ use esa.memoryctrl.all; use work.config.all; library lpp; use lpp.lpp_amba.all; -use lpp.lpp_uart.all; use lpp.lpp_memory.all; -use lpp.general_purpose.all; +--use lpp.lpp_uart.all; +--use lpp.lpp_matrix.all; +--use lpp.lpp_usb.all; + +entity leon3mp is + generic ( + fabtech : integer := CFG_FABTECH; + memtech : integer := CFG_MEMTECH; + padtech : integer := CFG_PADTECH; + clktech : integer := CFG_CLKTECH; + disas : integer := CFG_DISAS; -- Enable disassembly to console + dbguart : integer := CFG_DUART; -- Print UART on console + pclow : integer := CFG_PCLOW + ); + port ( + clk50MHz : in std_ulogic; + reset : in std_ulogic; + ramclk : out std_logic; + + ahbrxd : in std_ulogic; -- DSU rx data + ahbtxd : out std_ulogic; -- DSU tx data + dsubre : in std_ulogic; + dsuact : out std_ulogic; + urxd1 : in std_ulogic; -- UART1 rx data + utxd1 : out std_ulogic; -- UART1 tx data + errorn : out std_ulogic; + + address : out std_logic_vector(18 downto 0); + data : inout std_logic_vector(31 downto 0); -entity miniamba is - generic ( - fabtech : integer := CFG_FABTECH; - memtech : integer := CFG_MEMTECH; - padtech : integer := CFG_PADTECH; - clktech : integer := CFG_CLKTECH; - disas : integer := CFG_DISAS; -- Enable disassembly to console - dbguart : integer := CFG_DUART; -- Print UART on console - pclow : integer := CFG_PCLOW); - Port ( - clk50MHz : in STD_LOGIC; - reset : in STD_LOGIC; - led : out std_logic_vector(1 downto 0); - errorn : out std_ulogic; - dsubre : in std_ulogic; - dsuact : out std_ulogic; - ahbrxd : in std_ulogic; - ahbtxd : out std_ulogic; - urxd1 : in std_ulogic; - utxd1 : out std_ulogic; - data : inout std_logic_vector(31 downto 0); - address : out std_logic_vector(18 downto 0); - nBWa : out std_logic; - nBWb : out std_logic; - nBWc : out std_logic; - nBWd : out std_logic; - nBWE : out std_logic; - nADSC : out std_logic; - nADSP : out std_logic; - nADV : out std_logic; - nGW : out std_logic; - nCE1 : out std_logic; - CE2 : out std_logic; - nCE3 : out std_logic; - nOE : out std_logic; - MODE : out std_logic; - SSRAM_CLK : out std_logic; - ZZ : out std_logic - ); -end miniamba; + nBWa : out std_logic; + nBWb : out std_logic; + nBWc : out std_logic; + nBWd : out std_logic; + nBWE : out std_logic; + nADSC : out std_logic; + nADSP : out std_logic; + nADV : out std_logic; + nGW : out std_logic; + nCE1 : out std_logic; + CE2 : out std_logic; + nCE3 : out std_logic; + nOE : out std_logic; + MODE : out std_logic; + SSRAM_CLK : out std_logic; + ZZ : out std_logic; + led : out std_logic_vector(1 downto 0) + ); +end; -architecture Behavioral of miniamba is +architecture Behavioral of leon3mp is + +constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ + CFG_GRETH+CFG_AHB_JTAG; +constant maxahbm : integer := maxahbmsp; +--Clk & Rst géné +signal vcc : std_logic_vector(4 downto 0); +signal gnd : std_logic_vector(4 downto 0); +signal resetnl : std_ulogic; +signal clk2x : std_ulogic; +signal lclk : std_ulogic; +signal lclk2x : std_ulogic; +signal clkm : std_ulogic; +signal rstn : std_ulogic; +signal rstraw : std_ulogic; +signal pciclk : std_ulogic; +signal sdclkl : std_ulogic; +signal cgi : clkgen_in_type; +signal cgo : clkgen_out_type; --- AHB / APB -signal apbi : apb_slv_in_type; -signal apbo : apb_slv_out_vector := (others => apb_none); -signal ahbsi : ahb_slv_in_type; -signal ahbso : ahb_slv_out_vector := (others => ahbs_none); -signal ahbmi : ahb_mst_in_type; -signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); --- AHBUART -signal ahbuarti: uart_in_type; -signal ahbuarto: uart_out_type; -signal apbuarti: uart_in_type; -signal apbuarto: uart_out_type; -signal rxd2 : std_ulogic; -signal rxd1 : std_ulogic; -signal txd1 : std_ulogic; - -signal vcc : std_logic_vector(4 downto 0); -signal gnd : std_logic_vector(4 downto 0); - --- MEM CTRLR -signal memi : memory_in_type; -signal memo : memory_out_type; -signal sdo : sdram_out_type; -signal sdo3 : sdctrl_out_type; -signal wpo : wprot_out_type; +signal apbi : apb_slv_in_type; +signal apbo : apb_slv_out_vector := (others => apb_none); +signal ahbsi : ahb_slv_in_type; +signal ahbso : ahb_slv_out_vector := (others => ahbs_none); +signal ahbmi : ahb_mst_in_type; +signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); +--UART +signal ahbuarti : uart_in_type; +signal ahbuarto : uart_out_type; +signal apbuarti : uart_in_type; +signal apbuarto : uart_out_type; +--MEM CTRLR +signal memi : memory_in_type; +signal memo : memory_out_type; +signal wpo : wprot_out_type; +signal sdo : sdram_out_type; +--IRQ +signal irqi : irq_in_vector(0 to CFG_NCPU-1); +signal irqo : irq_out_vector(0 to CFG_NCPU-1); +--Timer +signal gpti : gptimer_in_type; +signal gpto : gptimer_out_type; +--GPIO +signal gpioi : gpio_in_type; +signal gpioo : gpio_out_type; +--DSU +signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); +signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); +signal dsui : dsu_in_type; +signal dsuo : dsu_out_type; +---------------------------------------------------------------------- +--- AJOUT TEST ------------------------Signaux---------------------- +---------------------------------------------------------------------- +-- TEST USB +--signal USB_Read : std_logic; +--signal USB_Write : std_logic; -signal clkm : std_ulogic; -signal resetnl : std_ulogic; -signal sdclkl : std_ulogic; -signal pciclk : std_ulogic; -signal lclk : std_ulogic; -signal rstn : std_ulogic; -signal clk2x : std_ulogic; -signal rstraw : std_logic; -signal rstneg : std_logic; -signal lock : std_logic; -signal cgi : clkgen_in_type; -signal cgo : clkgen_out_type; +-- MATRICE SPECTRALE +--signal Matrix_Write : std_logic; +--signal Matrix_Read : std_logic_vector(1 downto 0); +--signal Matrix_Full : std_logic_vector(1 downto 0); +--signal Matrix_Empty : std_logic_vector(1 downto 0); +--signal Matrix_Data1 : std_logic_vector(15 downto 0); +--signal Matrix_Data2 : std_logic_vector(15 downto 0); +--signal Matrix_Result : std_logic_vector(31 downto 0); --- LEON3 -signal irqi : irq_in_vector(0 to CFG_NCPU-1); -signal irqo : irq_out_vector(0 to CFG_NCPU-1); -signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); -signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); - -signal dsui : dsu_in_type; -signal dsuo : dsu_out_type; -signal dui : uart_in_type; -signal duo : uart_out_type; - - -constant boardfreq : integer := 50000; -- input frequency in KHz +--------------------------------------------------------------------- +constant IOAEN : integer := CFG_CAN; +constant boardfreq : integer := 50000; begin ---------------------------------------------------------------------- --- Reset and Clock generation ------------------------------------- ---------------------------------------------------------------------- - --- vcc <= (others => '1'); gnd <= (others => '0'); --- cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; --- rstneg <= reset; --- --- rst0 : rstgen port map (rstneg, clkm, '1', rstn, rstraw); --- lock <= cgo.clklock; --- --- clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk); ----- ----- clkgen0 : clkgen -- clock generator MUL 4, DIV 5 ----- generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0) ----- port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x); --- ---process(lclk) ---begin --- if lclk'event and lclk = '1' then --- clkm <= not clkm; --- end if; ---end process; + vcc <= (others => '1'); gnd <= (others => '0'); cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; + + rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); - clk_pad : inpad generic map (tech => 0) port map (clk50MHz, lclk); + + clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); clkgen0 : clkgen -- clock generator generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo); - - resetn_pad : inpad generic map (tech => padtech) port map (reset, resetnl); - rst0 : rstgen -- reset generator - port map (resetnl, clkm, cgo.clklock, rstn, rstraw); - --led(5) <= cgo.clklock; - - --------------------------------------- ---- CLK_DIVIDER ---------------------- --------------------------------------- -clk_divider0 : Clk_divider - generic map (OSC_freqHz => 50000000, TargetFreq_Hz => 5) - Port map( clkm, rstn, led(1)); - -------------------------------- ---- AHB CONTROLLER ------------ -------------------------------- -ahb0 : ahbctrl -- AHB arbiter/multiplexer - generic map (defmast => 0, --AHB_UART default master - split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1, - nahbm => 3, - nahbs => 2) - port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - - -------------------------------- ---- MEMORY CONTROLLER --------- -------------------------------- -memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) - port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); - - -bdr : for i in 0 to 3 generate - data_pad : iopadv generic map (tech => padtech, width => 8) - port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), -memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); -end generate; - - - -addr_pad : outpadv generic map (width => 19, tech => padtech) - port map (address, memo.address(18 downto 0)); - - - -SSRAM_0:entity ssram_plugin -generic map (tech => padtech) -port map -(clkm,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); + port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); + + ramclk <= clkm; +process(lclk2x) +begin + if lclk2x'event and lclk2x = '1' then + lclk <= not lclk; + end if; +end process; ---------------------------------------------------------------------- ---- LEON3 processor and DSU ----------------------------------------- +--- LEON3 processor / DSU / IRQ ------------------------------------ ---------------------------------------------------------------------- l3 : if CFG_LEON3 = 1 generate @@ -252,43 +217,110 @@ port map nodsu : if CFG_DSU = 0 generate ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; end generate; - nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; + + irqctrl : if CFG_IRQ3_ENABLE /= 0 generate + irqctrl0 : irqmp -- interrupt controller + generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) + port map (rstn, clkm, apbi, apbo(2), irqo, irqi); + end generate; + irq3 : if CFG_IRQ3_ENABLE = 0 generate + x : for i in 0 to CFG_NCPU-1 generate + irqi(i).irl <= "0000"; + end generate; + apbo(2) <= apb_none; + end generate; + +---------------------------------------------------------------------- +--- Memory controllers --------------------------------------------- +---------------------------------------------------------------------- + +memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) + port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); + +memi.brdyn <= '1'; memi.bexcn <= '1'; +memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; + +bdr : for i in 0 to 3 generate + data_pad : iopadv generic map (tech => padtech, width => 8) + port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), +memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); +end generate; -------------------------------- ---- AHBUART ------------------- -------------------------------- -dcom0 : ahbuart -- AMBA AHB Serial Debug Interface - generic map (hindex => 1, pindex => 2, paddr => 2) - port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(2), ahbmi, ahbmo(1)); -dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, rxd2); -dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); -ahbuarti.rxd <= rxd2; +addr_pad : outpadv generic map (width => 19, tech => padtech) + port map (address, memo.address(20 downto 2)); + + +SSRAM_0:entity ssram_plugin +generic map (tech => padtech) +port map +(clkm,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); + +---------------------------------------------------------------------- +--- AHB CONTROLLER ------------------------------------------------- +---------------------------------------------------------------------- + + ahb0 : ahbctrl -- AHB arbiter/multiplexer + generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, + rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, + ioen => IOAEN, nahbm => maxahbm, nahbs => 8) + port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- ---- APB Bridge and various periherals -------------------------------- +--- AHB UART ------------------------------------------------------- ---------------------------------------------------------------------- -apb0 : apbctrl -- AHB/APB bridge - generic map (hindex => 3, haddr => CFG_APBADDR) - port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo); + dcomgen : if CFG_AHB_UART = 1 generate + dcom0: ahbuart -- Debug UART + generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) + port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); + dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); + dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); +-- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; + end generate; + nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; + +---------------------------------------------------------------------- +--- APB Bridge ----------------------------------------------------- +---------------------------------------------------------------------- -uart1 : APB_UART - generic map( - pindex => 1, - paddr => 1) - port map( - clk => clkm, --! Horloge du composant - rst => rstn, --! Reset general du composant - apbi => apbi, --! Registre de gestion des entrées du bus - apbo => apbo(1), --! Registre de gestion des sorties du bus - TXD => utxd1, --! Transmission série, côté composant - RXD => urxd1 --! Reception série, côté composant - ); + apb0 : apbctrl -- AHB/APB bridge + generic map (hindex => 1, haddr => CFG_APBADDR) + port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); + +---------------------------------------------------------------------- +--- GPT Timer ------------------------------------------------------ +---------------------------------------------------------------------- + + gpt : if CFG_GPT_ENABLE /= 0 generate + timer0 : gptimer -- timer unit + generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, + sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, + nbits => CFG_GPT_TW) + port map (rstn, clkm, apbi, apbo(3), gpti, gpto); + gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; +-- led(4) <= gpto.wdog; + end generate; + notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; ----------------------------------- ---- LED -------------------------- ----------------------------------- -led(0) <= not rxd1; +---------------------------------------------------------------------- +--- APB UART ------------------------------------------------------- +---------------------------------------------------------------------- + + ua1 : if CFG_UART1_ENABLE /= 0 generate + uart1 : apbuart -- UART 1 + generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, + fifosize => CFG_UART1_FIFO) + port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); + apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; + apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; + led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; + end generate; + noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; + +--------------------------------------------------------------------- +--- AJOUT TEST -------------------------------------IPs------------ +--------------------------------------------------------------------- + end Behavioral; \ No newline at end of file diff --git a/designs/LFR-142200-DM-MINIAMBA/leon3mp.vhd b/designs/LFR-142200-DM-MINIAMBA/leon3mp.vhd --- a/designs/LFR-142200-DM-MINIAMBA/leon3mp.vhd +++ b/designs/LFR-142200-DM-MINIAMBA/leon3mp.vhd @@ -17,55 +17,78 @@ -- Additional Comments: -- ---------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library grlib; +library ieee; +use ieee.std_logic_1164.all; +library grlib; use grlib.amba.all; -use work.config.all; +use grlib.stdlib.all; +library techmap; +use techmap.gencomp.all; library gaisler; +use gaisler.memctrl.all; +use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; -use gaisler.leon3.all; -library techmap; -use techmap.gencomp.all; -use techmap.allclkgen.all; +library esa; +use esa.memoryctrl.all; +use work.config.all; library lpp; -use lpp.general_purpose.all; +use lpp.lpp_amba.all; use lpp.lpp_uart.all; +use lpp.lpp_memory.all; +use lpp.general_purpose.all; -entity top is +entity miniamba is generic ( fabtech : integer := CFG_FABTECH; - memtech : integer := CFG_MEMTECH; - padtech : integer := CFG_PADTECH; - clktech : integer := CFG_CLKTECH; - disas : integer := CFG_DISAS; -- Enable disassembly to console - dbguart : integer := CFG_DUART; -- Print UART on console + memtech : integer := CFG_MEMTECH; + padtech : integer := CFG_PADTECH; + clktech : integer := CFG_CLKTECH; + disas : integer := CFG_DISAS; -- Enable disassembly to console + dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW); - Port ( clk50MHz : in STD_LOGIC; + Port ( + clk50MHz : in STD_LOGIC; reset : in STD_LOGIC; led : out std_logic_vector(1 downto 0); - -- - ahbrxd : in std_ulogic; + ahbrxd : in std_ulogic; ahbtxd : out std_ulogic; - urxd1 : in std_ulogic; - utxd1 : out std_ulogic - ); -end top; + urxd1 : in std_ulogic; + utxd1 : out std_ulogic; + data : inout std_logic_vector(31 downto 0); + address : out std_logic_vector(18 downto 0); + nBWa : out std_logic; + nBWb : out std_logic; + nBWc : out std_logic; + nBWd : out std_logic; + nBWE : out std_logic; + nADSC : out std_logic; + nADSP : out std_logic; + nADV : out std_logic; + nGW : out std_logic; + nCE1 : out std_logic; + CE2 : out std_logic; + nCE3 : out std_logic; + nOE : out std_logic; + MODE : out std_logic; + SSRAM_CLK : out std_logic; + ZZ : out std_logic + ); +end miniamba; -architecture Behavioral of top is - ---- AHB / APB -signal apbi : apb_slv_in_type; -signal apbo : apb_slv_out_vector := (others => apb_none); -signal ahbsi : ahb_slv_in_type; -signal ahbso : ahb_slv_out_vector := (others => ahbs_none); -signal ahbmi : ahb_mst_in_type; -signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); +architecture Behavioral of miniamba is + +--- AHB / APB +signal apbi : apb_slv_in_type; +signal apbo : apb_slv_out_vector := (others => apb_none); +signal ahbsi : ahb_slv_in_type; +signal ahbso : ahb_slv_out_vector := (others => ahbs_none); +signal ahbmi : ahb_mst_in_type; +signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); -- AHBUART -signal ahbuarti: uart_in_type; +signal ahbuarti: uart_in_type; signal ahbuarto: uart_out_type; -signal apbuarti: uart_in_type; +signal apbuarti: uart_in_type; signal apbuarto: uart_out_type; signal rxd2 : std_ulogic; signal rxd1 : std_ulogic; @@ -73,85 +96,155 @@ signal txd1 : std_ulogic; signal vcc : std_logic_vector(4 downto 0); signal gnd : std_logic_vector(4 downto 0); ---signal LED_rotary : std_logic_vector(7 downto 0); + +-- MEM CTRLR +signal memi : memory_in_type; +signal memo : memory_out_type; +signal sdo : sdram_out_type; +signal sdo3 : sdctrl_out_type; +signal wpo : wprot_out_type; signal clkm : std_ulogic; +signal resetnl : std_ulogic; +signal sdclkl : std_ulogic; +signal pciclk : std_ulogic; signal lclk : std_ulogic; signal rstn : std_ulogic; signal clk2x : std_ulogic; -signal rstraw : std_logic; +signal rstraw : std_logic; signal rstneg : std_logic; signal lock : std_logic; -signal cgi : clkgen_in_type; +signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; -constant BOARD_FREQ : integer := 50000; -- input frequency in KHz +-- LEON3 +signal irqi : irq_in_vector(0 to CFG_NCPU-1); +signal irqo : irq_out_vector(0 to CFG_NCPU-1); +signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); +signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); + +signal dsui : dsu_in_type; +signal dsuo : dsu_out_type; +signal dui : uart_in_type; +signal duo : uart_out_type; + + +constant boardfreq : integer := 50000; -- input frequency in KHz begin ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (others => '1'); gnd <= (others => '0'); - cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; - rstneg <= reset; - - rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw); - lock <= cgo.clklock; - - clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk); - - clkgen0 : clkgen -- clock generator MUL 4, DIV 5 - generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0) - port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x); +---------------------------------------------------------------------- +--- Reset and Clock generation ------------------------------------- +---------------------------------------------------------------------- + +-- vcc <= (others => '1'); gnd <= (others => '0'); +-- cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; +-- rstneg <= reset; +-- +-- rst0 : rstgen port map (rstneg, clkm, '1', rstn, rstraw); +-- lock <= cgo.clklock; +-- +-- clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk); +---- +---- clkgen0 : clkgen -- clock generator MUL 4, DIV 5 +---- generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0) +---- port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x); +-- +--process(lclk) +--begin +-- if lclk'event and lclk = '1' then +-- clkm <= not clkm; +-- end if; +--end process; + vcc <= (others => '1'); gnd <= (others => '0'); + cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; + + clk_pad : inpad generic map (tech => 0) port map (clk50MHz, lclk); + + clkgen0 : clkgen -- clock generator + generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, + CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) + port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo); + + resetn_pad : inpad generic map (tech => padtech) port map (reset, resetnl); + rst0 : rstgen -- reset generator + port map (resetnl, clkm, cgo.clklock, rstn, rstraw); + --led(5) <= cgo.clklock; + -------------------------------------- --- CLK_DIVIDER ---------------------- -------------------------------------- -clk_divider0 : Clk_divider - generic map (OSC_freqHz => 50000000, TargetFreq_Hz => 5) +clk_divider0 : Clk_divider + generic map (OSC_freqHz => 50000000, TargetFreq_Hz => 5) Port map( clkm, rstn, led(1)); -------------------------------- ---- AHB CONTROLLER ------------ -------------------------------- -ahb0 : ahbctrl -- AHB arbiter/multiplexer - generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1, - nahbm => CFG_NCPU+CFG_AHB_UART, - nahbs => 2) +------------------------------- +--- AHB CONTROLLER ------------ +------------------------------- +ahb0 : ahbctrl -- AHB arbiter/multiplexer + generic map (defmast => 0, --AHB_UART default master + split => CFG_SPLIT, + rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1, + nahbm => 3, + nahbs => 2) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); + +------------------------------- +--- MEMORY CONTROLLER --------- +------------------------------- +memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) + port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); + + +bdr : for i in 0 to 3 generate + data_pad : iopadv generic map (tech => padtech, width => 8) + port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), +memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); +end generate; + + + +addr_pad : outpadv generic map (width => 19, tech => padtech) + port map (address, memo.address(18 downto 0)); + + + +SSRAM_0:entity ssram_plugin +generic map (tech => padtech) +port map +(clkm,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); + ------------------------------- --- AHBUART ------------------- ------------------------------- dcom0 : ahbuart -- AMBA AHB Serial Debug Interface - generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7) - port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU)); + generic map (hindex => 1, pindex => 2, paddr => 2) + port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(2), ahbmi, ahbmo(1)); dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, rxd2); dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); ahbuarti.rxd <= rxd2; ----------------------------------------------------------------------- ---- APB Bridge and various periherals -------------------------------- ----------------------------------------------------------------------- +---------------------------------------------------------------------- +--- APB Bridge and various periherals -------------------------------- +---------------------------------------------------------------------- apb0 : apbctrl -- AHB/APB bridge - generic map (hindex => 1, haddr => CFG_APBADDR,nslaves => 1) - port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); + generic map (hindex => 3, haddr => CFG_APBADDR) + port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo); -uart1 : APB_UART - generic map( - pindex => 0, - paddr => 0) - port map( - clk => clkm, --! Horloge du composant - rst => rstn, --! Reset general du composant - apbi => apbi, --! Registre de gestion des entrées du bus - apbo => apbo(0), --! Registre de gestion des sorties du bus - TXD => utxd1, --! Transmission série, côté composant - RXD => urxd1 --! Reception série, côté composant - ); +uart1 : APB_UART + generic map( + pindex => 1, + paddr => 1) + port map( + clk => clkm, --! Horloge du composant + rst => rstn, --! Reset general du composant + apbi => apbi, --! Registre de gestion des entrées du bus + apbo => apbo(1), --! Registre de gestion des sorties du bus + TXD => utxd1, --! Transmission série, côté composant + RXD => urxd1 --! Reception série, côté composant + ); ---------------------------------- @@ -159,5 +252,4 @@ uart1 : APB_UART ---------------------------------- led(0) <= not rxd1; -end Behavioral; - +end Behavioral; \ No newline at end of file diff --git a/designs/LFR-142200-DM-MINIAMBA/top_libero.prj.convert.8.6.bak b/designs/LFR-142200-DM-MINIAMBA/top_libero.prj.convert.8.6.bak --- a/designs/LFR-142200-DM-MINIAMBA/top_libero.prj.convert.8.6.bak +++ b/designs/LFR-142200-DM-MINIAMBA/top_libero.prj.convert.8.6.bak @@ -14,6 +14,7 @@ CURREV=1 ENDLIST LIST LIBRARIES grlib +dw02 synplify techmap spw @@ -32,6 +33,10 @@ LIST LIBRARIES_grlib ALIAS=grlib COMPILE_OPTION=COMPILE ENDLIST +LIST LIBRARIES_dw02 +ALIAS=dw02 +COMPILE_OPTION=COMPILE +ENDLIST LIST LIBRARIES_synplify ALIAS=synplify COMPILE_OPTION=COMPILE @@ -165,6 +170,10 @@ VALUE "/../../lib/grlib/amba/am STATE="utd" LIBRARY="grlib" ENDFILE +VALUE "/../../lib/tech/dw02/comp/DW02_components.vhd,hdl" +STATE="utd" +LIBRARY="dw02" +ENDFILE VALUE "/../../lib/synplify/sim/synplify.vhd,hdl" STATE="utd" LIBRARY="synplify" @@ -185,6 +194,10 @@ VALUE "/../../lib/techmap/infer STATE="utd" LIBRARY="techmap" ENDFILE +VALUE "/../../lib/techmap/inferred/tap_inferred.vhd,hdl" +STATE="utd" +LIBRARY="techmap" +ENDFILE VALUE "/../../lib/techmap/inferred/ddr_inferred.vhd,hdl" STATE="utd" LIBRARY="techmap" @@ -197,6 +210,62 @@ VALUE "/../../lib/techmap/infer STATE="utd" LIBRARY="techmap" ENDFILE +VALUE "/../../lib/techmap/dw02/mul_dw_gen.vhd,hdl" +STATE="utd" +LIBRARY="techmap" +ENDFILE +VALUE "/../../lib/techmap/proasic3/a3pacomp.vhd,hdl" +STATE="utd" +LIBRARY="techmap" +ENDFILE +VALUE "/../../lib/techmap/proasic3/memory_apa3.vhd,hdl" +STATE="utd" +LIBRARY="techmap" +ENDFILE +VALUE "/../../lib/techmap/proasic3/buffer_apa3.vhd,hdl" +STATE="utd" +LIBRARY="techmap" +ENDFILE +VALUE "/../../lib/techmap/proasic3/pads_apa3.vhd,hdl" +STATE="utd" +LIBRARY="techmap" +ENDFILE +VALUE "/../../lib/techmap/proasic3/clkgen_proasic3.vhd,hdl" +STATE="utd" +LIBRARY="techmap" +ENDFILE +VALUE "/../../lib/techmap/proasic3/ddr_proasic3.vhd,hdl" +STATE="utd" +LIBRARY="techmap" +ENDFILE +VALUE "/../../lib/techmap/proasic3/tap_proasic3.vhd,hdl" +STATE="utd" +LIBRARY="techmap" +ENDFILE +VALUE "/../../lib/techmap/proasic3/grspwc_proasic3.vhd,hdl" +STATE="utd" +LIBRARY="techmap" +ENDFILE +VALUE "/../../lib/techmap/proasic3/leon3ft_proasic3.vhd,hdl" +STATE="utd" +LIBRARY="techmap" +ENDFILE +VALUE "/../../lib/techmap/proasic3/leon3ft_proasic3_8_4_v8.vhd,hdl" +STATE="utd" +LIBRARY="techmap" +ENDFILE +VALUE "/../../lib/techmap/proasic3/grspwc2_proasic3.vhd,hdl" +STATE="utd" +LIBRARY="techmap" +ENDFILE +VALUE "/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap0.vhd,hdl" +STATE="utd" +LIBRARY="techmap" +ENDFILE +VALUE "/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap1.vhd,hdl" +STATE="utd" +LIBRARY="techmap" +ENDFILE VALUE "/../../lib/techmap/maps/allclkgen.vhd,hdl" STATE="utd" LIBRARY="techmap" @@ -1085,6 +1154,10 @@ VALUE "/../../lib/lpp/./dsp/lpp STATE="utd" LIBRARY="lpp" ENDFILE +VALUE "/../../lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE VALUE "/../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl" STATE="utd" LIBRARY="lpp" @@ -1181,6 +1254,38 @@ VALUE "/../../lib/lpp/./lpp_amb STATE="utd" LIBRARY="lpp" ENDFILE +VALUE "/../../lib/lpp/./lpp_AMR/APB_AMR.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_AMR/Clock_multi.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_AMR/Dephaseur.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_AMR/Gene_Rz.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_AMR/bclk_reg.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_AMR/lpp_AMR.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_balise/APB_Balise.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_balise/lpp_balise.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE VALUE "/../../lib/lpp/./lpp_cna/APB_CNA.vhd,hdl" STATE="utd" LIBRARY="lpp" @@ -1209,6 +1314,54 @@ VALUE "/../../lib/lpp/./lpp_cna STATE="utd" LIBRARY="lpp" ENDFILE +VALUE "/../../lib/lpp/./lpp_matrix/ALU_Driver.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_matrix/ALU_v2.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_matrix/APB_Matrix.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_matrix/DriveInputs.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_matrix/GetResult.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_matrix/MAC_v2.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_matrix/Matrix.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_matrix/SelectInputs.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_matrix/SpectralMatrix.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_matrix/Starter.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_matrix/TwoComplementer.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_matrix/lpp_matrix.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE VALUE "/../../lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl" STATE="utd" LIBRARY="lpp" @@ -1237,15 +1390,11 @@ VALUE "/../../lib/lpp/./lpp_mem STATE="utd" LIBRARY="lpp" ENDFILE -VALUE "/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_memory/SSRAM_plugin.vhd,hdl" STATE="utd" LIBRARY="lpp" ENDFILE -VALUE "/../../lib/lpp/./lpp_memory/Top_FifoRead.vhd,hdl" -STATE="utd" -LIBRARY="lpp" -ENDFILE -VALUE "/../../lib/lpp/./lpp_memory/Top_FifoWrite.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl" STATE="utd" LIBRARY="lpp" ENDFILE @@ -1273,6 +1422,14 @@ VALUE "/../../lib/lpp/./lpp_uar STATE="utd" LIBRARY="lpp" ENDFILE +VALUE "/../../lib/lpp/./lpp_usb/RWbuf.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE +VALUE "/../../lib/lpp/./lpp_usb/lpp_usb.vhd,hdl" +STATE="utd" +LIBRARY="lpp" +ENDFILE VALUE "/../../lib/cypress/ssram/components.vhd,hdl" STATE="utd" LIBRARY="cypress" @@ -1332,6 +1489,7 @@ VALUE "/../../lib/grlib/sparc/s VALUE "/../../lib/grlib/sparc/cpu_disas.vhd,hdl" VALUE "/../../lib/grlib/amba/dma2ahb_tp.vhd,hdl" VALUE "/../../lib/grlib/amba/amba_tp.vhd,hdl" +VALUE "/../../lib/tech/dw02/comp/DW02_components.vhd,hdl" VALUE "/../../lib/synplify/sim/synplify.vhd,hdl" VALUE "/../../lib/synplify/sim/synattr.vhd,hdl" VALUE "/../../lib/gaisler/ambatest/ahbtbp.vhd,hdl" @@ -1395,9 +1553,24 @@ VALUE "/../../lib/grlib/amba/dm VALUE "/../../lib/techmap/gencomp/gencomp.vhd,hdl" VALUE "/../../lib/techmap/gencomp/netcomp.vhd,hdl" VALUE "/../../lib/techmap/inferred/memory_inferred.vhd,hdl" +VALUE "/../../lib/techmap/inferred/tap_inferred.vhd,hdl" VALUE "/../../lib/techmap/inferred/ddr_inferred.vhd,hdl" VALUE "/../../lib/techmap/inferred/mul_inferred.vhd,hdl" VALUE "/../../lib/techmap/inferred/ddr_phy_inferred.vhd,hdl" +VALUE "/../../lib/techmap/dw02/mul_dw_gen.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/a3pacomp.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/memory_apa3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/buffer_apa3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/pads_apa3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/clkgen_proasic3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/ddr_proasic3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/tap_proasic3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/grspwc_proasic3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/leon3ft_proasic3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/leon3ft_proasic3_8_4_v8.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/grspwc2_proasic3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap0.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap1.vhd,hdl" VALUE "/../../lib/techmap/maps/allclkgen.vhd,hdl" VALUE "/../../lib/techmap/maps/allddr.vhd,hdl" VALUE "/../../lib/techmap/maps/allmem.vhd,hdl" @@ -1595,6 +1768,7 @@ VALUE "/../../lib/lpp/./dsp/iir VALUE "/../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd,hdl" VALUE "/../../lib/lpp/./dsp/iir_filter/iir_filter.vhd,hdl" VALUE "/../../lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl" +VALUE "/../../lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd,hdl" VALUE "/../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl" VALUE "/../../lib/lpp/./general_purpose/ADDRcntr.vhd,hdl" VALUE "/../../lib/lpp/./general_purpose/ALU.vhd,hdl" @@ -1619,6 +1793,14 @@ VALUE "/../../lib/lpp/./lpp_amb VALUE "/../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl" VALUE "/../../lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl" VALUE "/../../lib/lpp/./lpp_amba/lpp_amba.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_AMR/APB_AMR.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_AMR/Clock_multi.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_AMR/Dephaseur.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_AMR/Gene_Rz.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_AMR/bclk_reg.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_AMR/lpp_AMR.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_balise/APB_Balise.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_balise/lpp_balise.vhd,hdl" VALUE "/../../lib/lpp/./lpp_cna/APB_CNA.vhd,hdl" VALUE "/../../lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl" VALUE "/../../lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl" @@ -1626,6 +1808,18 @@ VALUE "/../../lib/lpp/./lpp_cna VALUE "/../../lib/lpp/./lpp_cna/Serialize.vhd,hdl" VALUE "/../../lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl" VALUE "/../../lib/lpp/./lpp_cna/lpp_cna.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/ALU_Driver.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/ALU_v2.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/APB_Matrix.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/DriveInputs.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/GetResult.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/MAC_v2.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/Matrix.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/SelectInputs.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/SpectralMatrix.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/Starter.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/TwoComplementer.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/lpp_matrix.vhd,hdl" VALUE "/../../lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl" VALUE "/../../lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl" VALUE "/../../lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl" @@ -1633,15 +1827,16 @@ VALUE "/../../lib/lpp/./lpp_mem VALUE "/../../lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl" VALUE "/../../lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl" VALUE "/../../lib/lpp/./lpp_memory/Link_Reg.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_memory/SSRAM_plugin.vhd,hdl" VALUE "/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Top_FifoRead.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Top_FifoWrite.vhd,hdl" VALUE "/../../lib/lpp/./lpp_memory/lpp_memory.vhd,hdl" VALUE "/../../lib/lpp/./lpp_uart/APB_UART.vhd,hdl" VALUE "/../../lib/lpp/./lpp_uart/BaudGen.vhd,hdl" VALUE "/../../lib/lpp/./lpp_uart/Shift_REG.vhd,hdl" VALUE "/../../lib/lpp/./lpp_uart/UART.vhd,hdl" VALUE "/../../lib/lpp/./lpp_uart/lpp_uart.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_usb/RWbuf.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_usb/lpp_usb.vhd,hdl" VALUE "/config.vhd,hdl" VALUE "/ahbrom.vhd,hdl" VALUE "/leon3mp.vhd,hdl" @@ -1670,14 +1865,30 @@ VALUE "/../../lib/grlib/amba/dm VALUE "/../../lib/grlib/amba/dma2ahb.vhd,hdl" VALUE "/../../lib/grlib/amba/dma2ahb_tp.vhd,hdl" VALUE "/../../lib/grlib/amba/amba_tp.vhd,hdl" +VALUE "/../../lib/tech/dw02/comp/DW02_components.vhd,hdl" VALUE "/../../lib/synplify/sim/synplify.vhd,hdl" VALUE "/../../lib/synplify/sim/synattr.vhd,hdl" VALUE "/../../lib/techmap/gencomp/gencomp.vhd,hdl" VALUE "/../../lib/techmap/gencomp/netcomp.vhd,hdl" VALUE "/../../lib/techmap/inferred/memory_inferred.vhd,hdl" +VALUE "/../../lib/techmap/inferred/tap_inferred.vhd,hdl" VALUE "/../../lib/techmap/inferred/ddr_inferred.vhd,hdl" VALUE "/../../lib/techmap/inferred/mul_inferred.vhd,hdl" VALUE "/../../lib/techmap/inferred/ddr_phy_inferred.vhd,hdl" +VALUE "/../../lib/techmap/dw02/mul_dw_gen.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/a3pacomp.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/memory_apa3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/buffer_apa3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/pads_apa3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/clkgen_proasic3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/ddr_proasic3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/tap_proasic3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/grspwc_proasic3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/leon3ft_proasic3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/leon3ft_proasic3_8_4_v8.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/grspwc2_proasic3.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap0.vhd,hdl" +VALUE "/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap1.vhd,hdl" VALUE "/../../lib/techmap/maps/allclkgen.vhd,hdl" VALUE "/../../lib/techmap/maps/allddr.vhd,hdl" VALUE "/../../lib/techmap/maps/allmem.vhd,hdl" @@ -1900,6 +2111,7 @@ VALUE "/../../lib/lpp/./dsp/iir VALUE "/../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd,hdl" VALUE "/../../lib/lpp/./dsp/iir_filter/iir_filter.vhd,hdl" VALUE "/../../lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl" +VALUE "/../../lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd,hdl" VALUE "/../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl" VALUE "/../../lib/lpp/./general_purpose/ADDRcntr.vhd,hdl" VALUE "/../../lib/lpp/./general_purpose/ALU.vhd,hdl" @@ -1924,6 +2136,14 @@ VALUE "/../../lib/lpp/./lpp_amb VALUE "/../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl" VALUE "/../../lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl" VALUE "/../../lib/lpp/./lpp_amba/lpp_amba.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_AMR/APB_AMR.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_AMR/Clock_multi.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_AMR/Dephaseur.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_AMR/Gene_Rz.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_AMR/bclk_reg.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_AMR/lpp_AMR.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_balise/APB_Balise.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_balise/lpp_balise.vhd,hdl" VALUE "/../../lib/lpp/./lpp_cna/APB_CNA.vhd,hdl" VALUE "/../../lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl" VALUE "/../../lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl" @@ -1931,6 +2151,18 @@ VALUE "/../../lib/lpp/./lpp_cna VALUE "/../../lib/lpp/./lpp_cna/Serialize.vhd,hdl" VALUE "/../../lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl" VALUE "/../../lib/lpp/./lpp_cna/lpp_cna.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/ALU_Driver.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/ALU_v2.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/APB_Matrix.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/DriveInputs.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/GetResult.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/MAC_v2.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/Matrix.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/SelectInputs.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/SpectralMatrix.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/Starter.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/TwoComplementer.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_matrix/lpp_matrix.vhd,hdl" VALUE "/../../lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl" VALUE "/../../lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl" VALUE "/../../lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl" @@ -1938,15 +2170,16 @@ VALUE "/../../lib/lpp/./lpp_mem VALUE "/../../lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl" VALUE "/../../lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl" VALUE "/../../lib/lpp/./lpp_memory/Link_Reg.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_memory/SSRAM_plugin.vhd,hdl" VALUE "/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Top_FifoRead.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Top_FifoWrite.vhd,hdl" VALUE "/../../lib/lpp/./lpp_memory/lpp_memory.vhd,hdl" VALUE "/../../lib/lpp/./lpp_uart/APB_UART.vhd,hdl" VALUE "/../../lib/lpp/./lpp_uart/BaudGen.vhd,hdl" VALUE "/../../lib/lpp/./lpp_uart/Shift_REG.vhd,hdl" VALUE "/../../lib/lpp/./lpp_uart/UART.vhd,hdl" VALUE "/../../lib/lpp/./lpp_uart/lpp_uart.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_usb/RWbuf.vhd,hdl" +VALUE "/../../lib/lpp/./lpp_usb/lpp_usb.vhd,hdl" VALUE "/../../lib/cypress/ssram/components.vhd,hdl" VALUE "/../../lib/cypress/ssram/package_utility.vhd,hdl" VALUE "/../../lib/cypress/ssram/cy7c1354b.vhd,hdl" diff --git a/lib/lpp/Doxyfile b/lib/lpp/Doxyfile --- a/lib/lpp/Doxyfile +++ b/lib/lpp/Doxyfile @@ -1,4 +1,4 @@ -# Doxyfile 1.7.1 +# Doxyfile 1.7.5.1 # This file describes the settings to be used by the documentation system # doxygen (www.doxygen.org) for a project @@ -22,8 +22,9 @@ DOXYFILE_ENCODING = UTF-8 -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. +# The PROJECT_NAME tag is a single word (or sequence of words) that should +# identify the project. Note that if you do not use Doxywizard you need +# to put quotes around the project name if it contains spaces. PROJECT_NAME = lib-lpp @@ -31,7 +32,20 @@ PROJECT_NAME = lib-lpp # This could be handy for archiving the generated documentation or # if some version control system is used. -PROJECT_NUMBER = 0.4 +PROJECT_NUMBER = 1.0 + +# Using the PROJECT_BRIEF tag one can provide an optional one line description +# for a project that appears at the top of each page and should give viewer +# a quick idea about the purpose of the project. Keep the description short. + +PROJECT_BRIEF = + +# With the PROJECT_LOGO tag one can specify an logo or icon that is +# included in the documentation. The maximum height of the logo should not +# exceed 55 pixels and the maximum width should not exceed 200 pixels. +# Doxygen will copy the logo to the output directory. + +PROJECT_LOGO = # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) # base path where the generated documentation will be put. @@ -57,7 +71,7 @@ CREATE_SUBDIRS = NO # Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, # Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English # messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, +# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak, # Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. OUTPUT_LANGUAGE = English @@ -136,7 +150,7 @@ STRIP_FROM_PATH = STRIP_FROM_INC_PATH = # If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems +# (but less readable) file names. This can be useful if your file system # doesn't support long names like on DOS, Mac, or CD-ROM. SHORT_NAMES = NO @@ -233,7 +247,7 @@ EXTENSION_MAPPING = # to include (a tag file for) the STL sources as input, then you should # set this tag to YES in order to let doxygen match functions declarations and # definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration +# func(std::string) {}). This also makes the inheritance and collaboration # diagrams that involve STL classes more complete and accurate. BUILTIN_STL_SUPPORT = NO @@ -251,7 +265,7 @@ SIP_SUPPORT = NO # For Microsoft's IDL there are propget and propput attributes to indicate getter # and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the +# will make doxygen replace the get and set methods by a property in the # documentation. This will only work if the methods are indeed getting or # setting a simple type. If this is not the case, or you want to show the # methods anyway, you should set this option to NO. @@ -273,6 +287,22 @@ DISTRIBUTE_GROUP_DOC = NO SUBGROUPING = YES +# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and +# unions are shown inside the group in which they are included (e.g. using +# @ingroup) instead of on a separate page (for HTML and Man pages) or +# section (for LaTeX and RTF). + +INLINE_GROUPED_CLASSES = NO + +# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and +# unions with only public data fields will be shown inline in the documentation +# of the scope in which they are defined (i.e. file, namespace, or group +# documentation), provided this scope is documented. If set to NO (the default), +# structs, classes, and unions are shown on a separate page (for HTML and Man +# pages) or section (for LaTeX and RTF). + +INLINE_SIMPLE_STRUCTS = NO + # When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum # is documented as struct, union, or enum with the name of the typedef. So # typedef struct TypeS {} TypeT, will appear in the documentation as a struct @@ -289,10 +319,10 @@ TYPEDEF_HIDES_STRUCT = NO # For small to medium size projects (<1000 input files) the default value is # probably good enough. For larger projects a too small cache size can cause # doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. +# causing a significant performance penalty. # If the system has enough physical memory increasing the cache will improve the # performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the +# a logarithmic scale so increasing the size by one will roughly double the # memory usage. The cache size is given by this formula: # 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, # corresponding to a cache size of 2^16 = 65536 symbols @@ -337,7 +367,7 @@ EXTRACT_LOCAL_METHODS = NO # extracted and appear in the documentation as a namespace called # 'anonymous_namespace{file}', where file will be replaced with the base # name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. +# anonymous namespaces are hidden. EXTRACT_ANON_NSPACES = NO @@ -448,6 +478,15 @@ SORT_GROUP_NAMES = NO SORT_BY_SCOPE_NAME = NO +# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to +# do proper type resolution of all parameters of a function it will reject a +# match between the prototype and the implementation of a member function even +# if there is only one candidate or it is obvious which candidate to choose +# by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen +# will still accept a match between prototype and implementation in such cases. + +STRICT_PROTO_MATCHING = NO + # The GENERATE_TODOLIST tag can be used to enable (YES) or # disable (NO) the todo list. This list is created by putting \todo # commands in the documentation. @@ -478,10 +517,10 @@ GENERATE_DEPRECATEDLIST= YES ENABLED_SECTIONS = # The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in +# the initial value of a variable or macro consists of for it to appear in # the documentation. If the initializer consists of more lines than specified # here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the +# The appearance of the initializer of individual variables and macros in the # documentation can be controlled using \showinitializer or \hideinitializer # command in the documentation regardless of this setting. @@ -530,6 +569,15 @@ FILE_VERSION_FILTER = LAYOUT_FILE = +# The CITE_BIB_FILES tag can be used to specify one or more bib files +# containing the references data. This must be a list of .bib files. The +# .bib extension is automatically appended if omitted. Using this command +# requires the bibtex tool to be installed. See also +# http://en.wikipedia.org/wiki/BibTeX for more info. For LaTeX the style +# of the bibliography can be controlled using LATEX_BIB_STYLE. + +CITE_BIB_FILES = + #--------------------------------------------------------------------------- # configuration options related to warning and progress messages #--------------------------------------------------------------------------- @@ -558,7 +606,7 @@ WARN_IF_UNDOCUMENTED = YES WARN_IF_DOC_ERROR = YES -# This WARN_NO_PARAMDOC option can be abled to get warnings for +# The WARN_NO_PARAMDOC option can be enabled to get warnings for # functions that are documented, but have no documentation for their parameters # or return value. If set to NO (the default) doxygen will only warn about # wrong or incomplete parameter documentation, but not about the absence of @@ -604,8 +652,9 @@ INPUT_ENCODING = UTF-8 # FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp # and *.h) to filter out the source-files in the directories. If left # blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 +# *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh +# *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py +# *.f90 *.f *.for *.vhd *.vhdl FILE_PATTERNS = *.c \ *.cc \ @@ -647,12 +696,13 @@ RECURSIVE = YES # The EXCLUDE tag can be used to specify files and/or directories that should # excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. +# subdirectory from a directory tree whose root is specified with the INPUT tag. +# Note that relative paths are relative to directory from which doxygen is run. EXCLUDE = # The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded +# directories that are symbolic links (a Unix file system feature) are excluded # from the input. EXCLUDE_SYMLINKS = NO @@ -713,8 +763,8 @@ INPUT_FILTER = # basis. Doxygen will compare the file name with each pattern and apply the # filter if there is a match. The filters are a list of the form: # pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. +# info on how filters are used. If FILTER_PATTERNS is empty or if +# non of the patterns match the file name, INPUT_FILTER is applied. FILTER_PATTERNS = @@ -724,6 +774,14 @@ FILTER_PATTERNS = FILTER_SOURCE_FILES = NO +# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file +# pattern. A pattern will override the setting for FILTER_PATTERN (if any) +# and it is also possible to disable source filtering for a specific pattern +# using *.ext= (so without naming a filter). This option only has effect when +# FILTER_SOURCE_FILES is enabled. + +FILTER_SOURCE_PATTERNS = + #--------------------------------------------------------------------------- # configuration options related to source browsing #--------------------------------------------------------------------------- @@ -733,7 +791,7 @@ FILTER_SOURCE_FILES = NO # Note: To get rid of all source code in the generated output, make sure also # VERBATIM_HEADERS is set to NO. -SOURCE_BROWSER = YES +SOURCE_BROWSER = NO # Setting the INLINE_SOURCES tag to YES will include the body # of functions and classes directly in the documentation. @@ -825,15 +883,22 @@ HTML_FILE_EXTENSION = .html # The HTML_HEADER tag can be used to specify a personal HTML header for # each generated HTML page. If it is left blank doxygen will generate a -# standard header. +# standard header. Note that when using a custom header you are responsible +# for the proper inclusion of any scripts and style sheets that doxygen +# needs, which is dependent on the configuration options used. +# It is adviced to generate a default header using "doxygen -w html +# header.html footer.html stylesheet.css YourConfigFile" and then modify +# that header. Note that the header is subject to change so you typically +# have to redo this when upgrading to a newer version of doxygen or when +# changing the value of configuration settings such as GENERATE_TREEVIEW! -HTML_HEADER = ../../doc/ressources/Header +HTML_HEADER = # The HTML_FOOTER tag can be used to specify a personal HTML footer for # each generated HTML page. If it is left blank doxygen will generate a # standard footer. -HTML_FOOTER = ../../doc/ressources/Footer +HTML_FOOTER = # The HTML_STYLESHEET tag can be used to specify a user-defined cascading # style sheet that is used by each HTML page. It can be used to @@ -842,7 +907,16 @@ HTML_FOOTER = ../../doc/resso # the style sheet file to the HTML output directory, so don't put your own # stylesheet in the HTML output directory as well, or it will be erased! -HTML_STYLESHEET = ../../doc/ressources/doxygen.css +HTML_STYLESHEET = + +# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or +# other source files which should be copied to the HTML output directory. Note +# that these files will be copied to the base HTML output directory. Use the +# $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these +# files. In the HTML_STYLESHEET file, use the file name only. Also note that +# the files will be copied as-is; there are no commands or markers available. + +HTML_EXTRA_FILES = # The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. # Doxygen will adjust the colors in the stylesheet and background images @@ -1046,8 +1120,10 @@ ECLIPSE_DOC_ID = org.doxygen.Pro DISABLE_INDEX = NO -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. +# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values +# (range [0,1..20]) that doxygen will group on one line in the generated HTML +# documentation. Note that a value of 0 will completely suppress the enum +# values from appearing in the overview section. ENUM_VALUES_PER_LINE = 4 @@ -1093,6 +1169,31 @@ FORMULA_FONTSIZE = 10 FORMULA_TRANSPARENT = YES +# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax +# (see http://www.mathjax.org) which uses client side Javascript for the +# rendering instead of using prerendered bitmaps. Use this if you do not +# have LaTeX installed or if you want to formulas look prettier in the HTML +# output. When enabled you also need to install MathJax separately and +# configure the path to it using the MATHJAX_RELPATH option. + +USE_MATHJAX = NO + +# When MathJax is enabled you need to specify the location relative to the +# HTML output directory using the MATHJAX_RELPATH option. The destination +# directory should contain the MathJax.js script. For instance, if the mathjax +# directory is located at the same level as the HTML output directory, then +# MATHJAX_RELPATH should be ../mathjax. The default value points to the +# mathjax.org site, so you can quickly see the result without installing +# MathJax, but it is strongly recommended to install a local copy of MathJax +# before deployment. + +MATHJAX_RELPATH = http://www.mathjax.org/mathjax + +# The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension +# names that should be enabled during MathJax rendering. + +MATHJAX_EXTENSIONS = + # When the SEARCHENGINE tag is enabled doxygen will generate a search box # for the HTML output. The underlying search engine uses javascript # and DHTML and should work on any modern browser. Note that when using @@ -1108,7 +1209,7 @@ SEARCHENGINE = YES # using Javascript. Doxygen will generate the search PHP script and index # file to put on the web server. The advantage of the server # based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup +# full text search. The disadvantages are that it is more difficult to setup # and does not have live searching capabilities. SERVER_BASED_SEARCH = NO @@ -1146,13 +1247,13 @@ MAKEINDEX_CMD_NAME = makeindex # LaTeX documents. This may be useful for small projects and may help to # save some trees in general. -COMPACT_LATEX = YES +COMPACT_LATEX = NO # The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and +# by the printer. Possible values are: a4, letter, legal and # executive. If left blank a4wide will be used. -PAPER_TYPE = letter +PAPER_TYPE = a4wide # The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX # packages that should be included in the LaTeX output. @@ -1166,6 +1267,13 @@ EXTRA_PACKAGES = LATEX_HEADER = +# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for +# the generated latex document. The footer should contain everything after +# the last chapter. If it is left blank doxygen will generate a +# standard footer. Notice: only use this tag if you know what you are doing! + +LATEX_FOOTER = + # If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated # is prepared for conversion to pdf (using ps2pdf). The pdf file will # contain links (just like the HTML output) instead of page references @@ -1199,6 +1307,12 @@ LATEX_HIDE_INDICES = NO LATEX_SOURCE_CODE = NO +# The LATEX_BIB_STYLE tag can be used to specify the style to use for the +# bibliography, e.g. plainnat, or ieeetr. The default style is "plain". See +# http://en.wikipedia.org/wiki/BibTeX for more info. + +LATEX_BIB_STYLE = plain + #--------------------------------------------------------------------------- # configuration options related to the RTF output #--------------------------------------------------------------------------- @@ -1373,7 +1487,7 @@ MACRO_EXPANSION = NO EXPAND_ONLY_PREDEF = NO # If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. +# pointed to by INCLUDE_PATH will be searched when a #include is found. SEARCH_INCLUDES = YES @@ -1403,15 +1517,15 @@ PREDEFINED = # If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then # this tag can be used to specify a list of macro names that should be expanded. # The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. +# Use the PREDEFINED tag if you want to use a different macro definition that +# overrules the definition found in the source code. EXPAND_AS_DEFINED = # If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. +# doxygen's preprocessor will remove all references to function-like macros +# that are alone on a line, have an all uppercase name, and do not end with a +# semicolon, because these will confuse the parser if not removed. SKIP_FUNCTION_MACROS = YES @@ -1465,11 +1579,10 @@ PERL_PATH = /usr/bin/perl # If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will # generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base # or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. +# this option also works with HAVE_DOT disabled, but it is recommended to +# install and use dot, since it yields more powerful graphs. -CLASS_DIAGRAMS = NO +CLASS_DIAGRAMS = YES # You can define message sequence charts within doxygen comments using the \msc # command. Doxygen will then run the mscgen tool (see @@ -1501,14 +1614,12 @@ HAVE_DOT = YES DOT_NUM_THREADS = 0 -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. +# By default doxygen will use the Helvetica font for all dot files that +# doxygen generates. When you want a differently looking font you can specify +# the font name using DOT_FONTNAME. You need to make sure dot is able to find +# the font, which can be done by putting it in a standard location or by setting +# the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the +# directory containing the font. DOT_FONTNAME = FreeSans.ttf @@ -1517,10 +1628,9 @@ DOT_FONTNAME = FreeSans.ttf DOT_FONTSIZE = 10 -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. +# By default doxygen will tell dot to use the Helvetica font. +# If you specify a different font using DOT_FONTNAME you can use DOT_FONTPATH to +# set the path where dot can find it. DOT_FONTPATH = @@ -1547,7 +1657,7 @@ GROUP_GRAPHS = YES # collaboration diagrams in a style similar to the OMG's Unified Modeling # Language. -UML_LOOK = YES +UML_LOOK = NO # If set to YES, the inheritance and collaboration graphs will show the # relations between templates and their instances. @@ -1585,7 +1695,7 @@ CALL_GRAPH = NO CALLER_GRAPH = NO # If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. +# will generate a graphical hierarchy of all classes instead of a textual one. GRAPHICAL_HIERARCHY = YES @@ -1597,11 +1707,22 @@ GRAPHICAL_HIERARCHY = YES DIRECTORY_GRAPH = YES # The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. +# generated by dot. Possible values are svg, png, jpg, or gif. +# If left blank png will be used. If you choose svg you need to set +# HTML_FILE_EXTENSION to xhtml in order to make the SVG files +# visible in IE 9+ (other browsers do not have this requirement). DOT_IMAGE_FORMAT = png +# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to +# enable generation of interactive SVG images that allow zooming and panning. +# Note that this requires a modern browser other than Internet Explorer. +# Tested and working are Firefox, Chrome, Safari, and Opera. For IE 9+ you +# need to set HTML_FILE_EXTENSION to xhtml in order to make the SVG files +# visible. Older versions of IE do not have SVG support. + +INTERACTIVE_SVG = NO + # The tag DOT_PATH can be used to specify the path where the dot tool can be # found. If left blank, it is assumed the dot tool can be found in the path. @@ -1613,6 +1734,12 @@ DOT_PATH = DOTFILE_DIRS = +# The MSCFILE_DIRS tag can be used to specify one or more directories that +# contain msc files that are included in the documentation (see the +# \mscfile command). + +MSCFILE_DIRS = + # The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of # nodes that will be shown in the graph. If the number of nodes in a graph # becomes larger than this value, doxygen will truncate the graph, which is diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -26,6 +26,9 @@ use grlib.amba.all; use std.textio.all; library lpp; use lpp.lpp_amba.all; +library gaisler; +use gaisler.misc.all; +use gaisler.memctrl.all; --! Package contenant tous les programmes qui forment le composant intégré dans le léon