@@ -45,8 +45,8 USE lpp.general_purpose.ALL; | |||
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45 | 45 | USE lpp.lpp_lfr_management.ALL; |
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46 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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47 | 47 | |
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48 |
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49 |
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48 | library proasic3l; | |
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49 | use proasic3l.all; | |
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50 | 50 | |
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51 | 51 | ENTITY LFR_EQM IS |
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52 | 52 | --GENERIC ( |
@@ -64,7 +64,7 ENTITY LFR_EQM IS | |||
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64 | 64 | TAG2 : IN STD_ULOGIC; -- UART1 rx data |
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65 | 65 | TAG4 : OUT STD_ULOGIC; -- UART1 tx data |
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66 | 66 | -- RAM -------------------------------------------------------------------- |
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67 |
address : OUT STD_LOGIC_VECTOR(1 |
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67 | address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); | |
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68 | 68 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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69 | 69 | |
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70 | 70 | nSRAM_MBE : INOUT STD_LOGIC; -- new |
@@ -217,8 +217,8 BEGIN -- beh | |||
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217 | 217 | NB_AHB_MASTER => NB_AHB_MASTER, |
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218 | 218 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
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219 | 219 | NB_APB_SLAVE => NB_APB_SLAVE, |
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220 |
ADDRESS_SIZE => |
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221 |
USES_IAP_MEMCTRLR => |
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220 | ADDRESS_SIZE => 19, | |
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221 | USES_IAP_MEMCTRLR => 1, | |
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222 | 222 | BYPASS_EDAC_MEMCTRLR => '0', |
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223 | 223 | SRBANKSZ => 8) |
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224 | 224 | PORT MAP ( |
@@ -1,4 +1,3 | |||
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1 | ||
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2 | 1 |
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3 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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4 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
@@ -75,17 +74,17 ARCHITECTURE Behavioral OF lpp_dma_SEND1 | |||
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75 | 74 | 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0), |
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76 | 75 | OTHERS => (OTHERS => '0')); |
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77 | 76 | |
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77 | TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA); | |
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78 | SIGNAL state : AHB_DMA_FSM_STATE; | |
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79 | ||
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78 | 80 |
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79 | 81 | SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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80 | 82 | |
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81 |
SIGNAL |
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82 |
SIGNAL |
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83 | SIGNAL data_window : STD_LOGIC; | |
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84 | SIGNAL ctrl_window : STD_LOGIC; | |
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83 | 85 | |
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84 |
SIGNAL |
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85 |
SIGNAL |
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86 | SIGNAL DATA_ON_GOING_s : STD_LOGIC; | |
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87 | SIGNAL TRANSACTION_ON_GOING : STD_LOGIC; | |
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88 | SIGNAL internal_send : STD_LOGIC; | |
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86 | SIGNAL bus_request : STD_LOGIC; | |
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87 | SIGNAL bus_lock : STD_LOGIC; | |
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89 | 88 | |
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90 | 89 | BEGIN |
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91 | 90 | |
@@ -95,84 +94,120 BEGIN | |||
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95 | 94 | AHB_Master_Out.HINDEX <= hindex; |
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96 | 95 | AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS |
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97 | 96 | AHB_Master_Out.HIRQ <= (OTHERS => '0'); |
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98 |
AHB_Master_Out.HBURST <= " |
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97 | AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16 | |
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99 | 98 | AHB_Master_Out.HWRITE <= '1'; |
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100 | AHB_Master_Out.HTRANS <= HTRANS_NONSEQ; | |
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99 | ||
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100 | --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE; | |
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101 | ||
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102 | --AHB_Master_Out.HBUSREQ <= bus_request; | |
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103 | --AHB_Master_Out.HLOCK <= data_window; | |
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101 | 104 | |
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102 |
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103 | AHB_Master_Out.HLOCK <= REQ_ON_GOING WHEN NOT(address_counter = "1111" AND AHB_Master_In.HREADY = '1') ELSE '0'; | |
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105 | --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE | |
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106 | -- '1' WHEN ctrl_window = '1' ELSE | |
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107 | -- '0'; | |
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108 | ||
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109 | --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE | |
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110 | -- '1' WHEN ctrl_window = '1' ELSE '0'; | |
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111 | ||
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104 | 112 |
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105 | ||
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106 | 113 | AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00"; |
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107 | 114 | AHB_Master_Out.HWDATA <= ahbdrivedata(data); |
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108 | 115 | |
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109 | ||
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110 | 116 | ----------------------------------------------------------------------------- |
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111 | -- REN GEN | |
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112 | ----------------------------------------------------------------------------- | |
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113 | ren <= NOT (AHB_Master_In.HREADY AND DATA_ON_GOING); | |
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114 | ||
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115 | ----------------------------------------------------------------------------- | |
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116 | -- ADDR GEN | |
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117 | --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY ); | |
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118 | --ren <= NOT beat; | |
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117 | 119 | ----------------------------------------------------------------------------- |
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118 | 120 | PROCESS (clk, rstn) |
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119 | 121 | BEGIN -- PROCESS |
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120 | 122 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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123 | state <= IDLE; | |
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124 | done <= '0'; | |
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121 | 125 | address_counter_reg <= (OTHERS => '0'); |
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122 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
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123 | IF DATA_ON_GOING = '0' THEN | |
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124 | address_counter_reg <= (OTHERS => '0'); | |
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125 | ELSE | |
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126 | address_counter_reg <= address_counter; | |
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127 | END IF; | |
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128 | END IF; | |
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129 | END PROCESS; | |
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130 | ||
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131 | --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN AHB_Master_In.HGRANT(hindex) = '1' AND REQ_ON_GOING = '1' AND AHB_Master_In.HREADY = '1' ELSE | |
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132 | -- address_counter_reg; | |
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133 | address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN DATA_ON_GOING = '1' AND AHB_Master_In.HREADY = '1' ELSE | |
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134 | address_counter_reg; | |
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135 | ||
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136 | ----------------------------------------------------------------------------- | |
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137 | -- | |
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138 | ----------------------------------------------------------------------------- | |
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139 | PROCESS (clk, rstn) | |
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140 | BEGIN -- PROCESS | |
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141 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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142 | REQ_ON_GOING <= '0'; | |
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143 | done <= '0'; | |
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144 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
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126 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; | |
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127 | AHB_Master_Out.HBUSREQ <= '0'; | |
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128 | AHB_Master_Out.HLOCK <= '0'; | |
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129 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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145 | 130 | done <= '0'; |
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146 | IF send = '1' THEN --send = '1' THEN | |
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147 | REQ_ON_GOING <= '1'; | |
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148 | ELSE | |
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149 | IF address_counter = "1111" AND AHB_Master_In.HREADY = '1' THEN | |
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150 | REQ_ON_GOING <= '0'; | |
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151 | done <= '1'; | |
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152 | END IF; | |
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153 | END IF; | |
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131 | CASE state IS | |
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132 | WHEN IDLE => | |
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133 | AHB_Master_Out.HBUSREQ <= '0'; | |
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134 | AHB_Master_Out.HLOCK <= '0'; | |
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135 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; | |
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136 | address_counter_reg <= (OTHERS => '0'); | |
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137 | IF send = '1' THEN | |
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138 | AHB_Master_Out.HBUSREQ <= '1'; | |
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139 | AHB_Master_Out.HLOCK <= '1'; | |
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140 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; | |
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141 | state <= s_ARBITER; | |
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142 | END IF; | |
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143 | ||
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144 | WHEN s_ARBITER => | |
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145 | AHB_Master_Out.HBUSREQ <= '1'; | |
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146 | AHB_Master_Out.HLOCK <= '1'; | |
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147 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; | |
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148 | address_counter_reg <= (OTHERS => '0'); | |
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149 | ||
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150 | IF AHB_Master_In.HGRANT(hindex) = '1' THEN | |
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151 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; | |
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152 | state <= s_CTRL; | |
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153 | END IF; | |
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154 | ||
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155 | WHEN s_CTRL => | |
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156 | AHB_Master_Out.HBUSREQ <= '1'; | |
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157 | AHB_Master_Out.HLOCK <= '1'; | |
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158 | AHB_Master_Out.HTRANS <= HTRANS_NONSEQ; | |
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159 | IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN | |
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160 | AHB_Master_Out.HTRANS <= HTRANS_SEQ; | |
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161 | state <= s_CTRL_DATA; | |
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162 | END IF; | |
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163 | ||
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164 | WHEN s_CTRL_DATA => | |
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165 | AHB_Master_Out.HBUSREQ <= '1'; | |
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166 | AHB_Master_Out.HLOCK <= '1'; | |
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167 | AHB_Master_Out.HTRANS <= HTRANS_SEQ; | |
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168 | IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN | |
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169 | address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1); | |
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170 | END IF; | |
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171 | ||
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172 | IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN | |
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173 | AHB_Master_Out.HBUSREQ <= '0'; | |
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174 | AHB_Master_Out.HLOCK <= '1';--'0'; | |
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175 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; | |
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176 | state <= s_DATA; | |
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177 | END IF; | |
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178 | ||
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179 | WHEN s_DATA => | |
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180 | AHB_Master_Out.HBUSREQ <= '0'; | |
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181 | AHB_Master_Out.HLOCK <= '0'; | |
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182 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; | |
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183 | IF AHB_Master_In.HREADY = '1' THEN | |
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184 | state <= IDLE; | |
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185 | done <= '1'; | |
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186 | END IF; | |
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187 | ||
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188 | WHEN OTHERS => NULL; | |
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189 | END CASE; | |
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154 | 190 | END IF; |
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155 | 191 | END PROCESS; |
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156 | 192 | |
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193 | ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0'; | |
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194 | data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0'; | |
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157 | 195 | ----------------------------------------------------------------------------- |
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158 | -- | |
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196 | ren <= NOT( data_window AND AHB_Master_In.HREADY); | |
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197 | ||
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159 | 198 | ----------------------------------------------------------------------------- |
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160 | PROCESS (clk, rstn) | |
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161 | BEGIN -- PROCESS | |
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162 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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163 | DATA_ON_GOING <= '0'; | |
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164 |
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165 | IF REQ_ON_GOING = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN | |
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166 | DATA_ON_GOING <= '1'; | |
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167 | ELSE | |
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168 | IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN | |
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169 | DATA_ON_GOING <= '0'; | |
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170 | END IF; | |
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171 | -- DATA_ON_GOING_s <= REQ_ON_GOING ; | |
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172 | END IF; | |
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173 | END IF; | |
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174 | END PROCESS; | |
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175 | --DATA_ON_GOING <= DATA_ON_GOING_s AND REQ_ON_GOING; | |
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176 | ||
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199 | --PROCESS (clk, rstn) | |
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200 | --BEGIN -- PROCESS | |
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201 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |
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202 | -- address_counter_reg <= (OTHERS => '0'); | |
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203 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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204 | -- address_counter_reg <= address_counter; | |
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205 | -- END IF; | |
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206 | --END PROCESS; | |
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207 | ||
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208 | --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE | |
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209 | -- address_counter_reg; | |
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210 | ----------------------------------------------------------------------------- | |
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211 | ||
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177 | 212 |
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178 | 213 | END Behavioral; |
@@ -364,11 +364,11 BEGIN | |||
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364 | 364 | dsugen : IF CFG_DSU = 1 GENERATE |
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365 | 365 | |
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366 | 366 | dsu0 : dsu3 -- LEON3 Debug Support Unit |
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367 |
GENERIC MAP (hindex => |
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367 | GENERIC MAP (hindex => 0, -- TODO : hindex => 2 | |
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368 | 368 | haddr => 16#900#, hmask => 16#F00#, |
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369 | 369 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, |
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370 | 370 | irq => 0, kbytes => CFG_ATBSZ) |
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371 |
PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso( |
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371 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),-- TODO :ahbso(2) | |
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372 | 372 | dbgo, dbgi, dsui, dsuo); |
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373 | 373 | dsui.enable <= '1'; |
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374 | 374 | dsui.break <= '0'; |
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