diff --git a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd --- a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd +++ b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd @@ -45,8 +45,8 @@ USE lpp.general_purpose.ALL; USE lpp.lpp_lfr_management.ALL; USE lpp.lpp_leon3_soc_pkg.ALL; ---library proasic3l; ---use proasic3l.all; +library proasic3l; +use proasic3l.all; ENTITY LFR_EQM IS --GENERIC ( @@ -64,7 +64,7 @@ ENTITY LFR_EQM IS TAG2 : IN STD_ULOGIC; -- UART1 rx data TAG4 : OUT STD_ULOGIC; -- UART1 tx data -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); nSRAM_MBE : INOUT STD_LOGIC; -- new @@ -217,8 +217,8 @@ BEGIN -- beh NB_AHB_MASTER => NB_AHB_MASTER, NB_AHB_SLAVE => NB_AHB_SLAVE, NB_APB_SLAVE => NB_APB_SLAVE, - ADDRESS_SIZE => 20, - USES_IAP_MEMCTRLR => 0, + ADDRESS_SIZE => 19, + USES_IAP_MEMCTRLR => 1, BYPASS_EDAC_MEMCTRLR => '0', SRBANKSZ => 8) PORT MAP ( diff --git a/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd b/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd --- a/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd @@ -1,4 +1,3 @@ - ------------------------------------------------------------------------------ -- This file is a part of the LPP VHDL IP LIBRARY -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS @@ -75,17 +74,17 @@ ARCHITECTURE Behavioral OF lpp_dma_SEND1 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0), OTHERS => (OTHERS => '0')); + TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA); + SIGNAL state : AHB_DMA_FSM_STATE; + SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL address_counter_reset : STD_LOGIC; - SIGNAL address_counter_add1 : STD_LOGIC; + SIGNAL data_window : STD_LOGIC; + SIGNAL ctrl_window : STD_LOGIC; - SIGNAL REQ_ON_GOING : STD_LOGIC; - SIGNAL DATA_ON_GOING : STD_LOGIC; - SIGNAL DATA_ON_GOING_s : STD_LOGIC; - SIGNAL TRANSACTION_ON_GOING : STD_LOGIC; - SIGNAL internal_send : STD_LOGIC; + SIGNAL bus_request : STD_LOGIC; + SIGNAL bus_lock : STD_LOGIC; BEGIN @@ -95,84 +94,120 @@ BEGIN AHB_Master_Out.HINDEX <= hindex; AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS AHB_Master_Out.HIRQ <= (OTHERS => '0'); - AHB_Master_Out.HBURST <= "001"; -- INCR --"111"; --INCR16 + AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16 AHB_Master_Out.HWRITE <= '1'; - AHB_Master_Out.HTRANS <= HTRANS_NONSEQ; + + --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE; + + --AHB_Master_Out.HBUSREQ <= bus_request; + --AHB_Master_Out.HLOCK <= data_window; - AHB_Master_Out.HBUSREQ <= REQ_ON_GOING WHEN NOT(address_counter = "1111" AND AHB_Master_In.HREADY = '1') ELSE '0'; - AHB_Master_Out.HLOCK <= REQ_ON_GOING WHEN NOT(address_counter = "1111" AND AHB_Master_In.HREADY = '1') ELSE '0'; + --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE + -- '1' WHEN ctrl_window = '1' ELSE + -- '0'; + + --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE + -- '1' WHEN ctrl_window = '1' ELSE '0'; + ----------------------------------------------------------------------------- - AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00"; AHB_Master_Out.HWDATA <= ahbdrivedata(data); - ----------------------------------------------------------------------------- - -- REN GEN - ----------------------------------------------------------------------------- - ren <= NOT (AHB_Master_In.HREADY AND DATA_ON_GOING); - - ----------------------------------------------------------------------------- - -- ADDR GEN + --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY ); + --ren <= NOT beat; ----------------------------------------------------------------------------- PROCESS (clk, rstn) BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) + state <= IDLE; + done <= '0'; address_counter_reg <= (OTHERS => '0'); - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - IF DATA_ON_GOING = '0' THEN - address_counter_reg <= (OTHERS => '0'); - ELSE - address_counter_reg <= address_counter; - END IF; - END IF; - END PROCESS; - - --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN AHB_Master_In.HGRANT(hindex) = '1' AND REQ_ON_GOING = '1' AND AHB_Master_In.HREADY = '1' ELSE - -- address_counter_reg; - address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN DATA_ON_GOING = '1' AND AHB_Master_In.HREADY = '1' ELSE - address_counter_reg; - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - REQ_ON_GOING <= '0'; - done <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + AHB_Master_Out.HBUSREQ <= '0'; + AHB_Master_Out.HLOCK <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge done <= '0'; - IF send = '1' THEN --send = '1' THEN - REQ_ON_GOING <= '1'; - ELSE - IF address_counter = "1111" AND AHB_Master_In.HREADY = '1' THEN - REQ_ON_GOING <= '0'; - done <= '1'; - END IF; - END IF; + CASE state IS + WHEN IDLE => + AHB_Master_Out.HBUSREQ <= '0'; + AHB_Master_Out.HLOCK <= '0'; + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + address_counter_reg <= (OTHERS => '0'); + IF send = '1' THEN + AHB_Master_Out.HBUSREQ <= '1'; + AHB_Master_Out.HLOCK <= '1'; + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + state <= s_ARBITER; + END IF; + + WHEN s_ARBITER => + AHB_Master_Out.HBUSREQ <= '1'; + AHB_Master_Out.HLOCK <= '1'; + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + address_counter_reg <= (OTHERS => '0'); + + IF AHB_Master_In.HGRANT(hindex) = '1' THEN + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + state <= s_CTRL; + END IF; + + WHEN s_CTRL => + AHB_Master_Out.HBUSREQ <= '1'; + AHB_Master_Out.HLOCK <= '1'; + AHB_Master_Out.HTRANS <= HTRANS_NONSEQ; + IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN + AHB_Master_Out.HTRANS <= HTRANS_SEQ; + state <= s_CTRL_DATA; + END IF; + + WHEN s_CTRL_DATA => + AHB_Master_Out.HBUSREQ <= '1'; + AHB_Master_Out.HLOCK <= '1'; + AHB_Master_Out.HTRANS <= HTRANS_SEQ; + IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN + address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1); + END IF; + + IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN + AHB_Master_Out.HBUSREQ <= '0'; + AHB_Master_Out.HLOCK <= '1';--'0'; + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + state <= s_DATA; + END IF; + + WHEN s_DATA => + AHB_Master_Out.HBUSREQ <= '0'; + AHB_Master_Out.HLOCK <= '0'; + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + IF AHB_Master_In.HREADY = '1' THEN + state <= IDLE; + done <= '1'; + END IF; + + WHEN OTHERS => NULL; + END CASE; END IF; END PROCESS; + ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0'; + data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0'; ----------------------------------------------------------------------------- - -- + ren <= NOT( data_window AND AHB_Master_In.HREADY); + ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - DATA_ON_GOING <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - IF REQ_ON_GOING = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN - DATA_ON_GOING <= '1'; - ELSE - IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN - DATA_ON_GOING <= '0'; - END IF; --- DATA_ON_GOING_s <= REQ_ON_GOING ; - END IF; - END IF; - END PROCESS; - --DATA_ON_GOING <= DATA_ON_GOING_s AND REQ_ON_GOING; - + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- address_counter_reg <= (OTHERS => '0'); + -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- address_counter_reg <= address_counter; + -- END IF; + --END PROCESS; + + --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE + -- address_counter_reg; + ----------------------------------------------------------------------------- + END Behavioral; diff --git a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd --- a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd +++ b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd @@ -364,11 +364,11 @@ BEGIN dsugen : IF CFG_DSU = 1 GENERATE dsu0 : dsu3 -- LEON3 Debug Support Unit - GENERIC MAP (hindex => 2, -- TODO : hindex => 2 + GENERIC MAP (hindex => 0, -- TODO : hindex => 2 haddr => 16#900#, hmask => 16#F00#, ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2),-- TODO :ahbso(2) + PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),-- TODO :ahbso(2) dbgo, dbgi, dsui, dsuo); dsui.enable <= '1'; dsui.break <= '0';