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custom dma ready to test on board
pellion -
r576:4347a39d5ac8 simu_double_DMA
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@@ -45,8 +45,8 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 --library proasic3l;
48 library proasic3l;
49 --use proasic3l.all;
49 use proasic3l.all;
50
50
51 ENTITY LFR_EQM IS
51 ENTITY LFR_EQM IS
52 --GENERIC (
52 --GENERIC (
@@ -64,7 +64,7 ENTITY LFR_EQM IS
64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
66 -- RAM --------------------------------------------------------------------
66 -- RAM --------------------------------------------------------------------
67 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
67 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69
69
70 nSRAM_MBE : INOUT STD_LOGIC; -- new
70 nSRAM_MBE : INOUT STD_LOGIC; -- new
@@ -217,8 +217,8 BEGIN -- beh
217 NB_AHB_MASTER => NB_AHB_MASTER,
217 NB_AHB_MASTER => NB_AHB_MASTER,
218 NB_AHB_SLAVE => NB_AHB_SLAVE,
218 NB_AHB_SLAVE => NB_AHB_SLAVE,
219 NB_APB_SLAVE => NB_APB_SLAVE,
219 NB_APB_SLAVE => NB_APB_SLAVE,
220 ADDRESS_SIZE => 20,
220 ADDRESS_SIZE => 19,
221 USES_IAP_MEMCTRLR => 0,
221 USES_IAP_MEMCTRLR => 1,
222 BYPASS_EDAC_MEMCTRLR => '0',
222 BYPASS_EDAC_MEMCTRLR => '0',
223 SRBANKSZ => 8)
223 SRBANKSZ => 8)
224 PORT MAP (
224 PORT MAP (
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@@ -1,4 +1,3
1
2 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
@@ -75,17 +74,17 ARCHITECTURE Behavioral OF lpp_dma_SEND1
75 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
76 OTHERS => (OTHERS => '0'));
75 OTHERS => (OTHERS => '0'));
77
76
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
78 SIGNAL state : AHB_DMA_FSM_STATE;
79
78 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
79 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
80
82
81 SIGNAL address_counter_reset : STD_LOGIC;
83 SIGNAL data_window : STD_LOGIC;
82 SIGNAL address_counter_add1 : STD_LOGIC;
84 SIGNAL ctrl_window : STD_LOGIC;
83
85
84 SIGNAL REQ_ON_GOING : STD_LOGIC;
86 SIGNAL bus_request : STD_LOGIC;
85 SIGNAL DATA_ON_GOING : STD_LOGIC;
87 SIGNAL bus_lock : STD_LOGIC;
86 SIGNAL DATA_ON_GOING_s : STD_LOGIC;
87 SIGNAL TRANSACTION_ON_GOING : STD_LOGIC;
88 SIGNAL internal_send : STD_LOGIC;
89
88
90 BEGIN
89 BEGIN
91
90
@@ -95,84 +94,120 BEGIN
95 AHB_Master_Out.HINDEX <= hindex;
94 AHB_Master_Out.HINDEX <= hindex;
96 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
95 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
97 AHB_Master_Out.HIRQ <= (OTHERS => '0');
96 AHB_Master_Out.HIRQ <= (OTHERS => '0');
98 AHB_Master_Out.HBURST <= "001"; -- INCR --"111"; --INCR16
97 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
99 AHB_Master_Out.HWRITE <= '1';
98 AHB_Master_Out.HWRITE <= '1';
100 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
99
100 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
101
102 --AHB_Master_Out.HBUSREQ <= bus_request;
103 --AHB_Master_Out.HLOCK <= data_window;
101
104
102 AHB_Master_Out.HBUSREQ <= REQ_ON_GOING WHEN NOT(address_counter = "1111" AND AHB_Master_In.HREADY = '1') ELSE '0';
105 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
103 AHB_Master_Out.HLOCK <= REQ_ON_GOING WHEN NOT(address_counter = "1111" AND AHB_Master_In.HREADY = '1') ELSE '0';
106 -- '1' WHEN ctrl_window = '1' ELSE
107 -- '0';
108
109 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
110 -- '1' WHEN ctrl_window = '1' ELSE '0';
111
104 -----------------------------------------------------------------------------
112 -----------------------------------------------------------------------------
105
106 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
113 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
107 AHB_Master_Out.HWDATA <= ahbdrivedata(data);
114 AHB_Master_Out.HWDATA <= ahbdrivedata(data);
108
115
109
110 -----------------------------------------------------------------------------
116 -----------------------------------------------------------------------------
111 -- REN GEN
117 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
112 -----------------------------------------------------------------------------
118 --ren <= NOT beat;
113 ren <= NOT (AHB_Master_In.HREADY AND DATA_ON_GOING);
114
115 -----------------------------------------------------------------------------
116 -- ADDR GEN
117 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
118 PROCESS (clk, rstn)
120 PROCESS (clk, rstn)
119 BEGIN -- PROCESS
121 BEGIN -- PROCESS
120 IF rstn = '0' THEN -- asynchronous reset (active low)
122 IF rstn = '0' THEN -- asynchronous reset (active low)
123 state <= IDLE;
124 done <= '0';
121 address_counter_reg <= (OTHERS => '0');
125 address_counter_reg <= (OTHERS => '0');
122 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
126 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
123 IF DATA_ON_GOING = '0' THEN
127 AHB_Master_Out.HBUSREQ <= '0';
124 address_counter_reg <= (OTHERS => '0');
128 AHB_Master_Out.HLOCK <= '0';
125 ELSE
129 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
126 address_counter_reg <= address_counter;
127 END IF;
128 END IF;
129 END PROCESS;
130
131 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN AHB_Master_In.HGRANT(hindex) = '1' AND REQ_ON_GOING = '1' AND AHB_Master_In.HREADY = '1' ELSE
132 -- address_counter_reg;
133 address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN DATA_ON_GOING = '1' AND AHB_Master_In.HREADY = '1' ELSE
134 address_counter_reg;
135
136 -----------------------------------------------------------------------------
137 --
138 -----------------------------------------------------------------------------
139 PROCESS (clk, rstn)
140 BEGIN -- PROCESS
141 IF rstn = '0' THEN -- asynchronous reset (active low)
142 REQ_ON_GOING <= '0';
143 done <= '0';
144 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
145 done <= '0';
130 done <= '0';
146 IF send = '1' THEN --send = '1' THEN
131 CASE state IS
147 REQ_ON_GOING <= '1';
132 WHEN IDLE =>
148 ELSE
133 AHB_Master_Out.HBUSREQ <= '0';
149 IF address_counter = "1111" AND AHB_Master_In.HREADY = '1' THEN
134 AHB_Master_Out.HLOCK <= '0';
150 REQ_ON_GOING <= '0';
135 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
151 done <= '1';
136 address_counter_reg <= (OTHERS => '0');
152 END IF;
137 IF send = '1' THEN
153 END IF;
138 AHB_Master_Out.HBUSREQ <= '1';
139 AHB_Master_Out.HLOCK <= '1';
140 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
141 state <= s_ARBITER;
142 END IF;
143
144 WHEN s_ARBITER =>
145 AHB_Master_Out.HBUSREQ <= '1';
146 AHB_Master_Out.HLOCK <= '1';
147 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
148 address_counter_reg <= (OTHERS => '0');
149
150 IF AHB_Master_In.HGRANT(hindex) = '1' THEN
151 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
152 state <= s_CTRL;
153 END IF;
154
155 WHEN s_CTRL =>
156 AHB_Master_Out.HBUSREQ <= '1';
157 AHB_Master_Out.HLOCK <= '1';
158 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
159 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
160 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
161 state <= s_CTRL_DATA;
162 END IF;
163
164 WHEN s_CTRL_DATA =>
165 AHB_Master_Out.HBUSREQ <= '1';
166 AHB_Master_Out.HLOCK <= '1';
167 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
168 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
169 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
170 END IF;
171
172 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
173 AHB_Master_Out.HBUSREQ <= '0';
174 AHB_Master_Out.HLOCK <= '1';--'0';
175 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
176 state <= s_DATA;
177 END IF;
178
179 WHEN s_DATA =>
180 AHB_Master_Out.HBUSREQ <= '0';
181 AHB_Master_Out.HLOCK <= '0';
182 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
183 IF AHB_Master_In.HREADY = '1' THEN
184 state <= IDLE;
185 done <= '1';
186 END IF;
187
188 WHEN OTHERS => NULL;
189 END CASE;
154 END IF;
190 END IF;
155 END PROCESS;
191 END PROCESS;
156
192
193 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
194 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
157 -----------------------------------------------------------------------------
195 -----------------------------------------------------------------------------
158 --
196 ren <= NOT( data_window AND AHB_Master_In.HREADY);
197
159 -----------------------------------------------------------------------------
198 -----------------------------------------------------------------------------
160 PROCESS (clk, rstn)
199 --PROCESS (clk, rstn)
161 BEGIN -- PROCESS
200 --BEGIN -- PROCESS
162 IF rstn = '0' THEN -- asynchronous reset (active low)
201 -- IF rstn = '0' THEN -- asynchronous reset (active low)
163 DATA_ON_GOING <= '0';
202 -- address_counter_reg <= (OTHERS => '0');
164 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
203 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
165 IF REQ_ON_GOING = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
204 -- address_counter_reg <= address_counter;
166 DATA_ON_GOING <= '1';
205 -- END IF;
167 ELSE
206 --END PROCESS;
168 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
207
169 DATA_ON_GOING <= '0';
208 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
170 END IF;
209 -- address_counter_reg;
171 -- DATA_ON_GOING_s <= REQ_ON_GOING ;
210 -----------------------------------------------------------------------------
172 END IF;
211
173 END IF;
174 END PROCESS;
175 --DATA_ON_GOING <= DATA_ON_GOING_s AND REQ_ON_GOING;
176
177
212
178 END Behavioral;
213 END Behavioral;
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@@ -364,11 +364,11 BEGIN
364 dsugen : IF CFG_DSU = 1 GENERATE
364 dsugen : IF CFG_DSU = 1 GENERATE
365
365
366 dsu0 : dsu3 -- LEON3 Debug Support Unit
366 dsu0 : dsu3 -- LEON3 Debug Support Unit
367 GENERIC MAP (hindex => 2, -- TODO : hindex => 2
367 GENERIC MAP (hindex => 0, -- TODO : hindex => 2
368 haddr => 16#900#, hmask => 16#F00#,
368 haddr => 16#900#, hmask => 16#F00#,
369 ncpu => CFG_NCPU, tbits => 30, tech => memtech,
369 ncpu => CFG_NCPU, tbits => 30, tech => memtech,
370 irq => 0, kbytes => CFG_ATBSZ)
370 irq => 0, kbytes => CFG_ATBSZ)
371 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2),-- TODO :ahbso(2)
371 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),-- TODO :ahbso(2)
372 dbgo, dbgi, dsui, dsuo);
372 dbgo, dbgi, dsui, dsuo);
373 dsui.enable <= '1';
373 dsui.enable <= '1';
374 dsui.break <= '0';
374 dsui.break <= '0';
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