HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r388:3dbc90b2eccb

Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

pellion -

r388:3dbc90b2eccb JC

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r388:3dbc90b2eccb

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lib/lpp/lpp_top_lfr/lpp_lfr_ms_reg_head.vhd created 644 +68 0

@@ -0,0 +1,68
	1	LIBRARY ieee;
	2	USE ieee.std_logic_1164.ALL;
	3
	4	ENTITY lpp_lfr_ms_reg_head IS
	5
	6	PORT (
	7	clk : IN STD_LOGIC;
	8	rstn : IN STD_LOGIC;
	9
	10	in_wen : IN STD_LOGIC;
	11	in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
	12	in_full : IN STD_LOGIC;
	13	in_empty : IN STD_LOGIC;
	14
	15	out_wen : OUT STD_LOGIC;
	16	out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
	17	out_full : OUT STD_LOGIC
	18	);
	19
	20	END lpp_lfr_ms_reg_head;
	21
	22	ARCHITECTURE Beh OF lpp_lfr_ms_reg_head IS
	23	TYPE fsm_state_reg_head IS (REG_EMPTY, REG_FULL);
	24	SIGNAL fsm_state : fsm_state_reg_head;
	25
	26	SIGNAL reg_data : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
	27	SIGNAL out_wen_s : STD_LOGIC;
	28	BEGIN -- Beh
	29
	30	PROCESS (clk, rstn)
	31	BEGIN
	32	IF rstn = '0' THEN
	33	fsm_state <= REG_EMPTY;
	34	reg_data <= (OTHERS => '0');
	35	out_wen_s <= '1';
	36	ELSIF clk'event AND clk = '1' THEN
	37	out_wen_s <= '1';
	38
	39	CASE fsm_state IS
	40	WHEN REG_EMPTY =>
	41	reg_data <= in_data;
	42	IF in_wen = '0' AND in_full = '1' THEN
	43	fsm_state <= REG_FULL;
	44	END IF;
	45	WHEN REG_FULL =>
	46	IF in_empty = '1' THEN
	47	out_wen_s <= '0';
	48	IF in_wen = '0' THEN
	49	reg_data <= in_data;
	50	ELSE
	51	fsm_state <= REG_EMPTY;
	52	END IF;
	53	END IF;
	54	WHEN OTHERS => NULL;
	55	END CASE;
	56
	57	END IF;
	58	END PROCESS;
	59
	60	out_full <= '1' WHEN fsm_state = REG_FULL ELSE in_full;
	61
	62	out_data <= reg_data WHEN fsm_state = REG_FULL ELSE in_data;
	63
	64	out_wen <= '0' WHEN out_wen_s = '0' ELSE
	65	'1' WHEN fsm_state = REG_FULL ELSE
	66	in_wen;
	67
	68	END Beh;

designs/Validation_LFR_SpectralMatrix/Makefile +1 0

             VHDLIB=../..
             SCRIPTSDIR=$(VHDLIB)/scripts/
             GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
             TOP=TB
             CMD_VLIB=vlib
             CMD_VMAP=vmap
             CMD_VCOM=@vcom -quiet -93 -work
             ##################  project specific targets ##########################
             all:
             	@echo "make vsim"
             	@echo "make libs"
             	@echo "make clean"
             	@echo "make vcom_grlib vcom_lpp vcom_tb"
             run:
             	@vsim work.TB -do run.do
             #	@vsim work.TB
             #	@vsim lpp.lpp_lfr_ms
             vsim:   libs vcom run
             libs:
             	@$(CMD_VLIB) modelsim
             	@$(CMD_VMAP) modelsim modelsim
             	@$(CMD_VLIB) modelsim/techmap
             	@$(CMD_VMAP) techmap modelsim/techmap
             	@$(CMD_VLIB) modelsim/grlib
             	@$(CMD_VMAP) grlib modelsim/grlib
             	@$(CMD_VLIB) modelsim/gaisler
             	@$(CMD_VMAP) gaisler modelsim/gaisler
             	@$(CMD_VLIB) modelsim/work
             	@$(CMD_VMAP) work modelsim/work
             	@$(CMD_VLIB) modelsim/lpp
             	@$(CMD_VMAP) lpp modelsim/lpp
             	@echo "libs done"
             clean:
             	@rm -Rf modelsim
             	@rm -Rf modelsim.ini
             	@rm -Rf *~
             	@rm -Rf transcript
             	@rm -Rf wlft*
             	@rm -Rf *.wlf
             	@rm -Rf vish_stacktrace.vstf
             	@rm -Rf libs.do
             vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb
             vcom_tb:
             ##	$(CMD_VCOM) lpp  lpp_memory.vhd
             ##	$(CMD_VCOM) lpp  lppFIFOxN.vhd
             ##	$(CMD_VCOM) lpp  lpp_FIFO.vhd
             ##	$(CMD_VCOM) lpp  lpp_lfr_ms.vhd
             	$(CMD_VCOM) work TB.vhd
             	@echo "vcom done"
             vcom_grlib:
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd
             	@echo "vcom grlib done"
             vcom_gaisler:
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd
             # #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd
             # #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd
             # #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd
             ##	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd
             	@echo "vcom gaisler done"
             vcom_techmap:
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd
             	@echo "vcom techmap done"
             vcom_lpp:
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_memory.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lppFIFOxN.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_reg_head.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd
             	@echo "vcom lpp done"
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd
             # 	@echo "vcom lpp done"
             #include Makefile_vcom_lpp

designs/Validation_LFR_SpectralMatrix/wave.do +51 -21

@@ -1,44 +1,74
1	onerror {resume}	1	onerror {resume}
2	quietly WaveActivateNextPane {} 0	2	quietly WaveActivateNextPane {} 0
3	add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0)	3	add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0)
4	add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1)	4	add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1)
5	add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2)	5	add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2)
6	add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5)	6	add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5)
7	add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4)	7	add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4)
8	add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3)	8	add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3)
9	add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8)	9	add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8)
10	add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7)	10	add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7)
11	add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6)	11	add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6)
12	add wave -noupdate -group debug /tb/lpp_lfr_ms_1/debug_reg	12	add wave -noupdate -expand -group debug /tb/lpp_lfr_ms_1/debug_reg
13	add wave -noupdate -group debug /tb/lpp_lfr_apbreg_1/apbi	13	add wave -noupdate -expand -group debug /tb/lpp_lfr_apbreg_1/apbi
14	add wave -noupdate -group debug /tb/lpp_lfr_apbreg_1/apbo	14	add wave -noupdate -expand -group debug /tb/lpp_lfr_apbreg_1/apbo
15	add wave -noupdate -group debug /tb/ready_reg	15	add wave -noupdate -expand -group debug /tb/ready_reg
16	add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(0)	16	add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(0)
17	add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(1)	17	add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(1)
18	add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(2)	18	add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(2)
19	add wave -noupdate -~~expand~~ /tb/lpp_lfr_apbreg_1/debug_signal	19	add wave -noupdate /tb/lpp_lfr_apbreg_1/debug_signal
20	add wave -noupdate -expand -subitemconfig {/tb/lpp_lfr_ms_1/observation_vector_0(2) {-color Blue} /tb/lpp_lfr_ms_1/observation_vector_0(0) {-color Blue}} /tb/lpp_lfr_ms_1/observation_vector_0	20	add wave -noupdate -expand -subitemconfig {/tb/lpp_lfr_ms_1/observation_vector_0(2) {-color Blue -height 15} /tb/lpp_lfr_ms_1/observation_vector_0(0) {-color Blue -height 15}} /tb/lpp_lfr_ms_1/observation_vector_0
21	add wave -noupdate -expand /tb/lpp_lfr_ms_1/observation_vector_1	21	add wave -noupdate -expand /tb/lpp_lfr_ms_1/observation_vector_1
22	add wave -noupdate -divider {New Divider}	22	add wave -noupdate -divider {New Divider}
23	add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter	23	add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter
24	add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter_out	24	add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter_out
25	add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter_wait	25	add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter_wait
		26	add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_bad_component_error
		27	add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_buffer_full
		28	add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_input_fifo_write
		29	add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen
		30	add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren
		31	add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty
		32	add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full
		33	add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full
		34	add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onnewmatrix {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onerror {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.config_ms_run {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_error_bad_component_error {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 {-height 15 -radix hexadecimal}} /tb/lpp_lfr_apbreg_1/reg_sp
		35	add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/sample_valid
		36	add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_read
		37	add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/sample_data
		38	add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/sample_load
		39	add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_pong
		40	add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_data_im
		41	add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_data_re
		42	add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_data_valid
		43	add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_ready
		44	add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft
		45	add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel
		46	add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_wen
		47	add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_data
		48	add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_full
		49	add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_empty
		50	add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/fsm_state
		51	add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/reg_data
		52	add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen_s
		53	add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen
		54	add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_data
		55	add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_full
26	TreeUpdate [SetDefaultTree]	56	TreeUpdate [SetDefaultTree]
27	WaveRestoreCursors {{Cursor 1} {~~20859515887~~ ps} 0}	57	WaveRestoreCursors {{Cursor 1} {41374417240 ps} 0} {{Cursor 2} {62390873400 ps} 0}
28	configure wave -namecolwidth ~~253~~	58	configure wave -namecolwidth 419
29	configure wave -valuecolwidth 112	59	configure wave -valuecolwidth 112
30	configure wave -justifyvalue left	60	configure wave -justifyvalue left
31	configure wave -signalnamewidth 0	61	configure wave -signalnamewidth 0
32	configure wave -snapdistance 10	62	configure wave -snapdistance 10
33	configure wave -datasetprefix 0	63	configure wave -datasetprefix 0
34	configure wave -rowmargin 4	64	configure wave -rowmargin 4
35	configure wave -childrowmargin 2	65	configure wave -childrowmargin 2
36	configure wave -gridoffset 0	66	configure wave -gridoffset 0
37	configure wave -gridperiod 1	67	configure wave -gridperiod 1
38	configure wave -griddelta 40	68	configure wave -griddelta 40
39	configure wave -timeline 0	69	configure wave -timeline 0
40	configure wave -timelineunits ps	70	configure wave -timelineunits ps
41	update	71	update
42	WaveRestoreZoom {~~20840058904~~ ps} {~~20863099265~~ ps}	72	WaveRestoreZoom {62074549955 ps} {63157132736 ps}
43	bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0	73	bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
44	bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0	74	bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0

lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +29 -3

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.spectral_matrix_package.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_Header.ALL;
             USE lpp.lpp_matrix.ALL;
             USE lpp.lpp_matrix.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.lpp_fft.ALL;
             USE lpp.fft_components.ALL;
             ENTITY lpp_lfr_ms IS
               GENERIC (
                 Mem_use : INTEGER := use_RAM
                 );
               PORT (
                 clk  : IN STD_LOGIC;
                 rstn : IN STD_LOGIC;
                 ---------------------------------------------------------------------------
                 -- DATA INPUT
                 ---------------------------------------------------------------------------
                 -- TIME
                 coarse_time     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                 fine_time       : IN STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 sample_f0_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f1_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f2_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 -- DMA
                 ---------------------------------------------------------------------------
                 dma_addr        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 dma_data        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 dma_valid       : OUT STD_LOGIC;
                 dma_valid_burst : OUT STD_LOGIC;
                 dma_ren         : IN  STD_LOGIC;
                 dma_done        : IN  STD_LOGIC;
                 -- Reg out
                 ready_matrix_f0           : OUT STD_LOGIC;
                 ready_matrix_f1           : OUT STD_LOGIC;
                 ready_matrix_f2           : OUT STD_LOGIC;
                 error_bad_component_error : OUT STD_LOGIC;
                 error_buffer_full         : OUT STD_LOGIC;
                 error_input_fifo_write    : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --
                 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
                 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
                 -- Reg In
                 status_ready_matrix_f0 : IN STD_LOGIC;
                 status_ready_matrix_f1 : IN STD_LOGIC;
                 status_ready_matrix_f2 : IN STD_LOGIC;
                 config_active_interruption_onNewMatrix : IN STD_LOGIC;
                 config_active_interruption_onError     : IN STD_LOGIC;
                 addr_matrix_f0                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f1                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f2                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
                 );
             END;
             ARCHITECTURE Behavioral OF lpp_lfr_ms IS
               SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f0_A_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f0_B_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f1_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f2_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL error_wen_f0 : STD_LOGIC;
               SIGNAL error_wen_f1 : STD_LOGIC;
               SIGNAL error_wen_f2 : STD_LOGIC;
               SIGNAL one_sample_f1_full : STD_LOGIC;
               SIGNAL one_sample_f1_wen  : STD_LOGIC;
               SIGNAL one_sample_f2_full : STD_LOGIC;
               SIGNAL one_sample_f2_wen  : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- FSM / SWITCH SELECT CHANNEL
               -----------------------------------------------------------------------------
               TYPE   fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
               SIGNAL state_fsm_select_channel     : fsm_select_channel;
               SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
               SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- FSM LOAD FFT
               -----------------------------------------------------------------------------
               TYPE   fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
               SIGNAL state_fsm_load_FFT      : fsm_load_FFT;
               SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
               SIGNAL sample_ren_s   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_load    : STD_LOGIC;
               SIGNAL sample_valid   : STD_LOGIC;
               SIGNAL sample_valid_r : STD_LOGIC;
               SIGNAL sample_data    : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- FFT
               -----------------------------------------------------------------------------
               SIGNAL fft_read                 : STD_LOGIC;
               SIGNAL fft_pong                 : STD_LOGIC;
               SIGNAL fft_data_im              : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fft_data_re              : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fft_data_valid           : STD_LOGIC;
               SIGNAL fft_ready                : STD_LOGIC;
               -----------------------------------------------------------------------------
             --  SIGNAL fft_linker_ReUse    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               TYPE   fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
               SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
               SIGNAL current_fifo_load        : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL current_fifo_empty       : STD_LOGIC;
               SIGNAL current_fifo_locked      : STD_LOGIC;
               SIGNAL current_fifo_full        : STD_LOGIC;
               SIGNAL MEM_IN_SM_locked         : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
               SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
               SIGNAL MEM_IN_SM_Full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL SM_in_data      : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
               SIGNAL SM_in_ren       : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL SM_in_empty     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL SM_correlation_start     : STD_LOGIC;
               SIGNAL SM_correlation_auto      : STD_LOGIC;
               SIGNAL SM_correlation_done      : STD_LOGIC;
               SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
               SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
               SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
               SIGNAL SM_correlation_begin     : STD_LOGIC;
               SIGNAL MEM_OUT_SM_Full_s    : STD_LOGIC;
               SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Write_s   : STD_LOGIC;
               SIGNAL current_matrix_write      : STD_LOGIC;
               SIGNAL current_matrix_wait_empty : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL fifo_0_ready              : STD_LOGIC;
               SIGNAL fifo_1_ready              : STD_LOGIC;
               SIGNAL fifo_ongoing              : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_ren    : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_empty  : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_data   : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL MEM_OUT_SM_Write    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Read     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Data_in  : STD_LOGIC_VECTOR(63 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Full     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Empty    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- TIME REG & INFOs
               -----------------------------------------------------------------------------
               SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL f_empty       : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL f_empty_reg   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_reg_f    : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f1   : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f2   : STD_LOGIC_VECTOR(47 DOWNTO 0);
               --SIGNAL time_update_f0_A : STD_LOGIC;
               --SIGNAL time_update_f0_B : STD_LOGIC;
               --SIGNAL time_update_f1   : STD_LOGIC;
               --SIGNAL time_update_f2   : STD_LOGIC;
               --
               SIGNAL status_channel   : STD_LOGIC_VECTOR(49 DOWNTO 0);
               SIGNAL status_MS_input  : STD_LOGIC_VECTOR(49 DOWNTO 0);
               SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
               SIGNAL status_component_fifo_0     : STD_LOGIC_VECTOR(53 DOWNTO 0);
               SIGNAL status_component_fifo_1     : STD_LOGIC_VECTOR(53 DOWNTO 0);
               SIGNAL status_component_fifo_0_end : STD_LOGIC;
               SIGNAL status_component_fifo_1_end : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
               SIGNAL fft_ready_reg         : STD_LOGIC;
               SIGNAL fft_ready_rising_down : STD_LOGIC;
               SIGNAL sample_load_reg         : STD_LOGIC;
               SIGNAL sample_load_rising_down : STD_LOGIC;
+              -----------------------------------------------------------------------------
+              SIGNAL sample_f1_wen_head     : STD_LOGIC_VECTOR(4 DOWNTO 0);
+              SIGNAL sample_f1_wen_head_in  : STD_LOGIC;
+              SIGNAL sample_f1_wen_head_out : STD_LOGIC;
+              SIGNAL sample_f1_full_head_in : STD_LOGIC;
+              SIGNAL sample_f1_full_head_out : STD_LOGIC;
+              SIGNAL sample_f1_empty_head_in : STD_LOGIC;
+              SIGNAL sample_f1_wdata_head   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
             BEGIN
               error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
               switch_f0_inst : spectral_matrix_switch_f0
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   sample_wen => sample_f0_wen,
                   fifo_A_empty => sample_f0_A_empty,
                   fifo_A_full  => sample_f0_A_full,
                   fifo_A_wen   => sample_f0_A_wen,
                   fifo_B_empty => sample_f0_B_empty,
                   fifo_B_full  => sample_f0_B_full,
                   fifo_B_wen   => sample_f0_B_wen,
                   error_wen => error_wen_f0);       -- TODO
               -----------------------------------------------------------------------------
               -- FIFO IN
               -----------------------------------------------------------------------------
               lppFIFOxN_f0_a : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   wen   => sample_f0_A_wen,
                   wdata => sample_f0_wdata,
                   ren   => sample_f0_A_ren,
                   rdata => sample_f0_A_rdata,
                   empty       => sample_f0_A_empty,
                   full        => sample_f0_A_full,
                   almost_full => OPEN);
               lppFIFOxN_f0_b : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   wen         => sample_f0_B_wen,
                   wdata       => sample_f0_wdata,
                   ren         => sample_f0_B_ren,
                   rdata       => sample_f0_B_rdata,
                   empty       => sample_f0_B_empty,
                   full        => sample_f0_B_full,
                   almost_full => OPEN);
               -----------------------------------------------------------------------------
               -- sample_f1_wen   in
               -- sample_f1_wdata in
               -- sample_f1_full  OUT
+              sample_f1_wen_head_in   <= '0' WHEN sample_f1_wen   = "00000" ELSE '1';
+              sample_f1_full_head_in  <= '0' WHEN sample_f1_full  = "00000" ELSE '1';
+              sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
+              lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
+                PORT MAP (
+                  clk      => clk,
+                  rstn     => rstn,
+                  in_wen   => sample_f1_wen_head_in,
+                  in_data  => sample_f1_wdata,
+                  in_full  => sample_f1_full_head_in,
+                  in_empty => sample_f1_empty_head_in,
+                  out_wen  => sample_f1_wen_head_out,
+                  out_data => sample_f1_wdata_head,
+                  out_full => sample_f1_full_head_out);
+              sample_f1_wen_head    <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
               lppFIFOxN_f1 : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
-                  wen         => sample_f1_wen,
+                  wen         => sample_f1_wen_head,
-                  wdata       => sample_f1_wdata,
+                  wdata       => sample_f1_wdata_head,
                   ren         => sample_f1_ren,
                   rdata       => sample_f1_rdata,
                   empty       => sample_f1_empty,
                   full        => sample_f1_full,
                   almost_full => sample_f1_almost_full);
               one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   one_sample_f1_full <= '0';
                   error_wen_f1       <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
-                  IF sample_f1_full = "00000" THEN
+                  IF sample_f1_full_head_out = '0' THEN
                     one_sample_f1_full <= '0';
                   ELSE
                     one_sample_f1_full <= '1';
                   END IF;
                   error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               lppFIFOxN_f2 : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   wen         => sample_f2_wen,
                   wdata       => sample_f2_wdata,
                   ren         => sample_f2_ren,
                   rdata       => sample_f2_rdata,
                   empty       => sample_f2_empty,
                   full        => sample_f2_full,
                   almost_full => OPEN);
               one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   one_sample_f2_full <= '0';
                   error_wen_f2       <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF sample_f2_full = "00000" THEN
                     one_sample_f2_full <= '0';
                   ELSE
                     one_sample_f2_full <= '1';
                   END IF;
                   error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- FSM SELECT CHANNEL
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   state_fsm_select_channel <= IDLE;
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_select_channel IS
                     WHEN IDLE =>
                       IF sample_f1_full = "11111" THEN
                         state_fsm_select_channel <= SWITCH_F1;
                       ELSIF sample_f1_almost_full = "00000" THEN
                         IF sample_f0_A_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F0_A;
                         ELSIF sample_f0_B_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F0_B;
                         ELSIF sample_f2_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F2;
                         END IF;
                       END IF;
                     WHEN SWITCH_F0_A =>
                       IF sample_f0_A_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                       END IF;
                     WHEN SWITCH_F0_B =>
                       IF sample_f0_B_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                       END IF;
                     WHEN SWITCH_F1 =>
                       IF sample_f1_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                       END IF;
                     WHEN SWITCH_F2 =>
                       IF sample_f2_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   pre_state_fsm_select_channel <= IDLE;
                 ELSIF clk'EVENT AND clk = '1' THEN
                   pre_state_fsm_select_channel <= state_fsm_select_channel;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- SWITCH SELECT CHANNEL
               -----------------------------------------------------------------------------
               sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                               sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                               sample_f1_empty   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                               sample_f2_empty   WHEN state_fsm_select_channel = SWITCH_F2   ELSE
                               (OTHERS => '1');
               sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                              sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                              sample_f1_full   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                              sample_f2_full   WHEN state_fsm_select_channel = SWITCH_F2   ELSE
                              (OTHERS => '0');
               sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
                               sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
                               sample_f1_rdata   WHEN pre_state_fsm_select_channel = SWITCH_F1   ELSE
                               sample_f2_rdata;  -- WHEN state_fsm_select_channel = SWITCH_F2   ELSE
               sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
               sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
               sample_f1_ren   <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1   ELSE (OTHERS => '1');
               sample_f2_ren   <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2   ELSE (OTHERS => '1');
               status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                                 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                                 time_reg_f1 & "01"   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                                 time_reg_f2 & "10";  -- WHEN state_fsm_select_channel = SWITCH_F2
               -----------------------------------------------------------------------------
               -- FSM LOAD FFT
               -----------------------------------------------------------------------------
               sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
                             sample_ren_s    WHEN sample_load = '1' ELSE
                             (OTHERS => '1');
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   sample_ren_s       <= (OTHERS => '1');
                   state_fsm_load_FFT <= IDLE;
                   status_MS_input    <= (OTHERS => '0');
                   --next_state_fsm_load_FFT <= IDLE;
                   --sample_valid              <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_load_FFT IS
                     WHEN IDLE =>
                       --sample_valid <= '0';
                       sample_ren_s <= (OTHERS => '1');
                       IF sample_full = "11111" AND sample_load = '1' THEN
                         state_fsm_load_FFT <= FIFO_1;
                         status_MS_input    <= status_channel;
                       END IF;
                     WHEN FIFO_1 =>
                       sample_ren_s <= "1111" & NOT(sample_load);
                       IF sample_empty(0) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_2;
                       END IF;
                     WHEN FIFO_2 =>
                       sample_ren_s <= "111" & NOT(sample_load) & '1';
                       IF sample_empty(1) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_3;
                       END IF;
                     WHEN FIFO_3 =>
                       sample_ren_s <= "11" & NOT(sample_load) & "11";
                       IF sample_empty(2) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_4;
                       END IF;
                     WHEN FIFO_4 =>
                       sample_ren_s <= '1' & NOT(sample_load) & "111";
                       IF sample_empty(3) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_5;
                       END IF;
                     WHEN FIFO_5 =>
                       sample_ren_s <= NOT(sample_load) & "1111";
                       IF sample_empty(4) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= IDLE;
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   sample_valid_r          <= '0';
                   next_state_fsm_load_FFT <= IDLE;
                 ELSIF clk'EVENT AND clk = '1' THEN
                   next_state_fsm_load_FFT <= state_fsm_load_FFT;
                   IF sample_ren_s = "11111" THEN
                     sample_valid_r <= '0';
                   ELSE
                     sample_valid_r <= '1';
                   END IF;
                 END IF;
               END PROCESS;
               sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
               sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
                              sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
                              sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
                              sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
                              sample_rdata(16*5-1 DOWNTO 16*4);  --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
               -----------------------------------------------------------------------------
               -- FFT
               -----------------------------------------------------------------------------
               lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_valid   => sample_valid,
                   fft_read       => fft_read,
                   sample_data    => sample_data,
                   sample_load    => sample_load,
                   fft_pong       => fft_pong,
                   fft_data_im    => fft_data_im,
                   fft_data_re    => fft_data_re,
                   fft_data_valid => fft_data_valid,
                   fft_ready      => fft_ready);
               observation_vector_0(11 DOWNTO 0) <= "000" &                              --11 10
                                                    fft_ongoing_counter &               --9 8
                                                    sample_load_rising_down &           --7
                                                    fft_ready_rising_down &             --6
                                                    fft_ready &                         --5
                                                    fft_data_valid &                    --4
                                                    fft_pong &                          --3
                                                    sample_load &                       --2
                                                    fft_read &                          --1
                                                    sample_valid;                       --0
               -----------------------------------------------------------------------------
               fft_ready_rising_down   <= fft_ready_reg AND NOT fft_ready;
               sample_load_rising_down <= sample_load_reg AND NOT sample_load;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   fft_ready_reg     <= '0';
                   sample_load_reg   <= '0';
                   fft_ongoing_counter <= '0';
                 ELSIF clk'event AND clk = '1' THEN
                   fft_ready_reg    <= fft_ready;
                   sample_load_reg  <= sample_load;
                   IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
                     fft_ongoing_counter <= '0';
             --        CASE fft_ongoing_counter IS
             --          WHEN "01" => fft_ongoing_counter <= "00";
             ----          WHEN "10" => fft_ongoing_counter <= "01";
             --          WHEN OTHERS => NULL;
             --        END CASE;
                   ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
                     fft_ongoing_counter <= '1';
             --        CASE fft_ongoing_counter IS
             --          WHEN "00" => fft_ongoing_counter <= "01";
             ----          WHEN "01" => fft_ongoing_counter <= "10";
             --          WHEN OTHERS => NULL;
             --        END CASE;
                   END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   state_fsm_load_MS_memory <= IDLE;
                   current_fifo_load        <= "00001";
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_load_MS_memory IS
                     WHEN IDLE =>
                       IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
                         state_fsm_load_MS_memory <= LOAD_FIFO;
                       END IF;
                     WHEN LOAD_FIFO =>
                       IF current_fifo_full = '1' THEN
                         state_fsm_load_MS_memory <= TRASH_FFT;
                       END IF;
                     WHEN TRASH_FFT =>
                       IF fft_ready = '0' THEN
                         state_fsm_load_MS_memory <= IDLE;
                         current_fifo_load        <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
                                     MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
                                     MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
                                     MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
                                     MEM_IN_SM_Empty(4);  -- WHEN current_fifo_load(3) = '1' ELSE
               current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
                                    MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
                                    MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
                                    MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
                                    MEM_IN_SM_Full(4);  -- WHEN current_fifo_load(3) = '1' ELSE
               current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
                                      MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
                                      MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
                                      MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
                                      MEM_IN_SM_locked(4);  -- WHEN current_fifo_load(3) = '1' ELSE
               fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
               all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
                 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
                                       AND state_fsm_load_MS_memory = LOAD_FIFO
                                       AND current_fifo_load(I) = '1'
                                       ELSE '1';
               END GENERATE all_fifo;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   MEM_IN_SM_wen <= (OTHERS => '1');
                 ELSIF clk'EVENT AND clk = '1' THEN
                   MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
                 END IF;
               END PROCESS;
               MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               Mem_In_SpectralMatrix : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 32,                    --16,
                   Addr_sz => 7,                     --8
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => MEM_IN_SM_ReUse,
                   wen   => MEM_IN_SM_wen,
                   wdata => MEM_IN_SM_wData,
                   ren         => MEM_IN_SM_ren,
                   rdata       => MEM_IN_SM_rData,
                   full        => MEM_IN_SM_Full,
                   empty       => MEM_IN_SM_Empty,
                   almost_full => OPEN);
               -----------------------------------------------------------------------------
               observation_vector_1(11 DOWNTO 0) <= '0' &
                                                    SM_correlation_done      &               --4
                                                    SM_correlation_auto   &                --3
                                                    SM_correlation_start  &
                                                    SM_correlation_start &            --7
                                                    status_MS_input(1 DOWNTO 0)&     --6..5
                                                    MEM_IN_SM_locked(4 DOWNTO 0);    --4..0
               -----------------------------------------------------------------------------
               MS_control_1 : MS_control
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   current_status_ms => status_MS_input,
                   fifo_in_lock  => MEM_IN_SM_locked,
                   fifo_in_data  => MEM_IN_SM_rdata,
                   fifo_in_full  => MEM_IN_SM_Full,
                   fifo_in_empty => MEM_IN_SM_Empty,
                   fifo_in_ren   => MEM_IN_SM_ren,
                   fifo_in_reuse => MEM_IN_SM_ReUse,
                   fifo_out_data  => SM_in_data,
                   fifo_out_ren   => SM_in_ren,
                   fifo_out_empty => SM_in_empty,
                   current_status_component => status_component,
                   correlation_start => SM_correlation_start,
                   correlation_auto  => SM_correlation_auto,
                   correlation_done  => SM_correlation_done);
               MS_calculation_1 : MS_calculation
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   fifo_in_data  => SM_in_data,
                   fifo_in_ren   => SM_in_ren,
                   fifo_in_empty => SM_in_empty,
                   fifo_out_data => MEM_OUT_SM_Data_in_s,  --    TODO
                   fifo_out_wen  => MEM_OUT_SM_Write_s,    --      TODO
                   fifo_out_full => MEM_OUT_SM_Full_s,     --       TODO
                   correlation_start => SM_correlation_start,
                   correlation_auto  => SM_correlation_auto,
                   correlation_begin => SM_correlation_begin,
                   correlation_done  => SM_correlation_done);
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   current_matrix_write        <= '0';
                   current_matrix_wait_empty   <= '1';
                   status_component_fifo_0     <= (OTHERS => '0');
                   status_component_fifo_1     <= (OTHERS => '0');
                   status_component_fifo_0_end <= '0';
                   status_component_fifo_1_end <= '0';
                   SM_correlation_done_reg1    <= '0';
                   SM_correlation_done_reg2    <= '0';
                   SM_correlation_done_reg3    <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   SM_correlation_done_reg1    <= SM_correlation_done;
                   SM_correlation_done_reg2    <= SM_correlation_done_reg1;
                   SM_correlation_done_reg3    <= SM_correlation_done_reg2;
                   status_component_fifo_0_end <= '0';
                   status_component_fifo_1_end <= '0';
                   IF SM_correlation_begin = '1' THEN
                     IF current_matrix_write = '0' THEN
                       status_component_fifo_0 <= status_component;
                     ELSE
                       status_component_fifo_1 <= status_component;
                     END IF;
                   END IF;
                   IF SM_correlation_done_reg3 = '1' THEN
                     IF current_matrix_write = '0' THEN
                       status_component_fifo_0_end <= '1';
                     ELSE
                       status_component_fifo_1_end <= '1';
                     END IF;
                     current_matrix_wait_empty <= '1';
                     current_matrix_write      <= NOT current_matrix_write;
                   END IF;
                   IF current_matrix_wait_empty <= '1' THEN
                     IF current_matrix_write = '0' THEN
                       current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
                     ELSE
                       current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
                                    '1'                WHEN SM_correlation_done_reg1 = '1'  ELSE
                                    '1'                WHEN SM_correlation_done_reg2 = '1'  ELSE
                                    '1'                WHEN SM_correlation_done_reg3 = '1'  ELSE
                                    '1'                WHEN current_matrix_wait_empty = '1' ELSE
                                    MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0'      ELSE
                                    MEM_OUT_SM_Full(1);
               MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
               MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
               MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
               -----------------------------------------------------------------------------
               Mem_Out_SpectralMatrix : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 32,
                   Addr_sz => 8,
                   FifoCnt => 2)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   wen   => MEM_OUT_SM_Write,
                   wdata => MEM_OUT_SM_Data_in,
                   ren   => MEM_OUT_SM_Read,
                   rdata => MEM_OUT_SM_Data_out,
                   full        => MEM_OUT_SM_Full,
                   empty       => MEM_OUT_SM_Empty,
                   almost_full => OPEN);
               -----------------------------------------------------------------------------
             --  MEM_OUT_SM_Read <= "00";
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   fifo_0_ready <= '0';
                   fifo_1_ready <= '0';
                   fifo_ongoing <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
                     fifo_ongoing <= '1';
                     fifo_0_ready <= '0';
                   ELSIF status_component_fifo_0_end = '1' THEN
                     fifo_0_ready <= '1';
                   END IF;
                   IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
                     fifo_ongoing <= '0';
                     fifo_1_ready <= '0';
                   ELSIF status_component_fifo_1_end = '1' THEN
                     fifo_1_ready <= '1';
                   END IF;
                 END IF;
               END PROCESS;
               MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
                                     '1' WHEN fifo_0_ready = '0' ELSE
                                     FSM_DMA_fifo_ren;
               MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
                                     '1' WHEN fifo_1_ready = '0' ELSE
                                     FSM_DMA_fifo_ren;
               FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
                                     MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
                                     '1';
               FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
                                      status_component_fifo_1;
               FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
                                    MEM_OUT_SM_Data_out(63 DOWNTO 32);
               -----------------------------------------------------------------------------
               lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
                 PORT MAP (
                   HCLK    => clk,
                   HRESETn => rstn,
                   fifo_matrix_type      => FSM_DMA_fifo_status(5 DOWNTO 4),
                   fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
                   fifo_matrix_time      => FSM_DMA_fifo_status(53 DOWNTO 6),
                   fifo_data             => FSM_DMA_fifo_data,
                   fifo_empty            => FSM_DMA_fifo_empty,
                   fifo_ren              => FSM_DMA_fifo_ren,
                   dma_addr        => dma_addr,
                   dma_data        => dma_data,
                   dma_valid       => dma_valid,
                   dma_valid_burst => dma_valid_burst,
                   dma_ren         => dma_ren,
                   dma_done        => dma_done,
                   ready_matrix_f0 => ready_matrix_f0,
                   ready_matrix_f1 => ready_matrix_f1,
                   ready_matrix_f2 => ready_matrix_f2,
                   error_bad_component_error => error_bad_component_error,
                   error_buffer_full         => error_buffer_full,
                   debug_reg              => debug_reg,
                   status_ready_matrix_f0 => status_ready_matrix_f0,
                   status_ready_matrix_f1 => status_ready_matrix_f1,
                   status_ready_matrix_f2 => status_ready_matrix_f2,
                   config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
                   config_active_interruption_onError     => config_active_interruption_onError,
                   addr_matrix_f0 => addr_matrix_f0,
                   addr_matrix_f1 => addr_matrix_f1,
                   addr_matrix_f2 => addr_matrix_f2,
                   matrix_time_f0 => matrix_time_f0,
                   matrix_time_f1 => matrix_time_f1,
                   matrix_time_f2 => matrix_time_f2
                   );
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- TIME MANAGMENT
               -----------------------------------------------------------------------------
               all_time         <= coarse_time & fine_time;
               --
               f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
               f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
               f_empty(2) <= '1' WHEN sample_f1_empty   = "11111" ELSE '0';
               f_empty(3) <= '1' WHEN sample_f2_empty   = "11111" ELSE '0';
               all_time_reg: FOR I IN 0 TO 3 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN
                   IF rstn = '0' THEN
                     f_empty_reg(I) <= '1';
                   ELSIF clk'event AND clk = '1' THEN
                     f_empty_reg(I) <= f_empty(I);
                   END IF;
                 END PROCESS;
                 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
                 s_m_t_m_f0_A : spectral_matrix_time_managment
                   PORT MAP (
                     clk      => clk,
                     rstn     => rstn,
                     time_in  => all_time,
                     update_1 => time_update_f(I),
                     time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
                     );
               END GENERATE all_time_reg;
               time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
               time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
               time_reg_f1   <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
               time_reg_f2   <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
               -----------------------------------------------------------------------------
             END Behavioral;

lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +13 0

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             PACKAGE lpp_lfr_pkg IS
               -----------------------------------------------------------------------------
               -- TEMP
               -----------------------------------------------------------------------------
               COMPONENT lpp_lfr_ms_test
                 GENERIC (
                   Mem_use : INTEGER);
                 PORT (
                   clk              : IN  STD_LOGIC;
                   rstn             : IN  STD_LOGIC;
                 -- TIME
                 coarse_time     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                 fine_time       : IN STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 sample_f0_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f1_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f2_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 error_input_fifo_write        : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                 --
                 --sample_ren   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 --sample_full  : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 --sample_empty : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
                 -- IN
                 MEM_IN_SM_locked      : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 -----------------------------------------------------------------------------
                 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
                 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
                 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
                 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
                 SM_correlation_start : OUT STD_LOGIC;
                 SM_correlation_auto : OUT STD_LOGIC;
                 SM_correlation_done : IN STD_LOGIC
                 );
               END COMPONENT;
               -----------------------------------------------------------------------------
               COMPONENT lpp_lfr_ms
                 GENERIC (
                   Mem_use : INTEGER
                   );
                 PORT (
                   clk                                    : IN  STD_LOGIC;
                   rstn                                   : IN  STD_LOGIC;
                   coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                   fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                   sample_f0_wen                          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f0_wdata                        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                   sample_f1_wen                          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f1_wdata                        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                   sample_f2_wen                          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f2_wdata                        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                   dma_addr        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_data        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_valid       : OUT STD_LOGIC;
                   dma_valid_burst : OUT STD_LOGIC;
                   dma_ren         : IN STD_LOGIC;
                   dma_done        : IN STD_LOGIC;
                   ready_matrix_f0                      : OUT STD_LOGIC;
             --      ready_matrix_f0_1                      : OUT STD_LOGIC;
                   ready_matrix_f1                        : OUT STD_LOGIC;
                   ready_matrix_f2                        : OUT STD_LOGIC;
             --      error_anticipating_empty_fifo          : OUT STD_LOGIC;
                   error_bad_component_error              : OUT STD_LOGIC;
                   error_buffer_full                      : OUT STD_LOGIC;
                   error_input_fifo_write                 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                   debug_reg                              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   --
                   observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
                   observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
                   -------------------------------------------------------------------------
                   status_ready_matrix_f0               : IN  STD_LOGIC;
             --      status_ready_matrix_f0_1               : IN  STD_LOGIC;
                   status_ready_matrix_f1                 : IN  STD_LOGIC;
                   status_ready_matrix_f2                 : IN  STD_LOGIC;
             --      status_error_anticipating_empty_fifo   : IN  STD_LOGIC;
             --      status_error_bad_component_error       : IN  STD_LOGIC;
                   config_active_interruption_onNewMatrix : IN  STD_LOGIC;
                   config_active_interruption_onError     : IN  STD_LOGIC;
                   addr_matrix_f0                       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
             --      addr_matrix_f0_1                       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1                         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2                         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   matrix_time_f0                       : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
             --      matrix_time_f0_1                       : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1                         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2                         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_lfr_ms_fsmdma
                 PORT (
                   HCLK                                   : IN  STD_ULOGIC;
                   HRESETn                                : IN  STD_ULOGIC;
                   fifo_matrix_type      : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
                   fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                   fifo_matrix_time      : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                   fifo_data  : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty : IN  STD_LOGIC;
                   fifo_ren   : OUT STD_LOGIC;
                   --data_time                              : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                   --fifo_data                              : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   --fifo_empty                             : IN  STD_LOGIC;
                   --fifo_ren                               : OUT STD_LOGIC;
                   --header                                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   --header_val                             : IN  STD_LOGIC;
                   --header_ack                             : OUT STD_LOGIC;
                   dma_addr                               : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_data                               : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_valid                              : OUT STD_LOGIC;
                   dma_valid_burst                        : OUT STD_LOGIC;
                   dma_ren                                : IN  STD_LOGIC;
                   dma_done                               : IN  STD_LOGIC;
                   ready_matrix_f0                      : OUT STD_LOGIC;
             --      ready_matrix_f0_1                      : OUT STD_LOGIC;
                   ready_matrix_f1                        : OUT STD_LOGIC;
                   ready_matrix_f2                        : OUT STD_LOGIC;
             --      error_anticipating_empty_fifo          : OUT STD_LOGIC;
                   error_bad_component_error              : OUT STD_LOGIC;
                   error_buffer_full                      : OUT STD_LOGIC;
                   debug_reg                              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   status_ready_matrix_f0               : IN  STD_LOGIC;
             --      status_ready_matrix_f0_1               : IN  STD_LOGIC;
                   status_ready_matrix_f1                 : IN  STD_LOGIC;
                   status_ready_matrix_f2                 : IN  STD_LOGIC;
             --      status_error_anticipating_empty_fifo   : IN  STD_LOGIC;
             --      status_error_bad_component_error       : IN  STD_LOGIC;
                   config_active_interruption_onNewMatrix : IN  STD_LOGIC;
                   config_active_interruption_onError     : IN  STD_LOGIC;
                   addr_matrix_f0                       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
             --      addr_matrix_f0_1                       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1                         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2                         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   matrix_time_f0                       : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
             --      matrix_time_f0_1                       : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1                         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2                         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT lpp_lfr_ms_FFT
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   sample_valid   : IN  STD_LOGIC;
                   fft_read       : IN  STD_LOGIC;
                   sample_data    : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   sample_load    : OUT STD_LOGIC;
                   fft_pong       : OUT STD_LOGIC;
                   fft_data_im    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                   fft_data_re    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                   fft_data_valid : OUT STD_LOGIC;
                   fft_ready      : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_lfr_filter
                 GENERIC (
                   Mem_use : INTEGER);
                 PORT (
                   sample           : IN  Samples(7 DOWNTO 0);
                   sample_val       : IN  STD_LOGIC;
                   clk              : IN  STD_LOGIC;
                   rstn             : IN  STD_LOGIC;
                   data_shaping_SP0 : IN  STD_LOGIC;
                   data_shaping_SP1 : IN  STD_LOGIC;
                   data_shaping_R0  : IN  STD_LOGIC;
                   data_shaping_R1  : IN  STD_LOGIC;
                   sample_f0_val    : OUT STD_LOGIC;
                   sample_f1_val    : OUT STD_LOGIC;
                   sample_f2_val    : OUT STD_LOGIC;
                   sample_f3_val    : OUT STD_LOGIC;
                   sample_f0_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f1_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f2_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f3_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_lfr
                 GENERIC (
                   Mem_use                : INTEGER;
                   nb_data_by_buffer_size : INTEGER;
                   nb_word_by_buffer_size : INTEGER;
                   nb_snapshot_param_size : INTEGER;
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER;
                   pindex                 : INTEGER;
                   paddr                  : INTEGER;
                   pmask                  : INTEGER;
                   pirq_ms                : INTEGER;
                   pirq_wfp               : INTEGER;
                   hindex                 : INTEGER;
                   top_lfr_version        : STD_LOGIC_VECTOR(23 DOWNTO 0)
                   );
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   sample_B        : IN  Samples(2 DOWNTO 0);
                   sample_E        : IN  Samples(4 DOWNTO 0);
                   sample_val      : IN  STD_LOGIC;
                   apbi            : IN  apb_slv_in_type;
                   apbo            : OUT apb_slv_out_type;
                   ahbi            : IN  AHB_Mst_In_Type;
                   ahbo            : OUT AHB_Mst_Out_Type;
                   coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   data_shaping_BW : OUT STD_LOGIC;
                   --
                   observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
                   observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
                   observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                   );
               END COMPONENT;
               -----------------------------------------------------------------------------
               -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
               -----------------------------------------------------------------------------
               COMPONENT lpp_lfr_WFP_nMS
                 GENERIC (
                   Mem_use                : INTEGER;
                   nb_data_by_buffer_size : INTEGER;
                   nb_word_by_buffer_size : INTEGER;
                   nb_snapshot_param_size : INTEGER;
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER;
                   pindex                 : INTEGER;
                   paddr                  : INTEGER;
                   pmask                  : INTEGER;
                   pirq_ms                : INTEGER;
                   pirq_wfp               : INTEGER;
                   hindex                 : INTEGER;
                   top_lfr_version        : STD_LOGIC_VECTOR(23 DOWNTO 0));
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   sample_B        : IN  Samples(2 DOWNTO 0);
                   sample_E        : IN  Samples(4 DOWNTO 0);
                   sample_val      : IN  STD_LOGIC;
                   apbi            : IN  apb_slv_in_type;
                   apbo            : OUT apb_slv_out_type;
                   ahbi            : IN  AHB_Mst_In_Type;
                   ahbo            : OUT AHB_Mst_Out_Type;
                   coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   data_shaping_BW : OUT STD_LOGIC;
                   observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               -----------------------------------------------------------------------------
               COMPONENT lpp_lfr_apbreg
                 GENERIC (
                   nb_data_by_buffer_size : INTEGER;
                   nb_word_by_buffer_size : INTEGER;
                   nb_snapshot_param_size : INTEGER;
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER;
                   pindex                 : INTEGER;
                   paddr                  : INTEGER;
                   pmask                  : INTEGER;
                   pirq_ms                : INTEGER;
                   pirq_wfp               : INTEGER;
                   top_lfr_version        : STD_LOGIC_VECTOR(23 DOWNTO 0));
                 PORT (
                   HCLK                                   : IN  STD_ULOGIC;
                   HRESETn                                : IN  STD_ULOGIC;
                   apbi                                   : IN  apb_slv_in_type;
                   apbo                                   : OUT apb_slv_out_type;
                   run_ms                                 : OUT STD_LOGIC;
                   ready_matrix_f0                      : IN  STD_LOGIC;
                   ready_matrix_f1                        : IN  STD_LOGIC;
                   ready_matrix_f2                        : IN  STD_LOGIC;
                   error_bad_component_error              : IN  STD_LOGIC;
                   error_buffer_full                      : in  STD_LOGIC;
                   error_input_fifo_write                 : in  STD_LOGIC_VECTOR(2 DOWNTO 0);
             --x      debug_reg                              : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   status_ready_matrix_f0               : OUT STD_LOGIC;
                   status_ready_matrix_f1                 : OUT STD_LOGIC;
                   status_ready_matrix_f2                 : OUT STD_LOGIC;
                   config_active_interruption_onNewMatrix : OUT STD_LOGIC;
                   config_active_interruption_onError     : OUT STD_LOGIC;
                   addr_matrix_f0                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
             --      addr_matrix_f0_1                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   matrix_time_f0                       : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
             --      matrix_time_f0_1                       : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1                         : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2                         : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   status_full                            : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_ack                        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_err                        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_new_err                         : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_shaping_BW                        : OUT STD_LOGIC;
                   data_shaping_SP0                       : OUT STD_LOGIC;
                   data_shaping_SP1                       : OUT STD_LOGIC;
                   data_shaping_R0                        : OUT STD_LOGIC;
                   data_shaping_R1                        : OUT STD_LOGIC;
                   delta_snapshot                         : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   delta_f0                               : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   delta_f0_2                             : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
                   delta_f1                               : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   delta_f2                               : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   nb_data_by_buffer                      : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
                   nb_word_by_buffer                      : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
                   nb_snapshot_param                      : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                   enable_f0                              : OUT STD_LOGIC;
                   enable_f1                              : OUT STD_LOGIC;
                   enable_f2                              : OUT STD_LOGIC;
                   enable_f3                              : OUT STD_LOGIC;
                   burst_f0                               : OUT STD_LOGIC;
                   burst_f1                               : OUT STD_LOGIC;
                   burst_f2                               : OUT STD_LOGIC;
                   run                                    : OUT STD_LOGIC;
                   addr_data_f0                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f1                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f2                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f3                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   start_date                             : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
                   debug_signal                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT lpp_top_ms
                 GENERIC (
                   Mem_use                 : INTEGER;
                   nb_burst_available_size : INTEGER;
                   nb_snapshot_param_size  : INTEGER;
                   delta_snapshot_size     : INTEGER;
                   delta_f2_f0_size        : INTEGER;
                   delta_f2_f1_size        : INTEGER;
                   pindex                  : INTEGER;
                   paddr                   : INTEGER;
                   pmask                   : INTEGER;
                   pirq_ms                 : INTEGER;
                   pirq_wfp                : INTEGER;
                   hindex_wfp              : INTEGER;
                   hindex_ms               : INTEGER);
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   sample_B        : IN  Samples14v(2 DOWNTO 0);
                   sample_E        : IN  Samples14v(4 DOWNTO 0);
                   sample_val      : IN  STD_LOGIC;
                   apbi            : IN  apb_slv_in_type;
                   apbo            : OUT apb_slv_out_type;
                   ahbi_ms         : IN  AHB_Mst_In_Type;
                   ahbo_ms         : OUT AHB_Mst_Out_Type;
                   data_shaping_BW : OUT STD_LOGIC;
                   matrix_time_f0_0                       : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f0_1                       : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1                         : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2                         : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT lpp_apbreg_ms_pointer
                 PORT (
                   clk                      : IN  STD_LOGIC;
                   rstn                     : IN  STD_LOGIC;
                   reg0_status_ready_matrix : IN  STD_LOGIC;
                   reg0_ready_matrix        : OUT STD_LOGIC;
                   reg0_addr_matrix         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   reg0_matrix_time         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   reg1_status_ready_matrix : IN  STD_LOGIC;
                   reg1_ready_matrix        : OUT STD_LOGIC;
                   reg1_addr_matrix         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   reg1_matrix_time         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   ready_matrix             : IN  STD_LOGIC;
                   status_ready_matrix      : OUT STD_LOGIC;
                   addr_matrix              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   matrix_time              : IN  STD_LOGIC_VECTOR(47 DOWNTO 0));
               END COMPONENT;
+              COMPONENT lpp_lfr_ms_reg_head
+                PORT (
+                  clk      : IN  STD_LOGIC;
+                  rstn     : IN  STD_LOGIC;
+                  in_wen   : IN  STD_LOGIC;
+                  in_data  : IN  STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
+                  in_full  : IN  STD_LOGIC;
+                  in_empty : IN  STD_LOGIC;
+                  out_wen  : OUT STD_LOGIC;
+                  out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
+                  out_full : OUT STD_LOGIC);
+              END COMPONENT;
             END lpp_lfr_pkg;

lib/lpp/lpp_top_lfr/vhdlsyn.txt +1 0

             lpp_top_lfr_pkg.vhd
             lpp_lfr_pkg.vhd
             lpp_lfr_filter.vhd
             lpp_lfr_apbreg.vhd
             lpp_lfr_apbreg_ms_pointer.vhd
             lpp_lfr_ms_fsmdma.vhd
             lpp_lfr_ms_FFT.vhd
             lpp_lfr_ms.vhd
+            lpp_lfr_ms_reg_head.vhd
             lpp_lfr.vhd

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