##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Add HeadReg for input fifo channel f1 (lpp_lfr_ms)
pellion -
r388:3dbc90b2eccb JC
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,68
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY lpp_lfr_ms_reg_head IS
5
6 PORT (
7 clk : IN STD_LOGIC;
8 rstn : IN STD_LOGIC;
9
10 in_wen : IN STD_LOGIC;
11 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
12 in_full : IN STD_LOGIC;
13 in_empty : IN STD_LOGIC;
14
15 out_wen : OUT STD_LOGIC;
16 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
17 out_full : OUT STD_LOGIC
18 );
19
20 END lpp_lfr_ms_reg_head;
21
22 ARCHITECTURE Beh OF lpp_lfr_ms_reg_head IS
23 TYPE fsm_state_reg_head IS (REG_EMPTY, REG_FULL);
24 SIGNAL fsm_state : fsm_state_reg_head;
25
26 SIGNAL reg_data : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
27 SIGNAL out_wen_s : STD_LOGIC;
28 BEGIN -- Beh
29
30 PROCESS (clk, rstn)
31 BEGIN
32 IF rstn = '0' THEN
33 fsm_state <= REG_EMPTY;
34 reg_data <= (OTHERS => '0');
35 out_wen_s <= '1';
36 ELSIF clk'event AND clk = '1' THEN
37 out_wen_s <= '1';
38
39 CASE fsm_state IS
40 WHEN REG_EMPTY =>
41 reg_data <= in_data;
42 IF in_wen = '0' AND in_full = '1' THEN
43 fsm_state <= REG_FULL;
44 END IF;
45 WHEN REG_FULL =>
46 IF in_empty = '1' THEN
47 out_wen_s <= '0';
48 IF in_wen = '0' THEN
49 reg_data <= in_data;
50 ELSE
51 fsm_state <= REG_EMPTY;
52 END IF;
53 END IF;
54 WHEN OTHERS => NULL;
55 END CASE;
56
57 END IF;
58 END PROCESS;
59
60 out_full <= '1' WHEN fsm_state = REG_FULL ELSE in_full;
61
62 out_data <= reg_data WHEN fsm_state = REG_FULL ELSE in_data;
63
64 out_wen <= '0' WHEN out_wen_s = '0' ELSE
65 '1' WHEN fsm_state = REG_FULL ELSE
66 in_wen;
67
68 END Beh;
Show file before | Show file after | Hide comments
@@ -399,6 +399,7 vcom_lpp:
399 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd
399 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd
400 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd
400 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd
401 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
401 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
402 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_reg_head.vhd
402 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
403 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
403 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd
404 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd
404 @echo "vcom lpp done"
405 @echo "vcom lpp done"
Show file before | Show file after | Hide comments
@@ -1,31 +1,61
1 onerror {resume}
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0)
3 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0)
4 add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1)
4 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1)
5 add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2)
5 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2)
6 add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5)
6 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5)
7 add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4)
7 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4)
8 add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3)
8 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3)
9 add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8)
9 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8)
10 add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7)
10 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7)
11 add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6)
11 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6)
12 add wave -noupdate -group debug /tb/lpp_lfr_ms_1/debug_reg
12 add wave -noupdate -expand -group debug /tb/lpp_lfr_ms_1/debug_reg
13 add wave -noupdate -group debug /tb/lpp_lfr_apbreg_1/apbi
13 add wave -noupdate -expand -group debug /tb/lpp_lfr_apbreg_1/apbi
14 add wave -noupdate -group debug /tb/lpp_lfr_apbreg_1/apbo
14 add wave -noupdate -expand -group debug /tb/lpp_lfr_apbreg_1/apbo
15 add wave -noupdate -group debug /tb/ready_reg
15 add wave -noupdate -expand -group debug /tb/ready_reg
16 add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(0)
16 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(0)
17 add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(1)
17 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(1)
18 add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(2)
18 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(2)
19 add wave -noupdate -expand /tb/lpp_lfr_apbreg_1/debug_signal
19 add wave -noupdate /tb/lpp_lfr_apbreg_1/debug_signal
20 add wave -noupdate -expand -subitemconfig {/tb/lpp_lfr_ms_1/observation_vector_0(2) {-color Blue} /tb/lpp_lfr_ms_1/observation_vector_0(0) {-color Blue}} /tb/lpp_lfr_ms_1/observation_vector_0
20 add wave -noupdate -expand -subitemconfig {/tb/lpp_lfr_ms_1/observation_vector_0(2) {-color Blue -height 15} /tb/lpp_lfr_ms_1/observation_vector_0(0) {-color Blue -height 15}} /tb/lpp_lfr_ms_1/observation_vector_0
21 add wave -noupdate -expand /tb/lpp_lfr_ms_1/observation_vector_1
21 add wave -noupdate -expand /tb/lpp_lfr_ms_1/observation_vector_1
22 add wave -noupdate -divider {New Divider}
22 add wave -noupdate -divider {New Divider}
23 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter
23 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter
24 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter_out
24 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter_out
25 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter_wait
25 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter_wait
26 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_bad_component_error
27 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_buffer_full
28 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_input_fifo_write
29 add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen
30 add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren
31 add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty
32 add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full
33 add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full
34 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onnewmatrix {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onerror {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.config_ms_run {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_error_bad_component_error {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 {-height 15 -radix hexadecimal}} /tb/lpp_lfr_apbreg_1/reg_sp
35 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/sample_valid
36 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_read
37 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/sample_data
38 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/sample_load
39 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_pong
40 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_data_im
41 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_data_re
42 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_data_valid
43 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_ready
44 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft
45 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel
46 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_wen
47 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_data
48 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_full
49 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_empty
50 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/fsm_state
51 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/reg_data
52 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen_s
53 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen
54 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_data
55 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_full
26 TreeUpdate [SetDefaultTree]
56 TreeUpdate [SetDefaultTree]
27 WaveRestoreCursors {{Cursor 1} {20859515887 ps} 0}
57 WaveRestoreCursors {{Cursor 1} {41374417240 ps} 0} {{Cursor 2} {62390873400 ps} 0}
28 configure wave -namecolwidth 253
58 configure wave -namecolwidth 419
29 configure wave -valuecolwidth 112
59 configure wave -valuecolwidth 112
30 configure wave -justifyvalue left
60 configure wave -justifyvalue left
31 configure wave -signalnamewidth 0
61 configure wave -signalnamewidth 0
@@ -39,6 +69,6 configure wave -griddelta 40
39 configure wave -timeline 0
69 configure wave -timeline 0
40 configure wave -timelineunits ps
70 configure wave -timelineunits ps
41 update
71 update
42 WaveRestoreZoom {20840058904 ps} {20863099265 ps}
72 WaveRestoreZoom {62074549955 ps} {63157132736 ps}
43 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
73 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
44 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
74 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
Show file before | Show file after | Hide comments
@@ -241,6 +241,16 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
241
241
242 SIGNAL sample_load_reg : STD_LOGIC;
242 SIGNAL sample_load_reg : STD_LOGIC;
243 SIGNAL sample_load_rising_down : STD_LOGIC;
243 SIGNAL sample_load_rising_down : STD_LOGIC;
244
245 -----------------------------------------------------------------------------
246 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
247 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
248 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
249 SIGNAL sample_f1_full_head_in : STD_LOGIC;
250 SIGNAL sample_f1_full_head_out : STD_LOGIC;
251 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
252
253 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
244
254
245 BEGIN
255 BEGIN
246
256
@@ -317,7 +327,23 BEGIN
317 -- sample_f1_wdata in
327 -- sample_f1_wdata in
318 -- sample_f1_full OUT
328 -- sample_f1_full OUT
319
329
330 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1';
331 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
332 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
333
334 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
335 PORT MAP (
336 clk => clk,
337 rstn => rstn,
338 in_wen => sample_f1_wen_head_in,
339 in_data => sample_f1_wdata,
340 in_full => sample_f1_full_head_in,
341 in_empty => sample_f1_empty_head_in,
342 out_wen => sample_f1_wen_head_out,
343 out_data => sample_f1_wdata_head,
344 out_full => sample_f1_full_head_out);
320
345
346 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
321
347
322
348
323 lppFIFOxN_f1 : lppFIFOxN
349 lppFIFOxN_f1 : lppFIFOxN
@@ -333,8 +359,8 BEGIN
333
359
334 ReUse => (OTHERS => '0'),
360 ReUse => (OTHERS => '0'),
335
361
336 wen => sample_f1_wen,
362 wen => sample_f1_wen_head,
337 wdata => sample_f1_wdata,
363 wdata => sample_f1_wdata_head,
338 ren => sample_f1_ren,
364 ren => sample_f1_ren,
339 rdata => sample_f1_rdata,
365 rdata => sample_f1_rdata,
340 empty => sample_f1_empty,
366 empty => sample_f1_empty,
@@ -350,7 +376,7 BEGIN
350 one_sample_f1_full <= '0';
376 one_sample_f1_full <= '0';
351 error_wen_f1 <= '0';
377 error_wen_f1 <= '0';
352 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
378 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
353 IF sample_f1_full = "00000" THEN
379 IF sample_f1_full_head_out = '0' THEN
354 one_sample_f1_full <= '0';
380 one_sample_f1_full <= '0';
355 ELSE
381 ELSE
356 one_sample_f1_full <= '1';
382 one_sample_f1_full <= '1';
Show file before | Show file after | Hide comments
@@ -412,5 +412,18 PACKAGE lpp_lfr_pkg IS
412 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
412 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
413 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
413 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
414 END COMPONENT;
414 END COMPONENT;
415
416 COMPONENT lpp_lfr_ms_reg_head
417 PORT (
418 clk : IN STD_LOGIC;
419 rstn : IN STD_LOGIC;
420 in_wen : IN STD_LOGIC;
421 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
422 in_full : IN STD_LOGIC;
423 in_empty : IN STD_LOGIC;
424 out_wen : OUT STD_LOGIC;
425 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
426 out_full : OUT STD_LOGIC);
427 END COMPONENT;
415
428
416 END lpp_lfr_pkg;
429 END lpp_lfr_pkg;
Show file before | Show file after | Hide comments
@@ -6,4 +6,5 lpp_lfr_apbreg_ms_pointer.vhd
6 lpp_lfr_ms_fsmdma.vhd
6 lpp_lfr_ms_fsmdma.vhd
7 lpp_lfr_ms_FFT.vhd
7 lpp_lfr_ms_FFT.vhd
8 lpp_lfr_ms.vhd
8 lpp_lfr_ms.vhd
9 lpp_lfr_ms_reg_head.vhd
9 lpp_lfr.vhd
10 lpp_lfr.vhd
General Comments 0
You need to be logged in to leave comments. Login now