##// END OF EJS Templates
Change clk divider parameter of ad_conv_RHF401
pellion -
r349:36f3a1a19c4e JC
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@@ -44,7 +44,7 BEGIN
44 cnv_s <= '0';
44 cnv_s <= '0';
45 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
45 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
46 -- IF cnv_run = '1' THEN
46 -- IF cnv_run = '1' THEN
47 IF cnv_cycle_counter < ncycle_cnv THEN
47 IF cnv_cycle_counter < ncycle_cnv-1 THEN
48 cnv_cycle_counter <= cnv_cycle_counter +1;
48 cnv_cycle_counter <= cnv_cycle_counter +1;
49 IF cnv_cycle_counter < ncycle_cnv_high THEN
49 IF cnv_cycle_counter < ncycle_cnv_high THEN
50 cnv_s <= '1';
50 cnv_s <= '1';
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