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Change clk divider parameter of ad_conv_RHF401
pellion -
r349:36f3a1a19c4e JC
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1
2 LIBRARY IEEE;
2 LIBRARY IEEE;
3 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.STD_LOGIC_1164.ALL;
4 LIBRARY lpp;
4 LIBRARY lpp;
5 USE lpp.lpp_ad_conv.ALL;
5 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.general_purpose.SYNC_FF;
6 USE lpp.general_purpose.SYNC_FF;
7
7
8 ENTITY top_ad_conv_RHF1401 IS
8 ENTITY top_ad_conv_RHF1401 IS
9 GENERIC(
9 GENERIC(
10 ChanelCount : INTEGER := 8;
10 ChanelCount : INTEGER := 8;
11 ncycle_cnv_high : INTEGER := 79;
11 ncycle_cnv_high : INTEGER := 79;
12 ncycle_cnv : INTEGER := 500);
12 ncycle_cnv : INTEGER := 500);
13 PORT (
13 PORT (
14 cnv_clk : IN STD_LOGIC;
14 cnv_clk : IN STD_LOGIC;
15 cnv_rstn : IN STD_LOGIC;
15 cnv_rstn : IN STD_LOGIC;
16
16
17 cnv : OUT STD_LOGIC;
17 cnv : OUT STD_LOGIC;
18
18
19 clk : IN STD_LOGIC;
19 clk : IN STD_LOGIC;
20 rstn : IN STD_LOGIC;
20 rstn : IN STD_LOGIC;
21 ADC_data : IN Samples14;
21 ADC_data : IN Samples14;
22 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
22 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
23 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
23 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
24 sample_val : OUT STD_LOGIC
24 sample_val : OUT STD_LOGIC
25 );
25 );
26 END top_ad_conv_RHF1401;
26 END top_ad_conv_RHF1401;
27
27
28 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401 IS
28 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401 IS
29
29
30 SIGNAL cnv_cycle_counter : INTEGER;
30 SIGNAL cnv_cycle_counter : INTEGER;
31 SIGNAL cnv_s : STD_LOGIC;
31 SIGNAL cnv_s : STD_LOGIC;
32 SIGNAL cnv_sync : STD_LOGIC;
32 SIGNAL cnv_sync : STD_LOGIC;
33
33
34 BEGIN
34 BEGIN
35
35
36
36
37 -----------------------------------------------------------------------------
37 -----------------------------------------------------------------------------
38 -- CONV
38 -- CONV
39 -----------------------------------------------------------------------------
39 -----------------------------------------------------------------------------
40 PROCESS (cnv_clk, cnv_rstn)
40 PROCESS (cnv_clk, cnv_rstn)
41 BEGIN -- PROCESS
41 BEGIN -- PROCESS
42 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
42 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
43 cnv_cycle_counter <= 0;
43 cnv_cycle_counter <= 0;
44 cnv_s <= '0';
44 cnv_s <= '0';
45 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
45 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
46 -- IF cnv_run = '1' THEN
46 -- IF cnv_run = '1' THEN
47 IF cnv_cycle_counter < ncycle_cnv THEN
47 IF cnv_cycle_counter < ncycle_cnv-1 THEN
48 cnv_cycle_counter <= cnv_cycle_counter +1;
48 cnv_cycle_counter <= cnv_cycle_counter +1;
49 IF cnv_cycle_counter < ncycle_cnv_high THEN
49 IF cnv_cycle_counter < ncycle_cnv_high THEN
50 cnv_s <= '1';
50 cnv_s <= '1';
51 ELSE
51 ELSE
52 cnv_s <= '0';
52 cnv_s <= '0';
53 END IF;
53 END IF;
54 ELSE
54 ELSE
55 cnv_s <= '1';
55 cnv_s <= '1';
56 cnv_cycle_counter <= 0;
56 cnv_cycle_counter <= 0;
57 END IF;
57 END IF;
58 --ELSE
58 --ELSE
59 -- cnv_s <= '0';
59 -- cnv_s <= '0';
60 -- cnv_cycle_counter <= 0;
60 -- cnv_cycle_counter <= 0;
61 --END IF;
61 --END IF;
62 END IF;
62 END IF;
63 END PROCESS;
63 END PROCESS;
64
64
65 cnv <= cnv_s;
65 cnv <= cnv_s;
66
66
67
67
68 -----------------------------------------------------------------------------
68 -----------------------------------------------------------------------------
69 -- SYNC CNV
69 -- SYNC CNV
70 -----------------------------------------------------------------------------
70 -----------------------------------------------------------------------------
71
71
72 SYNC_FF_cnv : SYNC_FF
72 SYNC_FF_cnv : SYNC_FF
73 GENERIC MAP (
73 GENERIC MAP (
74 NB_FF_OF_SYNC => 2)
74 NB_FF_OF_SYNC => 2)
75 PORT MAP (
75 PORT MAP (
76 clk => clk,
76 clk => clk,
77 rstn => rstn,
77 rstn => rstn,
78 A => cnv_s,
78 A => cnv_s,
79 A_sync => cnv_sync);
79 A_sync => cnv_sync);
80
80
81 -----------------------------------------------------------------------------
81 -----------------------------------------------------------------------------
82 RHF1401_drvr_1: RHF1401_drvr
82 RHF1401_drvr_1: RHF1401_drvr
83 GENERIC MAP (
83 GENERIC MAP (
84 ChanelCount => ChanelCount)
84 ChanelCount => ChanelCount)
85 PORT MAP (
85 PORT MAP (
86 cnv_clk => cnv_sync,
86 cnv_clk => cnv_sync,
87 clk => clk,
87 clk => clk,
88 rstn => rstn,
88 rstn => rstn,
89 ADC_data => ADC_data,
89 ADC_data => ADC_data,
90 --ADC_smpclk => OPEN,
90 --ADC_smpclk => OPEN,
91 ADC_nOE => ADC_nOE,
91 ADC_nOE => ADC_nOE,
92 sample => sample,
92 sample => sample,
93 sample_val => sample_val);
93 sample_val => sample_val);
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97
98 END ar_top_ad_conv_RHF1401;
98 END ar_top_ad_conv_RHF1401;
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