# HG changeset patch
# User pellion
# Date 2014-04-29 13:31:42
# Node ID 36f3a1a19c4e453e91c0b351bae92e2dd7081345
# Parent  bf706ff52eaeeaf2a3f07d35a2481849544a64db

Change clk divider parameter of ad_conv_RHF401

diff --git a/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401.vhd b/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401.vhd
--- a/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401.vhd
+++ b/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401.vhd
@@ -44,7 +44,7 @@ BEGIN
       cnv_s             <= '0';
     ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
 --      IF cnv_run = '1' THEN
-      IF cnv_cycle_counter < ncycle_cnv THEN
+      IF cnv_cycle_counter < ncycle_cnv-1 THEN
         cnv_cycle_counter <= cnv_cycle_counter +1;
         IF cnv_cycle_counter < ncycle_cnv_high THEN
           cnv_s <= '1';