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add pkg conv
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22
22
23 library IEEE;
23 LIBRARY IEEE;
24 use IEEE.STD_LOGIC_1164.all;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 library grlib;
25 LIBRARY grlib;
26 use grlib.amba.all;
26 USE grlib.amba.ALL;
27 use grlib.stdlib.all;
27 USE grlib.stdlib.ALL;
28 use grlib.devices.all;
28 USE grlib.devices.ALL;
29
29
30
30
31 package lpp_ad_conv is
31 PACKAGE lpp_ad_conv IS
32
33
34 --CONSTANT AD7688 : INTEGER := 0;
35 --CONSTANT ADS7886 : INTEGER := 1;
32
36
33
37
34 constant AD7688 : integer := 0;
38 --TYPE AD7688_out IS
35 constant ADS7886 : integer := 1;
39 --RECORD
40 -- CNV : STD_LOGIC;
41 -- SCK : STD_LOGIC;
42 --END RECORD;
43
44 --TYPE AD7688_in_element IS
45 --RECORD
46 -- SDI : STD_LOGIC;
47 --END RECORD;
48
49 --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
50
51 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
36
52
53 COMPONENT ADS7886_drvr
54 GENERIC (
55 ChanelCount : INTEGER;
56 ncycle_cnv_high : INTEGER := 79;
57 ncycle_cnv : INTEGER := 500);
58 PORT (
59 cnv_clk : IN STD_LOGIC;
60 cnv_rstn : IN STD_LOGIC;
61 cnv_run : IN STD_LOGIC;
62 cnv : OUT STD_LOGIC;
63 clk : IN STD_LOGIC;
64 rstn : IN STD_LOGIC;
65 sck : OUT STD_LOGIC;
66 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
67 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
68 sample_val : OUT STD_LOGIC);
69 END COMPONENT;
37
70
38 type AD7688_out is
71 --COMPONENT AD7688_drvr IS
39 record
72 -- GENERIC(ChanelCount : INTEGER;
40 CNV : std_logic;
73 -- clkkHz : INTEGER);
41 SCK : std_logic;
74 -- PORT (clk : IN STD_LOGIC;
42 end record;
75 -- rstn : IN STD_LOGIC;
43
76 -- enable : IN STD_LOGIC;
44 type AD7688_in_element is
77 -- smplClk : IN STD_LOGIC;
45 record
78 -- DataReady : OUT STD_LOGIC;
46 SDI : std_logic;
79 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
47 end record;
80 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
48
81 -- AD_out : OUT AD7688_out);
49 type AD7688_in is array(natural range <>) of AD7688_in_element;
82 --END COMPONENT;
50
51 type Samples_out is array(natural range <>) of std_logic_vector(15 downto 0);
52
53 component AD7688_drvr is
54 generic(ChanelCount : integer;
55 clkkHz : integer);
56 Port ( clk : in STD_LOGIC;
57 rstn : in STD_LOGIC;
58 enable : in std_logic;
59 smplClk: in STD_LOGIC;
60 DataReady : out std_logic;
61 smpout : out Samples_out(ChanelCount-1 downto 0);
62 AD_in : in AD7688_in(ChanelCount-1 downto 0);
63 AD_out : out AD7688_out);
64 end component;
65
83
66
84
67 component AD7688_spi_if is
85 --COMPONENT AD7688_spi_if IS
68 generic(ChanelCount : integer);
86 -- GENERIC(ChanelCount : INTEGER);
69 Port( clk : in STD_LOGIC;
87 -- PORT(clk : IN STD_LOGIC;
70 reset : in STD_LOGIC;
88 -- reset : IN STD_LOGIC;
71 cnv : in STD_LOGIC;
89 -- cnv : IN STD_LOGIC;
72 DataReady: out std_logic;
90 -- DataReady : OUT STD_LOGIC;
73 sdi : in AD7688_in(ChanelCount-1 downto 0);
91 -- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0);
74 smpout : out Samples_out(ChanelCount-1 downto 0)
92 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0)
75 );
93 -- );
76 end component;
94 --END COMPONENT;
77
95
78
96
79 component lpp_apb_ad_conv
97 --COMPONENT lpp_apb_ad_conv
80 generic(
98 -- GENERIC(
81 pindex : integer := 0;
99 -- pindex : INTEGER := 0;
82 paddr : integer := 0;
100 -- paddr : INTEGER := 0;
83 pmask : integer := 16#fff#;
101 -- pmask : INTEGER := 16#fff#;
84 pirq : integer := 0;
102 -- pirq : INTEGER := 0;
85 abits : integer := 8;
103 -- abits : INTEGER := 8;
86 ChanelCount : integer := 1;
104 -- ChanelCount : INTEGER := 1;
87 clkkHz : integer := 50000;
105 -- clkkHz : INTEGER := 50000;
88 smpClkHz : integer := 100;
106 -- smpClkHz : INTEGER := 100;
89 ADCref : integer := AD7688);
107 -- ADCref : INTEGER := AD7688);
90 Port (
108 -- PORT (
91 clk : in STD_LOGIC;
109 -- clk : IN STD_LOGIC;
92 reset : in STD_LOGIC;
110 -- reset : IN STD_LOGIC;
93 apbi : in apb_slv_in_type;
111 -- apbi : IN apb_slv_in_type;
94 apbo : out apb_slv_out_type;
112 -- apbo : OUT apb_slv_out_type;
95 AD_in : in AD7688_in(ChanelCount-1 downto 0);
113 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
96 AD_out : out AD7688_out);
114 -- AD_out : OUT AD7688_out);
97 end component;
115 --END COMPONENT;
98
116
99 component ADS7886_drvr is
117 --COMPONENT ADS7886_drvr IS
100 generic(ChanelCount : integer;
118 -- GENERIC(ChanelCount : INTEGER;
101 clkkHz : integer);
119 -- clkkHz : INTEGER);
102 Port (
120 -- PORT (
103 clk : in STD_LOGIC;
121 -- clk : IN STD_LOGIC;
104 reset : in STD_LOGIC;
122 -- reset : IN STD_LOGIC;
105 smplClk : in STD_LOGIC;
123 -- smplClk : IN STD_LOGIC;
106 DataReady : out std_logic;
124 -- DataReady : OUT STD_LOGIC;
107 smpout : out Samples_out(ChanelCount-1 downto 0);
125 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
108 AD_in : in AD7688_in(ChanelCount-1 downto 0);
126 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
109 AD_out : out AD7688_out
127 -- AD_out : OUT AD7688_out
110 );
128 -- );
111 end component;
129 --END COMPONENT;
112
130
113 component WriteGen_ADC is
131 --COMPONENT WriteGen_ADC IS
114 port(
132 -- PORT(
115 clk : in std_logic;
133 -- clk : IN STD_LOGIC;
116 rstn : in std_logic;
134 -- rstn : IN STD_LOGIC;
117 SmplCLK : in std_logic;
135 -- SmplCLK : IN STD_LOGIC;
118 DataReady : in std_logic;
136 -- DataReady : IN STD_LOGIC;
119 Full : in std_logic_vector(4 downto 0);
137 -- Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
120 ReUse : out std_logic_vector(4 downto 0);
138 -- ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
121 Write : out std_logic_vector(4 downto 0)
139 -- Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
122 );
140 -- );
123 end component;
141 --END COMPONENT;
124
142
125 end lpp_ad_conv;
143 END lpp_ad_conv;
126
144
127
145
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