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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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PACKAGE lpp_ad_conv IS
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--CONSTANT AD7688 : INTEGER := 0;
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--CONSTANT ADS7886 : INTEGER := 1;
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--TYPE AD7688_out IS
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--RECORD
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-- CNV : STD_LOGIC;
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-- SCK : STD_LOGIC;
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--END RECORD;
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--TYPE AD7688_in_element IS
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--RECORD
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-- SDI : STD_LOGIC;
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--END RECORD;
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--TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
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TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
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COMPONENT ADS7886_drvr
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GENERIC (
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ChanelCount : INTEGER;
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ncycle_cnv_high : INTEGER := 79;
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ncycle_cnv : INTEGER := 500);
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PORT (
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cnv_clk : IN STD_LOGIC;
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cnv_rstn : IN STD_LOGIC;
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cnv_run : IN STD_LOGIC;
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cnv : OUT STD_LOGIC;
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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sck : OUT STD_LOGIC;
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sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
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sample : OUT Samples(ChanelCount-1 DOWNTO 0);
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sample_val : OUT STD_LOGIC);
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END COMPONENT;
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--COMPONENT AD7688_drvr IS
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-- GENERIC(ChanelCount : INTEGER;
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-- clkkHz : INTEGER);
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-- PORT (clk : IN STD_LOGIC;
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-- rstn : IN STD_LOGIC;
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-- enable : IN STD_LOGIC;
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-- smplClk : IN STD_LOGIC;
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-- DataReady : OUT STD_LOGIC;
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-- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
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-- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
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-- AD_out : OUT AD7688_out);
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--END COMPONENT;
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--COMPONENT AD7688_spi_if IS
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-- GENERIC(ChanelCount : INTEGER);
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-- PORT(clk : IN STD_LOGIC;
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-- reset : IN STD_LOGIC;
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-- cnv : IN STD_LOGIC;
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-- DataReady : OUT STD_LOGIC;
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-- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0);
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-- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0)
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-- );
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--END COMPONENT;
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--COMPONENT lpp_apb_ad_conv
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-- GENERIC(
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-- pindex : INTEGER := 0;
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-- paddr : INTEGER := 0;
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-- pmask : INTEGER := 16#fff#;
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-- pirq : INTEGER := 0;
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-- abits : INTEGER := 8;
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-- ChanelCount : INTEGER := 1;
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-- clkkHz : INTEGER := 50000;
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-- smpClkHz : INTEGER := 100;
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-- ADCref : INTEGER := AD7688);
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-- PORT (
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-- clk : IN STD_LOGIC;
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-- reset : IN STD_LOGIC;
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-- apbi : IN apb_slv_in_type;
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-- apbo : OUT apb_slv_out_type;
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-- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
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-- AD_out : OUT AD7688_out);
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--END COMPONENT;
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--COMPONENT ADS7886_drvr IS
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-- GENERIC(ChanelCount : INTEGER;
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-- clkkHz : INTEGER);
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-- PORT (
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-- clk : IN STD_LOGIC;
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-- reset : IN STD_LOGIC;
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-- smplClk : IN STD_LOGIC;
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-- DataReady : OUT STD_LOGIC;
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-- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
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-- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
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-- AD_out : OUT AD7688_out
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-- );
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--END COMPONENT;
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--COMPONENT WriteGen_ADC IS
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-- PORT(
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-- clk : IN STD_LOGIC;
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-- rstn : IN STD_LOGIC;
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-- SmplCLK : IN STD_LOGIC;
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-- DataReady : IN STD_LOGIC;
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-- Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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-- ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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-- Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
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-- );
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--END COMPONENT;
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END lpp_ad_conv;
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