diff --git a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
--- a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
+++ b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
@@ -20,108 +20,126 @@
 --                     Mail : alexis.jeandet@lpp.polytechnique.fr
 ----------------------------------------------------------------------------
 
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library grlib;
-use grlib.amba.all;
-use grlib.stdlib.all;
-use grlib.devices.all;
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+LIBRARY grlib;
+USE grlib.amba.ALL;
+USE grlib.stdlib.ALL;
+USE grlib.devices.ALL;
 
 
-package lpp_ad_conv is
+PACKAGE lpp_ad_conv IS
+
+
+  --CONSTANT AD7688  : INTEGER := 0;
+  --CONSTANT ADS7886 : INTEGER := 1;
 
 
-  constant    AD7688    : integer := 0;
-  constant    ADS7886   : integer := 1;
+  --TYPE AD7688_out IS
+  --RECORD
+  --  CNV : STD_LOGIC;
+  --  SCK : STD_LOGIC;
+  --END RECORD;
+
+  --TYPE AD7688_in_element IS
+  --RECORD
+  --  SDI : STD_LOGIC;
+  --END RECORD;
+
+  --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
+
+  TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
 
+  COMPONENT ADS7886_drvr
+    GENERIC (
+      ChanelCount     : INTEGER;
+      ncycle_cnv_high : INTEGER := 79;
+      ncycle_cnv      : INTEGER := 500);
+    PORT (
+      cnv_clk    : IN  STD_LOGIC;
+      cnv_rstn   : IN  STD_LOGIC;
+      cnv_run  : IN  STD_LOGIC;
+      cnv        : OUT STD_LOGIC;
+      clk        : IN  STD_LOGIC;
+      rstn       : IN  STD_LOGIC;
+      sck        : OUT STD_LOGIC;
+      sdo        : IN  STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
+      sample     : OUT Samples(ChanelCount-1 DOWNTO 0);
+      sample_val : OUT STD_LOGIC);
+  END COMPONENT;
   
-  type AD7688_out is
-    record
-        CNV        : std_logic;
-        SCK        : std_logic;
-    end record;
-	 
-  type AD7688_in_element is
-    record
-        SDI        : std_logic;
-    end record;
-	 
-	 type AD7688_in is array(natural range <>) of AD7688_in_element;
-
-	type Samples_out is array(natural range <>) of std_logic_vector(15 downto 0);
-
-	component  AD7688_drvr is
-		    generic(ChanelCount	:	integer; 
-				clkkHz		:	integer);
-		 Port ( clk 	: in  STD_LOGIC;
-                                rstn        :      in  STD_LOGIC;
-                                enable      :      in  std_logic;
-				  smplClk: in	STD_LOGIC;
-				  DataReady : out std_logic;
-				  smpout : out Samples_out(ChanelCount-1 downto 0);	
-				  AD_in	: in	AD7688_in(ChanelCount-1 downto 0);	
-				  AD_out : out AD7688_out);
-	end component;
+  --COMPONENT AD7688_drvr IS
+  --  GENERIC(ChanelCount : INTEGER;
+  --          clkkHz      : INTEGER);
+  --  PORT (clk        : IN  STD_LOGIC;
+  --         rstn      : IN  STD_LOGIC;
+  --         enable    : IN  STD_LOGIC;
+  --         smplClk   : IN  STD_LOGIC;
+  --         DataReady : OUT STD_LOGIC;
+  --         smpout    : OUT Samples_out(ChanelCount-1 DOWNTO 0);
+  --         AD_in     : IN  AD7688_in(ChanelCount-1 DOWNTO 0);
+  --         AD_out    : OUT AD7688_out);
+  --END COMPONENT;
 
 
-component AD7688_spi_if is
-	 generic(ChanelCount	:	integer);
-    Port(    clk      : in  STD_LOGIC;
-             reset    : in  STD_LOGIC;
-             cnv      : in  STD_LOGIC;
-	     DataReady:	out std_logic;
-             sdi      : in	AD7688_in(ChanelCount-1 downto 0);
-             smpout   :  out Samples_out(ChanelCount-1 downto 0)
-     );
-end component;
+  --COMPONENT AD7688_spi_if IS
+  --  GENERIC(ChanelCount : INTEGER);
+  --  PORT(clk           : IN  STD_LOGIC;
+  --           reset     : IN  STD_LOGIC;
+  --           cnv       : IN  STD_LOGIC;
+  --           DataReady : OUT STD_LOGIC;
+  --           sdi       : IN  AD7688_in(ChanelCount-1 DOWNTO 0);
+  --           smpout    : OUT Samples_out(ChanelCount-1 DOWNTO 0)
+  --           );
+  --END COMPONENT;
 
 
-component lpp_apb_ad_conv
-        generic(
-          pindex      : integer := 0;
-          paddr       : integer := 0;
-          pmask       : integer := 16#fff#;
-          pirq        : integer := 0;
-          abits       : integer := 8;
-          ChanelCount : integer := 1; 
-          clkkHz      : integer := 50000;
-	  smpClkHz    : integer := 100;
-          ADCref      : integer := AD7688);
-    Port ( 
-          clk        : in   STD_LOGIC;
-          reset      : in   STD_LOGIC;
-          apbi       : in   apb_slv_in_type;
-          apbo       : out  apb_slv_out_type;
-          AD_in      : in   AD7688_in(ChanelCount-1 downto 0);	
-          AD_out     : out  AD7688_out);
-end component;
+  --COMPONENT lpp_apb_ad_conv
+  --  GENERIC(
+  --    pindex      : INTEGER := 0;
+  --    paddr       : INTEGER := 0;
+  --    pmask       : INTEGER := 16#fff#;
+  --    pirq        : INTEGER := 0;
+  --    abits       : INTEGER := 8;
+  --    ChanelCount : INTEGER := 1;
+  --    clkkHz      : INTEGER := 50000;
+  --    smpClkHz    : INTEGER := 100;
+  --    ADCref      : INTEGER := AD7688);
+  --  PORT (
+  --    clk    : IN  STD_LOGIC;
+  --    reset  : IN  STD_LOGIC;
+  --    apbi   : IN  apb_slv_in_type;
+  --    apbo   : OUT apb_slv_out_type;
+  --    AD_in  : IN  AD7688_in(ChanelCount-1 DOWNTO 0);
+  --    AD_out : OUT AD7688_out);
+  --END COMPONENT;
 
-component ADS7886_drvr is
-    generic(ChanelCount :      integer; 
-            clkkHz      :      integer);
-    Port ( 
-            clk         :      in  STD_LOGIC;
-             reset 	: in  STD_LOGIC;
-            smplClk     :      in  STD_LOGIC;
-            DataReady   :      out std_logic;
-            smpout      :      out Samples_out(ChanelCount-1 downto 0);	
-            AD_in       :      in  AD7688_in(ChanelCount-1 downto 0);	
-            AD_out      :      out AD7688_out
-           );
-end component;
+  --COMPONENT ADS7886_drvr IS
+  --  GENERIC(ChanelCount : INTEGER;
+  --          clkkHz      : INTEGER);
+  --  PORT (
+  --    clk       : IN  STD_LOGIC;
+  --    reset     : IN  STD_LOGIC;
+  --    smplClk   : IN  STD_LOGIC;
+  --    DataReady : OUT STD_LOGIC;
+  --    smpout    : OUT Samples_out(ChanelCount-1 DOWNTO 0);
+  --    AD_in     : IN  AD7688_in(ChanelCount-1 DOWNTO 0);
+  --    AD_out    : OUT AD7688_out
+  --    );
+  --END COMPONENT;
 
-component WriteGen_ADC is
-    port(
-        clk         : in std_logic;
-        rstn        : in std_logic;
-        SmplCLK     : in std_logic;
-        DataReady   : in std_logic;
-        Full        : in std_logic_vector(4 downto 0);
-        ReUse       : out std_logic_vector(4 downto 0);
-        Write       : out std_logic_vector(4 downto 0)
-    );
-end component;
+  --COMPONENT WriteGen_ADC IS
+  --  PORT(
+  --    clk       : IN  STD_LOGIC;
+  --    rstn      : IN  STD_LOGIC;
+  --    SmplCLK   : IN  STD_LOGIC;
+  --    DataReady : IN  STD_LOGIC;
+  --    Full      : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
+  --    ReUse     : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+  --    Write     : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
+  --    );
+  --END COMPONENT;
 
-end lpp_ad_conv;
+END lpp_ad_conv;