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add pkg conv
pellion -
r123:3542464c18cc JC
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@@ -20,108 +20,126
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22
23 library IEEE;
24 use IEEE.STD_LOGIC_1164.all;
25 library grlib;
26 use grlib.amba.all;
27 use grlib.stdlib.all;
28 use grlib.devices.all;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 USE grlib.devices.ALL;
29 29
30 30
31 package lpp_ad_conv is
31 PACKAGE lpp_ad_conv IS
32
33
34 --CONSTANT AD7688 : INTEGER := 0;
35 --CONSTANT ADS7886 : INTEGER := 1;
32 36
33 37
34 constant AD7688 : integer := 0;
35 constant ADS7886 : integer := 1;
38 --TYPE AD7688_out IS
39 --RECORD
40 -- CNV : STD_LOGIC;
41 -- SCK : STD_LOGIC;
42 --END RECORD;
43
44 --TYPE AD7688_in_element IS
45 --RECORD
46 -- SDI : STD_LOGIC;
47 --END RECORD;
48
49 --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
50
51 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
36 52
53 COMPONENT ADS7886_drvr
54 GENERIC (
55 ChanelCount : INTEGER;
56 ncycle_cnv_high : INTEGER := 79;
57 ncycle_cnv : INTEGER := 500);
58 PORT (
59 cnv_clk : IN STD_LOGIC;
60 cnv_rstn : IN STD_LOGIC;
61 cnv_run : IN STD_LOGIC;
62 cnv : OUT STD_LOGIC;
63 clk : IN STD_LOGIC;
64 rstn : IN STD_LOGIC;
65 sck : OUT STD_LOGIC;
66 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
67 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
68 sample_val : OUT STD_LOGIC);
69 END COMPONENT;
37 70
38 type AD7688_out is
39 record
40 CNV : std_logic;
41 SCK : std_logic;
42 end record;
43
44 type AD7688_in_element is
45 record
46 SDI : std_logic;
47 end record;
48
49 type AD7688_in is array(natural range <>) of AD7688_in_element;
50
51 type Samples_out is array(natural range <>) of std_logic_vector(15 downto 0);
52
53 component AD7688_drvr is
54 generic(ChanelCount : integer;
55 clkkHz : integer);
56 Port ( clk : in STD_LOGIC;
57 rstn : in STD_LOGIC;
58 enable : in std_logic;
59 smplClk: in STD_LOGIC;
60 DataReady : out std_logic;
61 smpout : out Samples_out(ChanelCount-1 downto 0);
62 AD_in : in AD7688_in(ChanelCount-1 downto 0);
63 AD_out : out AD7688_out);
64 end component;
71 --COMPONENT AD7688_drvr IS
72 -- GENERIC(ChanelCount : INTEGER;
73 -- clkkHz : INTEGER);
74 -- PORT (clk : IN STD_LOGIC;
75 -- rstn : IN STD_LOGIC;
76 -- enable : IN STD_LOGIC;
77 -- smplClk : IN STD_LOGIC;
78 -- DataReady : OUT STD_LOGIC;
79 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
80 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
81 -- AD_out : OUT AD7688_out);
82 --END COMPONENT;
65 83
66 84
67 component AD7688_spi_if is
68 generic(ChanelCount : integer);
69 Port( clk : in STD_LOGIC;
70 reset : in STD_LOGIC;
71 cnv : in STD_LOGIC;
72 DataReady: out std_logic;
73 sdi : in AD7688_in(ChanelCount-1 downto 0);
74 smpout : out Samples_out(ChanelCount-1 downto 0)
75 );
76 end component;
85 --COMPONENT AD7688_spi_if IS
86 -- GENERIC(ChanelCount : INTEGER);
87 -- PORT(clk : IN STD_LOGIC;
88 -- reset : IN STD_LOGIC;
89 -- cnv : IN STD_LOGIC;
90 -- DataReady : OUT STD_LOGIC;
91 -- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0);
92 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0)
93 -- );
94 --END COMPONENT;
77 95
78 96
79 component lpp_apb_ad_conv
80 generic(
81 pindex : integer := 0;
82 paddr : integer := 0;
83 pmask : integer := 16#fff#;
84 pirq : integer := 0;
85 abits : integer := 8;
86 ChanelCount : integer := 1;
87 clkkHz : integer := 50000;
88 smpClkHz : integer := 100;
89 ADCref : integer := AD7688);
90 Port (
91 clk : in STD_LOGIC;
92 reset : in STD_LOGIC;
93 apbi : in apb_slv_in_type;
94 apbo : out apb_slv_out_type;
95 AD_in : in AD7688_in(ChanelCount-1 downto 0);
96 AD_out : out AD7688_out);
97 end component;
97 --COMPONENT lpp_apb_ad_conv
98 -- GENERIC(
99 -- pindex : INTEGER := 0;
100 -- paddr : INTEGER := 0;
101 -- pmask : INTEGER := 16#fff#;
102 -- pirq : INTEGER := 0;
103 -- abits : INTEGER := 8;
104 -- ChanelCount : INTEGER := 1;
105 -- clkkHz : INTEGER := 50000;
106 -- smpClkHz : INTEGER := 100;
107 -- ADCref : INTEGER := AD7688);
108 -- PORT (
109 -- clk : IN STD_LOGIC;
110 -- reset : IN STD_LOGIC;
111 -- apbi : IN apb_slv_in_type;
112 -- apbo : OUT apb_slv_out_type;
113 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
114 -- AD_out : OUT AD7688_out);
115 --END COMPONENT;
98 116
99 component ADS7886_drvr is
100 generic(ChanelCount : integer;
101 clkkHz : integer);
102 Port (
103 clk : in STD_LOGIC;
104 reset : in STD_LOGIC;
105 smplClk : in STD_LOGIC;
106 DataReady : out std_logic;
107 smpout : out Samples_out(ChanelCount-1 downto 0);
108 AD_in : in AD7688_in(ChanelCount-1 downto 0);
109 AD_out : out AD7688_out
110 );
111 end component;
117 --COMPONENT ADS7886_drvr IS
118 -- GENERIC(ChanelCount : INTEGER;
119 -- clkkHz : INTEGER);
120 -- PORT (
121 -- clk : IN STD_LOGIC;
122 -- reset : IN STD_LOGIC;
123 -- smplClk : IN STD_LOGIC;
124 -- DataReady : OUT STD_LOGIC;
125 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
126 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
127 -- AD_out : OUT AD7688_out
128 -- );
129 --END COMPONENT;
112 130
113 component WriteGen_ADC is
114 port(
115 clk : in std_logic;
116 rstn : in std_logic;
117 SmplCLK : in std_logic;
118 DataReady : in std_logic;
119 Full : in std_logic_vector(4 downto 0);
120 ReUse : out std_logic_vector(4 downto 0);
121 Write : out std_logic_vector(4 downto 0)
122 );
123 end component;
131 --COMPONENT WriteGen_ADC IS
132 -- PORT(
133 -- clk : IN STD_LOGIC;
134 -- rstn : IN STD_LOGIC;
135 -- SmplCLK : IN STD_LOGIC;
136 -- DataReady : IN STD_LOGIC;
137 -- Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
138 -- ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
139 -- Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
140 -- );
141 --END COMPONENT;
124 142
125 end lpp_ad_conv;
143 END lpp_ad_conv;
126 144
127 145
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