##// END OF EJS Templates
update LFR-em
pellion -
r607:337372d6bbe7 simu_with_Leon3
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@@ -92,7 +92,7 ENTITY LFR_em IS
92 92 ADC_OEB_bar_HK : OUT STD_LOGIC;
93 93 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
94 94 ---------------------------------------------------------------------------
95 TAG8 : IN STD_LOGIC;
95 TAG8 : OUT STD_LOGIC;
96 96 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
97 97 );
98 98
@@ -235,7 +235,7 BEGIN -- beh
235 235 ADDRESS_SIZE => 20,
236 236 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
237 237 BYPASS_EDAC_MEMCTRLR => '0',
238 SRBANKSZ => 8)
238 SRBANKSZ => 9)
239 239 PORT MAP (
240 240 clk => clk_25,
241 241 reset => rstn_25,
@@ -256,7 +256,7 BEGIN -- beh
256 256 nSRAM_CE => nSRAM_CE_s,
257 257 nSRAM_OE => nSRAM_OE,
258 258 nSRAM_READY => nSRAM_READY,
259 SRAM_MBE => OPEN,
259 SRAM_MBE => '0',
260 260
261 261 apbi_ext => apbi_ext,
262 262 apbo_ext => apbo_ext,
@@ -271,9 +271,6 BEGIN -- beh
271 271 nSRAM_READY <= '1';
272 272 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
273 273 nSRAM_READY <= '1';
274 IF TAG8 = '1' THEN
275 nSRAM_READY <= '0';
276 END IF;
277 274 END IF;
278 275 END PROCESS;
279 276
@@ -426,10 +423,11 BEGIN -- beh
426 423 pirq_ms => 6,
427 424 pirq_wfp => 14,
428 425 hindex => 2,
429 top_lfr_version => X"010153") -- aa.bb.cc version
426 top_lfr_version => X"010153", -- aa.bb.cc version
430 427 -- AA : BOARD NUMBER
431 428 -- 0 => MINI_LFR
432 429 -- 1 => EM
430 DEBUG_FORCE_DATA_DMA => 0)
433 431 PORT MAP (
434 432 clk => clk_25,
435 433 rstn => LFR_rstn,
@@ -480,11 +478,11 BEGIN -- beh
480 478 ADC_smpclk <= ADC_smpclk_s;
481 479 HK_smpclk <= ADC_smpclk_s;
482 480
483 -- TAG8 <= ADC_smpclk_s;
481 TAG8 <= ADC_smpclk_s;
484 482
485 483 -----------------------------------------------------------------------------
486 484 -- HK
487 485 -----------------------------------------------------------------------------
488 486 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
489 487
490 END beh; No newline at end of file
488 END beh;
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