HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r607:337372d6bbe7

update LFR-em

pellion -

r607:337372d6bbe7 simu_with_Leon3

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r607:337372d6bbe7

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designs/LFR-em-WFP_MS/LFR-em.vhd +7 -9

                 ADC_OEB_bar_HK : OUT   STD_LOGIC;
                 HK_SEL         : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
                 ---------------------------------------------------------------------------
-                TAG8           : IN   STD_LOGIC;
+                TAG8           : OUT   STD_LOGIC;
                 led            : OUT   STD_LOGIC_VECTOR(2 DOWNTO 0)
                 );
                   ADDRESS_SIZE    => 20,
                   USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
                   BYPASS_EDAC_MEMCTRLR => '0',
-                  SRBANKSZ          => 8)
+                  SRBANKSZ          => 9)
                 PORT MAP (
                   clk    => clk_25,
                   reset  => rstn_25,
                   nSRAM_CE  => nSRAM_CE_s,
                   nSRAM_OE  => nSRAM_OE,
                   nSRAM_READY => nSRAM_READY,
-                  SRAM_MBE    => OPEN,
+                  SRAM_MBE    => '0',
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   nSRAM_READY <= '1';
                 ELSIF clk_25'event AND clk_25 = '1' THEN  -- rising clock edge
                   nSRAM_READY <= '1';
-                  IF TAG8 = '1' THEN
-                    nSRAM_READY <= '0';
-                  END IF;
                 END IF;
               END PROCESS;
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"010153")  -- aa.bb.cc version
+                  top_lfr_version        => X"010153",  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM
+                  DEBUG_FORCE_DATA_DMA  => 0)
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
               ADC_smpclk <= ADC_smpclk_s;
               HK_smpclk  <= ADC_smpclk_s;
-            --  TAG8 <= ADC_smpclk_s;
+              TAG8 <= ADC_smpclk_s;
               -----------------------------------------------------------------------------
               -- HK
               -----------------------------------------------------------------------------
               ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
-            END beh;
  No newline at end of file
+            END beh;

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