# HG changeset patch
# User pellion
# Date 2015-06-04 14:02:38
# Node ID 337372d6bbe7d8827c54d29c104f83859b7b2886
# Parent  2f207df1fc75fc6efe621e9d4aa98a3772dd34fe

update LFR-em

diff --git a/designs/LFR-em-WFP_MS/LFR-em.vhd b/designs/LFR-em-WFP_MS/LFR-em.vhd
--- a/designs/LFR-em-WFP_MS/LFR-em.vhd
+++ b/designs/LFR-em-WFP_MS/LFR-em.vhd
@@ -92,7 +92,7 @@ ENTITY LFR_em IS
     ADC_OEB_bar_HK : OUT   STD_LOGIC;
     HK_SEL         : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
     ---------------------------------------------------------------------------
-    TAG8           : IN   STD_LOGIC;
+    TAG8           : OUT   STD_LOGIC;
     led            : OUT   STD_LOGIC_VECTOR(2 DOWNTO 0)
     );
 
@@ -235,7 +235,7 @@ BEGIN  -- beh
       ADDRESS_SIZE    => 20,
       USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
       BYPASS_EDAC_MEMCTRLR => '0',
-      SRBANKSZ          => 8)
+      SRBANKSZ          => 9)
     PORT MAP (
       clk    => clk_25,
       reset  => rstn_25,
@@ -256,7 +256,7 @@ BEGIN  -- beh
       nSRAM_CE  => nSRAM_CE_s,
       nSRAM_OE  => nSRAM_OE,
       nSRAM_READY => nSRAM_READY,
-      SRAM_MBE    => OPEN,
+      SRAM_MBE    => '0',
 
       apbi_ext   => apbi_ext,
       apbo_ext   => apbo_ext,
@@ -271,9 +271,6 @@ BEGIN  -- beh
       nSRAM_READY <= '1';
     ELSIF clk_25'event AND clk_25 = '1' THEN  -- rising clock edge
       nSRAM_READY <= '1';
-      IF TAG8 = '1' THEN
-        nSRAM_READY <= '0';
-      END IF;
     END IF;
   END PROCESS;
 
@@ -426,10 +423,11 @@ BEGIN  -- beh
       pirq_ms                => 6,
       pirq_wfp               => 14,
       hindex                 => 2,
-      top_lfr_version        => X"010153")  -- aa.bb.cc version
+      top_lfr_version        => X"010153",  -- aa.bb.cc version
                                             -- AA : BOARD NUMBER
                                             --      0 => MINI_LFR
                                             --      1 => EM
+      DEBUG_FORCE_DATA_DMA  => 0)      
     PORT MAP (
       clk             => clk_25,
       rstn            => LFR_rstn,
@@ -480,11 +478,11 @@ BEGIN  -- beh
   ADC_smpclk <= ADC_smpclk_s;
   HK_smpclk  <= ADC_smpclk_s;
 
---  TAG8 <= ADC_smpclk_s;
+  TAG8 <= ADC_smpclk_s;
 
   -----------------------------------------------------------------------------
   -- HK
   -----------------------------------------------------------------------------
   ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
 
-END beh;
\ No newline at end of file
+END beh;