@@ -0,0 +1,44 | |||||
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1 | #------------------------------------------------------------------------------ | |||
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2 | #-- This file is a part of the LPP VHDL IP LIBRARY | |||
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3 | #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS | |||
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4 | #-- | |||
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5 | #-- This program is free software; you can redistribute it and/or modify | |||
|
6 | #-- it under the terms of the GNU General Public License as published by | |||
|
7 | #-- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | #-- (at your option) any later version. | |||
|
9 | #-- | |||
|
10 | #-- This program is distributed in the hope that it will be useful, | |||
|
11 | #-- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | #-- GNU General Public License for more details. | |||
|
14 | #-- | |||
|
15 | #-- You should have received a copy of the GNU General Public License | |||
|
16 | #-- along with this program; if not, write to the Free Software | |||
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17 | #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
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18 | #------------------------------------------------------------------------------ | |||
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19 | ||||
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20 | include ../../rules.mk | |||
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21 | LIBDIR= | |||
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22 | INCPATH = ../../includes | |||
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23 | SCRIPTDIR=../../scripts/ | |||
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24 | LIBS= | |||
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25 | INPUTFILE=main.c | |||
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26 | EXEC=hello.bin | |||
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27 | OUTBINDIR=bin/ | |||
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28 | ||||
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29 | ||||
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30 | .PHONY:bin | |||
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31 | ||||
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32 | all:bin | |||
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33 | @echo $(EXEC)" file created" | |||
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34 | ||||
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35 | clean: | |||
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36 | rm -f *.{o,a} | |||
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37 | ||||
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38 | ||||
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39 | ||||
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40 | help:ruleshelp | |||
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41 | @echo " all : makes an executable file called "$(EXEC) | |||
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42 | @echo " in "$(OUTBINDIR) | |||
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43 | @echo " clean : removes temporary files" | |||
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44 |
@@ -0,0 +1,26 | |||||
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1 | /*------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | -------------------------------------------------------------------------------*/ | |||
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19 | #include "stdio.h" | |||
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20 | ||||
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21 | ||||
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22 | int main() | |||
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23 | { | |||
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24 | printf("hello World\n"); | |||
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25 | return 0; | |||
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26 | } |
@@ -0,0 +1,186 | |||||
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1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------ | |||
|
19 | -- Author : Alexis Jeandet | |||
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20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
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21 | ------------------------------------------------------------------------------ | |||
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22 | library ieee; | |||
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23 | use ieee.std_logic_1164.all; | |||
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24 | library grlib; | |||
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25 | use grlib.amba.all; | |||
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26 | use grlib.stdlib.all; | |||
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27 | use grlib.devices.all; | |||
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28 | library lpp; | |||
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29 | use lpp.lpp_amba.all; | |||
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30 | use lpp.apb_devices_list.all; | |||
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31 | ||||
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32 | --! Driver APB "G�n�rique" qui va faire le lien entre le bus Amba et la FIFO | |||
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33 | ||||
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34 | entity ApbFifoDriverV is | |||
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35 | generic ( | |||
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36 | pindex : integer := 0; | |||
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37 | paddr : integer := 0; | |||
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38 | pmask : integer := 16#fff#; | |||
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39 | pirq : integer := 0; | |||
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40 | abits : integer := 8; | |||
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41 | LPP_DEVICE : integer; | |||
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42 | FifoCnt : integer := 1; | |||
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43 | Data_sz : integer := 16; | |||
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44 | Addr_sz : integer := 8; | |||
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45 | addr_max_int : integer := 256); | |||
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46 | port ( | |||
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47 | clk : in std_logic; --! Horloge du composant | |||
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48 | rst : in std_logic; --! Reset general du composant | |||
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49 | ReadEnable : out std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire | |||
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50 | WriteEnable : out std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire | |||
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51 | FlagEmpty : in std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide | |||
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52 | FlagFull : in std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine | |||
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53 | ReUse : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Permet de relire la m�moire du d�but | |||
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54 | Lock : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Permet de bloquer l'�criture dans la m�moire | |||
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55 | DataIn : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e | |||
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56 | DataOut : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie | |||
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57 | AddrIn : in std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture) | |||
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58 | AddrOut : in std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) | |||
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59 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus | |||
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60 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |||
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61 | ); | |||
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62 | end ApbFifoDriverV; | |||
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63 | ||||
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64 | --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO | |||
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65 | ||||
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66 | architecture ar_ApbFifoDriverV of ApbFifoDriverV is | |||
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67 | ||||
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68 | constant REVISION : integer := 1; | |||
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69 | ||||
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70 | constant pconfig : apb_config_type := ( | |||
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71 | 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0), | |||
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72 | 1 => apb_iobar(paddr, pmask)); | |||
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73 | ||||
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74 | type DEVICE_ctrlr_Reg is record | |||
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75 | DEVICE_Cfg : std_logic_vector(5 downto 0); | |||
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76 | DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0); | |||
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77 | DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0); | |||
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78 | DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0); | |||
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79 | DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0); | |||
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80 | end record; | |||
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81 | ||||
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82 | type DEVICE_ctrlr_RegV is array(FifoCnt-1 downto 0) of DEVICE_ctrlr_Reg; | |||
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83 | ||||
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84 | signal Rec : DEVICE_ctrlr_RegV; | |||
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85 | signal Rdata : std_logic_vector(31 downto 0); | |||
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86 | ||||
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87 | signal FlagRE : std_logic; | |||
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88 | signal FlagWR : std_logic; | |||
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89 | ||||
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90 | begin | |||
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91 | ||||
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92 | fifoflags: for i in 0 to FifoCnt-1 generate: | |||
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93 | ||||
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94 | Rec(i).DEVICE_Cfg(0) <= FlagRE(i); | |||
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95 | Rec(i).DEVICE_Cfg(1) <= FlagWR(i); | |||
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96 | Rec(i).DEVICE_Cfg(2) <= FlagEmpty(i); | |||
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97 | Rec(i).DEVICE_Cfg(3) <= FlagFull(i); | |||
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98 | ||||
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99 | ReUse(i) <= Rec(i).DEVICE_Cfg(4); | |||
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100 | Lock(i) <= Rec(i).DEVICE_Cfg(5); | |||
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101 | ||||
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102 | DataIn(i*(Data_sz-1 downto 0)) <= Rec(i).DEVICE_DataW; | |||
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103 | ||||
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104 | Rec(i).DEVICE_DataR <= DataOut(i*(Data_sz-1 downto 0)); | |||
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105 | Rec(i).DEVICE_AddrW <= AddrIn(i*(Addr_sz-1 downto 0)); | |||
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106 | Rec(i).DEVICE_AddrR <= AddrOut(i*(Addr_sz-1 downto 0)); | |||
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107 | ||||
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108 | WriteEnable(i) <= FlagWR(i); | |||
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109 | ReadEnable(i) <= FlagRE(i); | |||
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110 | ||||
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111 | end generate; | |||
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112 | ||||
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113 | ||||
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114 | process(rst,clk) | |||
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115 | begin | |||
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116 | if(rst='0')then | |||
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117 | Rec.DEVICE_DataW <= (others => '0'); | |||
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118 | FlagWR <= '0'; | |||
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119 | FlagRE <= '0'; | |||
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120 | Rec.DEVICE_Cfg(4) <= '0'; | |||
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121 | Rec.DEVICE_Cfg(5) <= '0'; | |||
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122 | ||||
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123 | elsif(clk'event and clk='1')then | |||
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124 | ||||
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125 | --APB Write OP | |||
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126 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |||
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127 | case apbi.paddr(abits-1 downto 2) is | |||
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128 | when "000000" => | |||
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129 | FlagWR <= '1'; | |||
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130 | Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0); | |||
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131 | when "000010" => | |||
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132 | Rec.DEVICE_Cfg(4) <= apbi.pwdata(16); | |||
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133 | Rec.DEVICE_Cfg(5) <= apbi.pwdata(20); | |||
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134 | when others => | |||
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135 | null; | |||
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136 | end case; | |||
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137 | else | |||
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138 | FlagWR <= (others => '0'); | |||
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139 | end if; | |||
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140 | ||||
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141 | --APB Read OP | |||
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142 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |||
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143 | case apbi.paddr(abits-1 downto 2) is | |||
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144 | for i in 0 to FifoCnt-1 loop | |||
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145 | if conv_integer(apbi.paddr(7 downto 3)) = i then | |||
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146 | case apbi.paddr(2 downto 2) is | |||
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147 | when "0" => | |||
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148 | CoefsReg.numCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0)); | |||
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149 | when "1" => | |||
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150 | CoefsReg.numCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0)); | |||
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151 | when others => | |||
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152 | end case; | |||
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153 | end if; | |||
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154 | end loop; | |||
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155 | when "000000" => | |||
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156 | FlagRE <= '1'; | |||
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157 | Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR; | |||
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158 | when "000001" => | |||
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159 | Rdata(31 downto 8) <= X"AAAAAA"; | |||
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160 | Rdata(7 downto 0) <= Rec.DEVICE_AddrR; | |||
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161 | when "000101" => | |||
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162 | Rdata(31 downto 8) <= X"AAAAAA"; | |||
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163 | Rdata(7 downto 0) <= Rec.DEVICE_AddrW; | |||
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164 | when "000010" => | |||
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165 | Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0); | |||
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166 | Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1); | |||
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167 | Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2); | |||
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168 | Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3); | |||
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169 | Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4); | |||
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170 | Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5); | |||
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171 | Rdata(31 downto 24) <= X"CC"; | |||
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172 | when others => | |||
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173 | Rdata <= (others => '0'); | |||
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174 | end case; | |||
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175 | else | |||
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176 | FlagRE <= (others => '0'); | |||
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177 | end if; | |||
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178 | ||||
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179 | end if; | |||
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180 | apbo.pconfig <= pconfig; | |||
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181 | end process; | |||
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182 | ||||
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183 | apbo.prdata <= Rdata when apbi.penable = '1'; | |||
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184 | ||||
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185 | ||||
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186 | end ar_ApbFifoDriverV; No newline at end of file |
@@ -0,0 +1,184 | |||||
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1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2011, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
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21 | ------------------------------------------------------------------------------- | |||
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22 | library ieee; | |||
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23 | use ieee.std_logic_1164.all; | |||
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24 | library gaisler; | |||
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25 | use gaisler.misc.all; | |||
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26 | use gaisler.memctrl.all; | |||
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27 | library techmap; | |||
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28 | use techmap.gencomp.all; | |||
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29 | use techmap.allclkgen.all; | |||
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30 | ||||
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31 | ||||
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32 | ||||
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33 | ||||
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34 | entity ssram_plugin is | |||
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35 | generic (tech : integer := 0); | |||
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36 | port | |||
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37 | ( | |||
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38 | clk : in std_logic; | |||
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39 | mem_ctrlr_o : in memory_out_type; | |||
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40 | SSRAM_CLK : out std_logic; | |||
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41 | nBWa : out std_logic; | |||
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42 | nBWb : out std_logic; | |||
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43 | nBWc : out std_logic; | |||
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44 | nBWd : out std_logic; | |||
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45 | nBWE : out std_logic; | |||
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46 | nADSC : out std_logic; | |||
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47 | nADSP : out std_logic; | |||
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48 | nADV : out std_logic; | |||
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49 | nGW : out std_logic; | |||
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50 | nCE1 : out std_logic; | |||
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51 | CE2 : out std_logic; | |||
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52 | nCE3 : out std_logic; | |||
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53 | nOE : out std_logic; | |||
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54 | MODE : out std_logic; | |||
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55 | ZZ : out std_logic | |||
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56 | ); | |||
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57 | end entity; | |||
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58 | ||||
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59 | ||||
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60 | ||||
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61 | ||||
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62 | ||||
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63 | ||||
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64 | architecture ar_ssram_plugin of ssram_plugin is | |||
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65 | ||||
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66 | ||||
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67 | signal nADSPint : std_logic:='1'; | |||
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68 | signal nOEint : std_logic:='1'; | |||
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69 | signal RAMSN_reg: std_logic:='1'; | |||
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70 | signal OEreg : std_logic:='1'; | |||
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71 | signal nBWaint : std_logic:='1'; | |||
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72 | signal nBWbint : std_logic:='1'; | |||
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73 | signal nBWcint : std_logic:='1'; | |||
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74 | signal nBWdint : std_logic:='1'; | |||
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75 | signal nBWEint : std_logic:='1'; | |||
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76 | signal nCE1int : std_logic:='1'; | |||
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77 | signal CE2int : std_logic:='0'; | |||
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78 | signal nCE3int : std_logic:='1'; | |||
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79 | ||||
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80 | Type stateT is (idle,st1,st2,st3,st4); | |||
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81 | signal state : stateT; | |||
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82 | ||||
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83 | begin | |||
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84 | ||||
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85 | process(clk , mem_ctrlr_o.RAMSN(0)) | |||
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86 | begin | |||
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87 | if mem_ctrlr_o.RAMSN(0) ='1' then | |||
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88 | state <= idle; | |||
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89 | elsif clk ='1' and clk'event then | |||
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90 | case state is | |||
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91 | when idle => | |||
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92 | state <= st1; | |||
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93 | when st1 => | |||
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94 | state <= st2; | |||
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95 | when st2 => | |||
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96 | state <= st3; | |||
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97 | when st3 => | |||
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98 | state <= st4; | |||
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99 | when st4 => | |||
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100 | state <= st1; | |||
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101 | end case; | |||
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102 | end if; | |||
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103 | end process; | |||
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104 | ||||
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105 | ssram_clk_pad : outpad generic map (tech => tech) | |||
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106 | port map (SSRAM_CLK,not clk); | |||
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107 | ||||
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108 | ||||
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109 | nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0); | |||
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110 | nBWa_pad : outpad generic map (tech => tech) | |||
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111 | port map (nBWa,nBWaint); | |||
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112 | ||||
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113 | nBWbint <= mem_ctrlr_o.WRN(2)or mem_ctrlr_o.ramsn(0); | |||
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114 | nBWb_pad : outpad generic map (tech => tech) | |||
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115 | port map (nBWb, nBWbint); | |||
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116 | ||||
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117 | nBWcint <= mem_ctrlr_o.WRN(1)or mem_ctrlr_o.ramsn(0); | |||
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118 | nBWc_pad : outpad generic map (tech => tech) | |||
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119 | port map (nBWc, nBWcint); | |||
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120 | ||||
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121 | nBWdint <= mem_ctrlr_o.WRN(0)or mem_ctrlr_o.ramsn(0); | |||
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122 | nBWd_pad : outpad generic map (tech => tech) | |||
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123 | port map (nBWd, nBWdint); | |||
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124 | ||||
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125 | nBWEint <= mem_ctrlr_o.WRITEN or mem_ctrlr_o.ramsn(0); | |||
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126 | nBWE_pad : outpad generic map (tech => tech) | |||
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127 | port map (nBWE, nBWEint); | |||
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128 | ||||
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129 | nADSC_pad : outpad generic map (tech => tech) | |||
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130 | port map (nADSC, '1'); | |||
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131 | ||||
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132 | --nADSPint <= not((RAMSN_reg xor mem_ctrlr_o.RAMSN(0)) and RAMSN_reg); | |||
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133 | nADSPint <= '0' when state = st1 else '1'; | |||
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134 | ||||
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135 | process(clk) | |||
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136 | begin | |||
|
137 | if clk'event and clk = '1' then | |||
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138 | RAMSN_reg <= mem_ctrlr_o.RAMSN(0); | |||
|
139 | end if; | |||
|
140 | end process; | |||
|
141 | ||||
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142 | nADSP_pad : outpad generic map (tech => tech) | |||
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143 | port map (nADSP, nADSPint); | |||
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144 | ||||
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145 | nADV_pad : outpad generic map (tech => tech) | |||
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146 | port map (nADV, '1'); | |||
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147 | ||||
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148 | nGW_pad : outpad generic map (tech => tech) | |||
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149 | port map (nGW, '1'); | |||
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150 | ||||
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151 | nCE1int <= nADSPint or mem_ctrlr_o.address(31) or (not mem_ctrlr_o.address(30)) or mem_ctrlr_o.address(29) or mem_ctrlr_o.address(28); | |||
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152 | CE2int <= (not mem_ctrlr_o.address(27)) and (not mem_ctrlr_o.address(26)) and (not mem_ctrlr_o.address(25)) and (not mem_ctrlr_o.address(24)); | |||
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153 | nCE3int <= mem_ctrlr_o.address(23) or mem_ctrlr_o.address(22) or mem_ctrlr_o.address(21) or mem_ctrlr_o.address(20); | |||
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154 | ||||
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155 | nCE1_pad : outpad generic map (tech => tech) | |||
|
156 | port map (nCE1, nCE1int); | |||
|
157 | ||||
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158 | CE2_pad : outpad generic map (tech => tech) | |||
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159 | port map (CE2, CE2int); | |||
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160 | ||||
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161 | nCE3_pad : outpad generic map (tech => tech) | |||
|
162 | port map (nCE3, nCE3int); | |||
|
163 | ||||
|
164 | nOE_pad : outpad generic map (tech => tech) | |||
|
165 | port map (nOE, nOEint); | |||
|
166 | ||||
|
167 | process(clk) | |||
|
168 | begin | |||
|
169 | if clk'event and clk = '1' then | |||
|
170 | OEreg <= mem_ctrlr_o.OEN; | |||
|
171 | end if; | |||
|
172 | end process; | |||
|
173 | ||||
|
174 | ||||
|
175 | --nOEint <= OEreg or mem_ctrlr_o.RAMOEN(0); | |||
|
176 | nOEint <= '0' when state = st2 or state = st3 or state = st4 else '1'; | |||
|
177 | ||||
|
178 | MODE_pad : outpad generic map (tech => tech) | |||
|
179 | port map (MODE, '0'); | |||
|
180 | ||||
|
181 | ZZ_pad : outpad generic map (tech => tech) | |||
|
182 | port map (ZZ, '0'); | |||
|
183 | ||||
|
184 | end architecture; No newline at end of file |
@@ -0,0 +1,158 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------ | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------ | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.std_logic_1164.all; | |||
|
24 | use IEEE.numeric_std.all; | |||
|
25 | library lpp; | |||
|
26 | use lpp.lpp_memory.all; | |||
|
27 | library techmap; | |||
|
28 | use techmap.gencomp.all; | |||
|
29 | ||||
|
30 | entity lpp_fifo is | |||
|
31 | generic( | |||
|
32 | tech : integer := 0; | |||
|
33 | DataSz : integer range 1 to 32 := 8; | |||
|
34 | abits : integer range 2 to 12 := 8 | |||
|
35 | ); | |||
|
36 | port( | |||
|
37 | rstn : in std_logic; | |||
|
38 | rclk : in std_logic; | |||
|
39 | ren : in std_logic; | |||
|
40 | rdata : out std_logic_vector(DataSz-1 downto 0); | |||
|
41 | empty : out std_logic; | |||
|
42 | raddr : out std_logic_vector(abits-1 downto 0); | |||
|
43 | wclk : in std_logic; | |||
|
44 | wen : in std_logic; | |||
|
45 | wdata : in std_logic_vector(DataSz-1 downto 0); | |||
|
46 | full : out std_logic; | |||
|
47 | waddr : out std_logic_vector(abits-1 downto 0) | |||
|
48 | ); | |||
|
49 | end entity; | |||
|
50 | ||||
|
51 | ||||
|
52 | architecture ar_lpp_fifo of lpp_fifo is | |||
|
53 | ||||
|
54 | signal sFull : std_logic:='0'; | |||
|
55 | signal sEmpty : std_logic:='1'; | |||
|
56 | signal sREN : std_logic:='0'; | |||
|
57 | signal sWEN : std_logic:='0'; | |||
|
58 | ||||
|
59 | signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0'); | |||
|
60 | signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0'); | |||
|
61 | signal Waddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0'); | |||
|
62 | signal Raddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0'); | |||
|
63 | ||||
|
64 | begin | |||
|
65 | ||||
|
66 | SRAM : syncram_2p | |||
|
67 | generic map(tech,abits,DataSz) | |||
|
68 | port map(RCLK,sREN,Raddr_vect,rdata,WCLK,sWEN,Waddr_vect,wdata); | |||
|
69 | ||||
|
70 | --RAM0: entity work.RAM_CEL | |||
|
71 | -- generic map(abits, DataSz) | |||
|
72 | -- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, RCLK, WCLK, rstn); | |||
|
73 | ||||
|
74 | ||||
|
75 | --============================= | |||
|
76 | -- Read section | |||
|
77 | --============================= | |||
|
78 | sREN <= not REN and not sempty; | |||
|
79 | ||||
|
80 | process (rclk,rstn) | |||
|
81 | begin | |||
|
82 | if(rstn='0')then | |||
|
83 | Raddr_vect <= (others =>'0'); | |||
|
84 | Raddr_vect_d <= (others =>'1'); | |||
|
85 | sempty <= '1'; | |||
|
86 | elsif(rclk'event and rclk='1')then | |||
|
87 | if(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then | |||
|
88 | sempty <= '1'; | |||
|
89 | elsif(Raddr_vect/=Waddr_vect) then | |||
|
90 | sempty <= '0'; | |||
|
91 | end if; | |||
|
92 | if(sREN='1' and sempty = '0') then | |||
|
93 | Raddr_vect <= std_logic_vector(unsigned(Raddr_vect) + 1); | |||
|
94 | Raddr_vect_d <= Raddr_vect; | |||
|
95 | end if; | |||
|
96 | ||||
|
97 | end if; | |||
|
98 | end process; | |||
|
99 | ||||
|
100 | --============================= | |||
|
101 | -- Write section | |||
|
102 | --============================= | |||
|
103 | sWEN <= not WEN and not sfull; | |||
|
104 | ||||
|
105 | process (wclk,rstn) | |||
|
106 | begin | |||
|
107 | if(rstn='0')then | |||
|
108 | Waddr_vect <= (others =>'0'); | |||
|
109 | Waddr_vect_d <= (others =>'1'); | |||
|
110 | sfull <= '0'; | |||
|
111 | elsif(wclk'event and wclk='1')then | |||
|
112 | if(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then | |||
|
113 | sfull <= '1'; | |||
|
114 | elsif(Raddr_vect/=Waddr_vect) then | |||
|
115 | sfull <= '0'; | |||
|
116 | end if; | |||
|
117 | if(sWEN='1' and sfull='0') then | |||
|
118 | Waddr_vect <= std_logic_vector(unsigned(Waddr_vect) +1); | |||
|
119 | Waddr_vect_d <= Waddr_vect; | |||
|
120 | end if; | |||
|
121 | ||||
|
122 | ||||
|
123 | end if; | |||
|
124 | end process; | |||
|
125 | ||||
|
126 | ||||
|
127 | full <= sFull; | |||
|
128 | empty <= sEmpty; | |||
|
129 | waddr <= Waddr_vect; | |||
|
130 | raddr <= Raddr_vect; | |||
|
131 | ||||
|
132 | end architecture; | |||
|
133 | ||||
|
134 | ||||
|
135 | ||||
|
136 | ||||
|
137 | ||||
|
138 | ||||
|
139 | ||||
|
140 | ||||
|
141 | ||||
|
142 | ||||
|
143 | ||||
|
144 | ||||
|
145 | ||||
|
146 | ||||
|
147 | ||||
|
148 | ||||
|
149 | ||||
|
150 | ||||
|
151 | ||||
|
152 | ||||
|
153 | ||||
|
154 | ||||
|
155 | ||||
|
156 | ||||
|
157 | ||||
|
158 |
@@ -10,7 +10,7 device LPP_CNA 7 | |||||
10 | device LPP_APB_ADC 8 |
|
10 | device LPP_APB_ADC 8 | |
11 | device LPP_CHENILLARD 9 |
|
11 | device LPP_CHENILLARD 9 | |
12 | device LPP_IIR_CEL_FILTER 10 |
|
12 | device LPP_IIR_CEL_FILTER 10 | |
13 | device LPP_FIFO 11 |
|
13 | device LPP_FIFO_PID 11 | |
14 | device LPP_FFT 12 |
|
14 | device LPP_FFT 12 | |
15 | device LPP_MATRIX 13 |
|
15 | device LPP_MATRIX 13 | |
16 | device LPP_BALISE 14 |
|
16 | device LPP_BALISE 14 |
@@ -8,52 +8,101 | |||||
8 |
|
8 | |||
9 | int main() |
|
9 | int main() | |
10 | { |
|
10 | { | |
11 | int i=0; |
|
11 | int i=0,save; | |
12 | char temp[256]; |
|
12 | char temp[256]; | |
|
13 | //int TblX[10] = {0x11,0x22,0x33,0x04,0x05,0x06,0x07,0x08,0x09,0x0a}; | |||
13 | int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100}; |
|
14 | int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100}; | |
14 | int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105}; |
|
15 | int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105}; | |
15 | int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A}; |
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16 | int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A}; | |
16 |
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17 | // int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F}; | |
17 |
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18 | // int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114}; | |
18 | int Table[256]; |
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19 | int Table[256]; | |
19 |
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20 | |||
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21 | ||||
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22 | FIFO_Device* fifoX = openFIFO(0); | |||
20 | DELAY_Device* delay0 = openDELAY(0); |
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23 | DELAY_Device* delay0 = openDELAY(0); | |
21 | UART_Device* uart0 = openUART(0); |
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24 | UART_Device* uart0 = openUART(0); | |
22 |
FIFO_Device* fifo |
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25 | FIFO_Device* fifoIn = openFIFO(1); | |
23 |
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26 | MATRIX_Device* mspec = openMatrix(0); | |
24 | static MATRIX_Device* mspec; |
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27 | FIFO_Device* fifoOut = openFIFO(2); | |
25 | mspec = openMatrix(0); |
|
|||
26 | FIFO_Device* fifoOut = openFIFO(2); |
|
|||
27 | GPIO_Device* gpio0 = openGPIO(0); |
|
28 | GPIO_Device* gpio0 = openGPIO(0); | |
28 |
|
29 | |||
29 |
|
||||
30 | printf("\nDebut Main\n\n"); |
|
30 | printf("\nDebut Main\n\n"); | |
31 |
|
31 | |||
32 | Setup(delay0,30000000); |
|
32 | Setup(delay0,30000000); | |
33 | gpio0->oen = 0x3; |
|
33 | gpio0->oen = 0x3; | |
34 | gpio0->Dout = 0x0; |
|
34 | gpio0->Dout = 0x0; | |
35 |
|
35 | |||
|
36 | /////////////////////////////////////////////////////////////////////////// | |||
36 | mspec->Statu = 2; |
|
37 | mspec->Statu = 2; | |
37 |
FillFifo(fifo0,TblB1 |
|
38 | FillFifo(fifoIn,0,TblB1); | |
38 |
FillFifo(fifo1,TblB2 |
|
39 | FillFifo(fifoIn,1,TblB2); | |
|
40 | gpio0->Dout = 0x1; | |||
39 |
|
41 | |||
40 | Delay_ms(delay0,10); |
|
42 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS | |
41 | gpio0->Dout = 0x1; |
|
|||
42 | for (i = 0 ; i < 256 ; i++) |
|
|||
43 | { |
|
43 | { | |
44 |
Table[i] = fifoOut-> |
|
44 | Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; | |
|
45 | i++; | |||
45 | } |
|
46 | } | |
46 |
|
47 | save = i; | ||
47 | gpio0->Dout = 0x2; |
|
48 | gpio0->Dout = 0x2; | |
48 | sprintf(temp,"Reels\tImaginaires\n\r"); |
|
49 | ||
|
50 | sprintf(temp,"\nReels\tImaginaires\n\r"); | |||
49 | uartputs(uart0,temp); |
|
51 | uartputs(uart0,temp); | |
50 |
for (i = 0 ; i < |
|
52 | for (i = 0 ; i < save ; i+=2) | |
51 | { |
|
53 | { | |
52 | sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]); |
|
54 | sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]); | |
53 | uartputs(uart0,temp); |
|
55 | uartputs(uart0,temp); | |
54 | } |
|
56 | } | |
|
57 | i = 0; | |||
|
58 | gpio0->Dout = 0x0; | |||
55 |
|
59 | |||
56 | gpio0->Dout = 0x3; |
|
60 | /////////////////////////////////////////////////////////////////////////// | |
|
61 | mspec->Statu = 1; | |||
|
62 | FillFifo(fifoIn,0,TblB1); | |||
|
63 | gpio0->Dout = 0x1; | |||
|
64 | Delay_us(delay0,20); | |||
|
65 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS | |||
|
66 | { | |||
|
67 | Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; | |||
|
68 | i++; | |||
|
69 | } | |||
|
70 | save = i; | |||
|
71 | gpio0->Dout = 0x2; | |||
|
72 | ||||
|
73 | sprintf(temp,"\nReels\n\r"); | |||
|
74 | uartputs(uart0,temp); | |||
|
75 | for (i = 0 ; i < save ; i++) | |||
|
76 | { | |||
|
77 | sprintf(temp,"%d\n\r",Table[i]); | |||
|
78 | uartputs(uart0,temp); | |||
|
79 | } | |||
|
80 | i = 0; | |||
|
81 | gpio0->Dout = 0x0; | |||
|
82 | ||||
|
83 | /////////////////////////////////////////////////////////////////////////// | |||
|
84 | mspec->Statu = 4; | |||
|
85 | FillFifo(fifoIn,0,TblB1); | |||
|
86 | FillFifo(fifoIn,1,TblB3); | |||
|
87 | gpio0->Dout = 0x1; | |||
|
88 | ||||
|
89 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS | |||
|
90 | { | |||
|
91 | Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; | |||
|
92 | i++; | |||
|
93 | } | |||
|
94 | save = i; | |||
|
95 | gpio0->Dout = 0x2; | |||
|
96 | ||||
|
97 | sprintf(temp,"\nReels\tImaginaires\n\r"); | |||
|
98 | uartputs(uart0,temp); | |||
|
99 | for (i = 0 ; i < save ; i+=2) | |||
|
100 | { | |||
|
101 | sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]); | |||
|
102 | uartputs(uart0,temp); | |||
|
103 | } | |||
|
104 | i = 0; | |||
|
105 | gpio0->Dout = 0x0; | |||
57 |
|
106 | |||
58 | printf("\nFin Main\n\n"); |
|
107 | printf("\nFin Main\n\n"); | |
59 | return 0; |
|
108 | return 0; | |
@@ -65,17 +114,21 int main() | |||||
65 |
|
114 | |||
66 |
|
115 | |||
67 |
|
116 | |||
68 |
|
117 | /////////////////// Test R/W Fifo OKAI /////////////////////////////////// | ||
69 |
|
||||
70 |
|
118 | |||
71 |
|
119 | /*fifoX->FIFOreg[(2*0)+FIFO_RWdata] = 0x11; | ||
72 |
|
120 | Table[1] = fifoX->FIFOreg[(2*0)+FIFO_RWdata]; | ||
|
121 | printf("data: %x\n",Table[1]); | |||
73 |
|
|
122 | ||
74 |
|
123 | FillFifo(fifoX,0,TblX); | ||
75 |
|
124 | for (i = 1 ; i < 8 ; i++) | ||
76 |
|
125 | { | ||
77 |
|
126 | Table[i] = fifoX->FIFOreg[(2*0)+FIFO_RWdata] & Mask_2hex; | ||
78 |
|
127 | } | ||
|
128 | printf("data: %x\n",Table[1]); | |||
|
129 | printf("data: %x\n",Table[2]); | |||
|
130 | printf("data: %x\n",Table[3]); | |||
|
131 | printf("data: %x\n",Table[4]);*/ | |||
79 |
|
132 | |||
80 |
|
133 | |||
81 |
|
134 |
@@ -27,19 +27,18 | |||||
27 | FIFO_Device* openFIFO(int count) |
|
27 | FIFO_Device* openFIFO(int count) | |
28 | { |
|
28 | { | |
29 | FIFO_Device* fifo0; |
|
29 | FIFO_Device* fifo0; | |
30 | fifo0 = (FIFO_Device*) apbgetdevice(LPP_FIFO,VENDOR_LPP,count); |
|
30 | fifo0 = (FIFO_Device*) apbgetdevice(LPP_FIFO_PID,VENDOR_LPP,count); | |
31 | return fifo0; |
|
31 | return fifo0; | |
32 | } |
|
32 | } | |
33 |
|
33 | |||
34 |
|
34 | |||
35 |
int FillFifo(FIFO_Device* dev,int Tbl[] |
|
35 | int FillFifo(FIFO_Device* dev,int ID,int Tbl[]) | |
36 | { |
|
36 | { | |
37 | int i=0; |
|
37 | int i=0; | |
38 | while(i <= A) |
|
38 | while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full) // TANT QUE full a 0 ALORS | |
39 | { |
|
39 | { | |
40 |
dev-> |
|
40 | dev->FIFOreg[(2*ID)+FIFO_RWdata] = Tbl[i]; | |
41 | i++; |
|
41 | i++; | |
42 | } |
|
42 | } | |
43 |
|
||||
44 | return 0; |
|
43 | return 0; | |
45 | } |
|
44 | } |
@@ -28,12 +28,15 | |||||
28 | This library is written to work with LPP_APB_FIFO VHDL module from LPP's FreeVHDLIB. It represents a standard FIFO working, |
|
28 | This library is written to work with LPP_APB_FIFO VHDL module from LPP's FreeVHDLIB. It represents a standard FIFO working, | |
29 | used in many type of application. |
|
29 | used in many type of application. | |
30 |
|
30 | |||
|
31 | \todo Check "DEVICE1 => count = 2" function Open | |||
31 | \author Martin Morlot martin.morlot@lpp.polytechnique.fr |
|
32 | \author Martin Morlot martin.morlot@lpp.polytechnique.fr | |
32 | */ |
|
33 | */ | |
33 | #define FIFO_Empty 0x00000100 /**< Show that the FIFO is Empty */ |
|
34 | #define FIFO_Ctrl 0 | |
34 | #define FIFO_Full 0x00001000 /**< Show that the FIFO is Full */ |
|
35 | #define FIFO_RWdata 1 | |
35 | #define Boucle 0x00110000 /**< Configuration for reused the same value of the FIFO */ |
|
36 | #define FIFO_Full 0x00010000 | |
36 | #define NoBoucle 0xFFEEFFFF /**< Unlock the previous configuration */ |
|
37 | #define FIFO_Empty 0x00000001 | |
|
38 | #define Mask_2hex 0x000000FF | |||
|
39 | #define Mask_4hex 0x0000FFFF | |||
37 |
|
40 | |||
38 |
|
41 | |||
39 | /*=================================================== |
|
42 | /*=================================================== | |
@@ -45,18 +48,9 | |||||
45 | */ |
|
48 | */ | |
46 | struct APB_FIFO_REG |
|
49 | struct APB_FIFO_REG | |
47 | { |
|
50 | { | |
48 | int rwdata; /**< \brief Data register Write/Read */ |
|
51 | int IDreg; | |
49 | int raddr; /**< \brief Address register for the reading operation */ |
|
52 | int FIFOreg[2*8]; | |
50 | int cfgreg; /**< \brief Configuration register composed of Read enable Flag [HEX 0] |
|
53 | ||
51 | Write enable Flag [HEX 1] |
|
|||
52 | Empty Flag [HEX 2] |
|
|||
53 | Full Flag [HEX 3] |
|
|||
54 | ReUse Flag [HEX 4] |
|
|||
55 | Lock Flag [HEX 5] |
|
|||
56 | Dummy "C" [HEX 6/7] */ |
|
|||
57 | int dummy0; /**< \brief Unused register, aesthetic interest */ |
|
|||
58 | int dummy1; /**< \brief Unused register, aesthetic interest */ |
|
|||
59 | int waddr; /**< \brief Address register for the writing operation */ |
|
|||
60 | }; |
|
54 | }; | |
61 |
|
55 | |||
62 | typedef volatile struct APB_FIFO_REG FIFO_Device; |
|
56 | typedef volatile struct APB_FIFO_REG FIFO_Device; | |
@@ -75,16 +69,6 typedef volatile struct APB_FIFO_REG FIF | |||||
75 | \return The pointer to the device. |
|
69 | \return The pointer to the device. | |
76 | */ |
|
70 | */ | |
77 | FIFO_Device* openFIFO(int count); |
|
71 | FIFO_Device* openFIFO(int count); | |
78 |
|
72 | int FillFifo(FIFO_Device* dev,int ID,int Tbl[]); | ||
79 | /*! \fn int FillFifo(FIFO_Device* dev,int Tbl[],int A); |
|
|||
80 | \brief a Fill in FIFO function. |
|
|||
81 |
|
||||
82 | This Function fill in the FIFO with a table data. |
|
|||
83 |
|
||||
84 | \param dev The FFT pointer. |
|
|||
85 | \param Tbl[] The data table. |
|
|||
86 | \param A The data table size. |
|
|||
87 | */ |
|
|||
88 | int FillFifo(FIFO_Device* dev,int Tbl[],int A); |
|
|||
89 |
|
73 | |||
90 | #endif |
|
74 | #endif |
@@ -16,11 +16,15 | |||||
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 |
-- Author : |
|
19 | -- Author : Alexis Jeandet | |
20 |
-- Mail : |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
|
22 | -- APB_FIFO.vhd | |||
22 | library ieee; |
|
23 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
24 | use ieee.std_logic_1164.all; | |
|
25 | use IEEE.numeric_std.all; | |||
|
26 | library techmap; | |||
|
27 | use techmap.gencomp.all; | |||
24 | library grlib; |
|
28 | library grlib; | |
25 | use grlib.amba.all; |
|
29 | use grlib.amba.all; | |
26 | use grlib.stdlib.all; |
|
30 | use grlib.stdlib.all; | |
@@ -30,59 +34,242 use lpp.lpp_amba.all; | |||||
30 | use lpp.apb_devices_list.all; |
|
34 | use lpp.apb_devices_list.all; | |
31 | use lpp.lpp_memory.all; |
|
35 | use lpp.lpp_memory.all; | |
32 |
|
36 | |||
33 | --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba |
|
|||
34 |
|
37 | |||
35 | entity APB_FIFO is |
|
38 | entity APB_FIFO is | |
36 |
|
|
39 | generic ( | |
|
40 | tech : integer := apa3; | |||
37 | pindex : integer := 0; |
|
41 | pindex : integer := 0; | |
38 | paddr : integer := 0; |
|
42 | paddr : integer := 0; | |
39 | pmask : integer := 16#fff#; |
|
43 | pmask : integer := 16#fff#; | |
40 | pirq : integer := 0; |
|
44 | pirq : integer := 0; | |
41 |
abits : integer := 8; |
|
45 | abits : integer := 8; | |
|
46 | FifoCnt : integer := 2; | |||
42 | Data_sz : integer := 16; |
|
47 | Data_sz : integer := 16; | |
43 |
Addr_sz : integer := |
|
48 | Addr_sz : integer := 9; | |
44 | addr_max_int : integer := 256); |
|
49 | R : integer := 1; | |
|
50 | W : integer := 1 | |||
|
51 | ); | |||
45 | port ( |
|
52 | port ( | |
46 | clk : in std_logic; --! Horloge du composant |
|
53 | clk : in std_logic; --! Horloge du composant | |
47 | rst : in std_logic; --! Reset general du composant |
|
54 | rst : in std_logic; --! Reset general du composant | |
48 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus |
|
55 | rclk : in std_logic; | |
49 |
|
|
56 | wclk : in std_logic; | |
50 | Empty : out std_logic; |
|
57 | REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire | |
51 | WR : out std_logic; |
|
58 | WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire | |
52 | RE : out std_logic; |
|
59 | Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide | |
53 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus |
|
60 | Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine | |
|
61 | RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e | |||
|
62 | WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie | |||
|
63 | WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture) | |||
|
64 | RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) | |||
|
65 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus | |||
|
66 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |||
54 | ); |
|
67 | ); | |
55 | end APB_FIFO; |
|
68 | end entity; | |
56 |
|
||||
57 |
|
69 | |||
58 | architecture ar_APB_FIFO of APB_FIFO is |
|
70 | architecture ar_APB_FIFO of APB_FIFO is | |
59 |
|
71 | |||
60 | signal ReadEnable : std_logic; |
|
72 | constant REVISION : integer := 1; | |
61 | signal WriteEnable : std_logic; |
|
73 | ||
62 | signal FlagEmpty : std_logic; |
|
74 | constant pconfig : apb_config_type := ( | |
63 | signal FlagFull : std_logic; |
|
75 | 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0), | |
64 | --signal ReUse : std_logic; |
|
76 | 1 => apb_iobar(paddr, pmask)); | |
65 | --signal Lock : std_logic; |
|
77 | ||
66 | signal RstMem : std_logic; |
|
78 | type FIFO_ctrlr_Reg is record | |
67 |
|
|
79 | FIFO_Ctrl : std_logic_vector(31 downto 0); | |
68 |
|
|
80 | FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0); | |
69 |
|
|
81 | FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0); | |
70 | signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); |
|
82 | end record; | |
|
83 | ||||
|
84 | type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg; | |||
|
85 | type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0); | |||
|
86 | type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0); | |||
|
87 | ||||
|
88 | signal Rec : FIFO_ctrlr_Reg_Vec; | |||
|
89 | signal PRdata : std_logic_vector(31 downto 0); | |||
|
90 | signal FIFO_ID : std_logic_vector(31 downto 0); | |||
|
91 | signal autoloaded : std_logic_vector(FifoCnt-1 downto 0); | |||
|
92 | signal sFull : std_logic_vector(FifoCnt-1 downto 0); | |||
|
93 | signal sEmpty : std_logic_vector(FifoCnt-1 downto 0); | |||
|
94 | signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0); | |||
|
95 | signal sWen : std_logic_vector(FifoCnt-1 downto 0); | |||
|
96 | signal sRen : std_logic_vector(FifoCnt-1 downto 0); | |||
|
97 | signal sRclk : std_logic; | |||
|
98 | signal sWclk : std_logic; | |||
|
99 | signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0); | |||
|
100 | signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0); | |||
|
101 | signal sRDATA : fifodatabus; | |||
|
102 | signal sWDATA : fifodatabus; | |||
|
103 | signal sWADDR : fifoaddressbus; | |||
|
104 | signal sRADDR : fifoaddressbus; | |||
|
105 | ||||
|
106 | type state_t is (idle,Read); | |||
|
107 | signal fiforeadfsmst : state_t; | |||
71 |
|
108 | |||
72 | begin |
|
109 | begin | |
73 |
|
110 | |||
74 | APB : ApbDriver |
|
111 | FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4)); | |
75 | generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) |
|
112 | FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8)); | |
76 | port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,RstMem,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); |
|
113 | FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8)); | |
|
114 | ||||
|
115 | ||||
|
116 | Write : if W /= 0 generate | |||
|
117 | FIFO_ID(4) <= '1'; | |||
|
118 | sWen <= sWen_APB; | |||
|
119 | sWclk <= clk; | |||
|
120 | Wrapb: for i in 0 to FifoCnt-1 generate | |||
|
121 | sWDATA(i) <= Rec(i).FIFO_Wdata; | |||
|
122 | end generate; | |||
|
123 | end generate; | |||
|
124 | ||||
|
125 | Writeext : if W = 0 generate | |||
|
126 | FIFO_ID(4) <= '0'; | |||
|
127 | sWen <= WEN; | |||
|
128 | sWclk <= Wclk; | |||
|
129 | Wrext: for i in 0 to FifoCnt-1 generate | |||
|
130 | sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i); | |||
|
131 | end generate; | |||
|
132 | end generate; | |||
|
133 | ||||
|
134 | Read : if R /= 0 generate | |||
|
135 | FIFO_ID(5) <= '1'; | |||
|
136 | sRen <= sRen_APB; | |||
|
137 | srclk <= clk; | |||
|
138 | Rdapb: for i in 0 to FifoCnt-1 generate | |||
|
139 | Rec(i).FIFO_Rdata <= sRDATA(i); | |||
|
140 | end generate; | |||
|
141 | end generate; | |||
|
142 | ||||
|
143 | Readext : if R = 0 generate | |||
|
144 | FIFO_ID(5) <= '0'; | |||
|
145 | sRen <= REN; | |||
|
146 | srclk <= rclk; | |||
|
147 | Drext: for i in 0 to FifoCnt-1 generate | |||
|
148 | RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i) <= sRDATA(i); | |||
|
149 | end generate; | |||
|
150 | end generate; | |||
|
151 | ||||
|
152 | ctrlregs: for i in 0 to FifoCnt-1 generate | |||
|
153 | RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i); | |||
|
154 | WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i); | |||
|
155 | Rec(i).FIFO_Ctrl(16) <= sFull(i); | |||
|
156 | Rec(i).FIFO_Ctrl(Addr_sz downto 1) <= sRADDR(i); | |||
|
157 | Rec(i).FIFO_Ctrl((Addr_sz+16) downto 17) <= sWADDR(i); ---|free|Waddrs|Full||free|Raddrs|empty| | |||
|
158 | end generate; -- 31 17 16 15 1 0 | |||
|
159 | ||||
|
160 | Empty <= sEmpty; | |||
|
161 | Full <= sFull; | |||
77 |
|
162 | |||
78 |
|
163 | |||
79 | DEVICE : Top_FIFO |
|
164 | fifos: for i in 0 to FifoCnt-1 generate | |
80 | generic map(Data_sz,Addr_sz,addr_max_int) |
|
165 | FIFO0 : lpp_fifo | |
81 | port map(clk,rst,ReadEnable,WriteEnable,RstMem,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); |
|
166 | generic map (tech,Data_sz,Addr_sz) | |
|
167 | port map(rst,srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i)); | |||
|
168 | end generate; | |||
|
169 | ||||
|
170 | process(rst,clk) | |||
|
171 | begin | |||
|
172 | if(rst='0')then | |||
|
173 | rstloop1: for i in 0 to FifoCnt-1 loop | |||
|
174 | Rec(i).FIFO_Wdata <= (others => '0'); | |||
|
175 | sWen_APB(i) <= '1'; | |||
|
176 | end loop; | |||
|
177 | elsif(clk'event and clk='1')then | |||
|
178 | --APB Write OP | |||
|
179 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |||
|
180 | writelp: for i in 0 to FifoCnt-1 loop | |||
|
181 | if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then | |||
|
182 | Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0); | |||
|
183 | sWen_APB(i) <= '0'; | |||
|
184 | end if; | |||
|
185 | end loop; | |||
|
186 | else | |||
|
187 | sWen_APB <= (others =>'1'); | |||
|
188 | end if; | |||
|
189 | --APB Read OP | |||
|
190 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |||
|
191 | if(apbi.paddr(abits-1 downto 2)="000000") then | |||
|
192 | PRdata <= FIFO_ID; | |||
|
193 | else | |||
|
194 | readlp: for i in 0 to FifoCnt-1 loop | |||
|
195 | if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then | |||
|
196 | PRdata <= Rec(i).FIFO_Ctrl; | |||
|
197 | elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then | |||
|
198 | PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata; | |||
|
199 | end if; | |||
|
200 | end loop; | |||
|
201 | end if; | |||
|
202 | end if; | |||
|
203 | end if; | |||
|
204 | apbo.pconfig <= pconfig; | |||
|
205 | end process; | |||
|
206 | apbo.prdata <= PRdata when apbi.penable = '1'; | |||
|
207 | ||||
|
208 | ||||
82 |
|
209 | |||
83 | Empty <= FlagEmpty; |
|
210 | process(rst,clk) | |
84 | Full <= FlagFull; |
|
211 | begin | |
85 | WR <= WriteEnable; |
|
212 | if(rst='0')then | |
86 | RE <= ReadEnable; |
|
213 | fiforeadfsmst <= idle; | |
|
214 | rstloop: for i in 0 to FifoCnt-1 loop | |||
|
215 | sRen_APB(i) <= '1'; | |||
|
216 | autoloaded(i) <= '1'; | |||
|
217 | Rec(i).FIFO_Ctrl(0) <= sEmpty(i); | |||
|
218 | end loop; | |||
|
219 | elsif clk'event and clk = '1' then | |||
|
220 | sEmpty_d <= sEmpty; | |||
|
221 | case fiforeadfsmst is | |||
|
222 | when idle => | |||
|
223 | idlelp: for i in 0 to FifoCnt-1 loop | |||
|
224 | if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then | |||
|
225 | if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then | |||
|
226 | autoloaded(i) <= '0'; | |||
|
227 | else | |||
|
228 | autoloaded(i) <= '1'; | |||
|
229 | end if; | |||
|
230 | sRen_APB(i) <= '0'; | |||
|
231 | fiforeadfsmst <= read; | |||
|
232 | Rec(i).FIFO_Ctrl(0) <= sEmpty(i); | |||
|
233 | else | |||
|
234 | sRen_APB(i) <= '1'; | |||
|
235 | end if; | |||
|
236 | end loop; | |||
|
237 | when read => | |||
|
238 | sRen_APB <= (others => '1'); | |||
|
239 | fiforeadfsmst <= idle; | |||
|
240 | when others => | |||
|
241 | fiforeadfsmst <= idle; | |||
|
242 | end case; | |||
|
243 | end if; | |||
|
244 | end process; | |||
87 |
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245 | |||
88 | end ar_APB_FIFO; No newline at end of file |
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246 | ||
|
247 | end ar_APB_FIFO; | |||
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248 | ||||
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275 |
@@ -26,237 +26,93 use grlib.amba.all; | |||||
26 | use std.textio.all; |
|
26 | use std.textio.all; | |
27 | library lpp; |
|
27 | library lpp; | |
28 | use lpp.lpp_amba.all; |
|
28 | use lpp.lpp_amba.all; | |
|
29 | library gaisler; | |||
|
30 | use gaisler.misc.all; | |||
|
31 | use gaisler.memctrl.all; | |||
|
32 | library techmap; | |||
|
33 | use techmap.gencomp.all; | |||
29 |
|
34 | |||
30 | --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on |
|
35 | --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on | |
31 |
|
36 | |||
32 | package lpp_memory is |
|
37 | package lpp_memory is | |
33 |
|
38 | |||
34 | --===========================================================| |
|
|||
35 | --=================== FIFO Compl�te =========================| |
|
|||
36 | --===========================================================| |
|
|||
37 |
|
||||
38 | component APB_FIFO is |
|
39 | component APB_FIFO is | |
39 |
|
|
40 | generic ( | |
40 |
|
|
41 | tech : integer := apa3; | |
41 | paddr : integer := 0; |
|
|||
42 | pmask : integer := 16#fff#; |
|
|||
43 | pirq : integer := 0; |
|
|||
44 | abits : integer := 8; |
|
|||
45 | Data_sz : integer := 16; |
|
|||
46 | Addr_sz : integer := 8; |
|
|||
47 | addr_max_int : integer := 256); |
|
|||
48 | port ( |
|
|||
49 | clk : in std_logic; |
|
|||
50 | rst : in std_logic; |
|
|||
51 | apbi : in apb_slv_in_type; |
|
|||
52 | Full : out std_logic; |
|
|||
53 | Empty : out std_logic; |
|
|||
54 | WR : out std_logic; |
|
|||
55 | RE : out std_logic; |
|
|||
56 | apbo : out apb_slv_out_type |
|
|||
57 | ); |
|
|||
58 | end component; |
|
|||
59 |
|
||||
60 |
|
||||
61 | component ApbDriver is |
|
|||
62 | generic ( |
|
|||
63 | pindex : integer := 0; |
|
42 | pindex : integer := 0; | |
64 | paddr : integer := 0; |
|
43 | paddr : integer := 0; | |
65 | pmask : integer := 16#fff#; |
|
44 | pmask : integer := 16#fff#; | |
66 | pirq : integer := 0; |
|
45 | pirq : integer := 0; | |
67 | abits : integer := 8; |
|
46 | abits : integer := 8; | |
68 |
|
|
47 | FifoCnt : integer := 2; | |
69 | Data_sz : integer := 16; |
|
48 | Data_sz : integer := 16; | |
70 |
Addr_sz : integer := |
|
49 | Addr_sz : integer := 9; | |
71 | addr_max_int : integer := 256); |
|
50 | R : integer := 1; | |
72 | port ( |
|
51 | W : integer := 1 | |
73 | clk : in std_logic; |
|
|||
74 | rst : in std_logic; |
|
|||
75 | ReadEnable : out std_logic; |
|
|||
76 | WriteEnable : out std_logic; |
|
|||
77 | FlagEmpty : in std_logic; |
|
|||
78 | FlagFull : in std_logic; |
|
|||
79 | -- ReUse : out std_logic; |
|
|||
80 | -- Lock : out std_logic; |
|
|||
81 | RstMem : out std_logic; |
|
|||
82 | DataIn : out std_logic_vector(Data_sz-1 downto 0); |
|
|||
83 | DataOut : in std_logic_vector(Data_sz-1 downto 0); |
|
|||
84 | AddrIn : in std_logic_vector(Addr_sz-1 downto 0); |
|
|||
85 | AddrOut : in std_logic_vector(Addr_sz-1 downto 0); |
|
|||
86 | apbi : in apb_slv_in_type; |
|
|||
87 | apbo : out apb_slv_out_type |
|
|||
88 | ); |
|
|||
89 | end component; |
|
|||
90 |
|
||||
91 |
|
||||
92 | component Top_FIFO is |
|
|||
93 | generic( |
|
|||
94 | Data_sz : integer := 16; |
|
|||
95 | Addr_sz : integer := 8; |
|
|||
96 | addr_max_int : integer := 256 |
|
|||
97 | ); |
|
|||
98 | port( |
|
|||
99 | clk,raz : in std_logic; |
|
|||
100 | flag_RE : in std_logic; |
|
|||
101 | flag_WR : in std_logic; |
|
|||
102 | -- ReUse : in std_logic; |
|
|||
103 | -- Lock : in std_logic; |
|
|||
104 | RstMem : in std_logic; |
|
|||
105 | Data_in : in std_logic_vector(Data_sz-1 downto 0); |
|
|||
106 | Addr_RE : out std_logic_vector(addr_sz-1 downto 0); |
|
|||
107 | Addr_WR : out std_logic_vector(addr_sz-1 downto 0); |
|
|||
108 | full : out std_logic; |
|
|||
109 | empty : out std_logic; |
|
|||
110 | Data_out : out std_logic_vector(Data_sz-1 downto 0) |
|
|||
111 | ); |
|
52 | ); | |
112 | end component; |
|
53 | port ( | |
113 |
|
54 | clk : in std_logic; --! Horloge du composant | ||
114 |
|
55 | rst : in std_logic; --! Reset general du composant | ||
115 | component Fifo_Read is |
|
56 | rclk : in std_logic; | |
116 | generic( |
|
57 | wclk : in std_logic; | |
117 | Addr_sz : integer := 8; |
|
58 | REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire | |
118 | addr_max_int : integer := 256); |
|
59 | WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire | |
119 | port( |
|
60 | Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide | |
120 | clk : in std_logic; |
|
61 | Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine | |
121 | raz : in std_logic; |
|
62 | RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e | |
122 | flag_RE : in std_logic; |
|
63 | WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie | |
123 |
W |
|
64 | WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture) | |
124 | empty : out std_logic; |
|
65 | RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) | |
125 | Raddr : out std_logic_vector(addr_sz-1 downto 0) |
|
66 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus | |
126 | ); |
|
67 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |
127 | end component; |
|
|||
128 |
|
||||
129 |
|
||||
130 | component Fifo_Write is |
|
|||
131 | generic( |
|
|||
132 | Addr_sz : integer := 8; |
|
|||
133 | addr_max_int : integer := 256); |
|
|||
134 | port( |
|
|||
135 | clk : in std_logic; |
|
|||
136 | raz : in std_logic; |
|
|||
137 | flag_WR : in std_logic; |
|
|||
138 | Raddr : in std_logic_vector(addr_sz-1 downto 0); |
|
|||
139 | full : out std_logic; |
|
|||
140 | Waddr : out std_logic_vector(addr_sz-1 downto 0) |
|
|||
141 | ); |
|
|||
142 | end component; |
|
|||
143 |
|
||||
144 |
|
||||
145 | component PipeLine is |
|
|||
146 | generic(Data_sz : integer := 16); |
|
|||
147 | port( |
|
|||
148 | clk,raz : in std_logic; --! Horloge et reset general du composant |
|
|||
149 | Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Donn�e en entr�e de la FIFO, cot� �criture |
|
|||
150 | flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire |
|
|||
151 | flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire |
|
|||
152 | empty : in std_logic; --! Flag, M�moire vide |
|
|||
153 | Data_svg : out std_logic_vector(Data_sz-1 downto 0); |
|
|||
154 | Data1 : out std_logic; |
|
|||
155 | Data2 : out std_logic |
|
|||
156 | ); |
|
68 | ); | |
157 | end component; |
|
69 | end component; | |
158 |
|
70 | |||
159 |
|
71 | |||
160 |
component |
|
72 | component lpp_fifo is | |
161 | port( |
|
73 | generic( | |
162 | clk : in std_logic; |
|
74 | tech : integer := 0; | |
163 | raz : in std_logic; |
|
75 | DataSz : integer range 1 to 32 := 8; | |
164 | Rz : in std_logic; |
|
76 | abits : integer range 2 to 12 := 8 | |
165 | rstf : out std_logic |
|
|||
166 | ); |
|
77 | ); | |
167 | end component; |
|
78 | port( | |
168 | --===========================================================| |
|
79 | rstn : in std_logic; | |
169 | --================= Demi FIFO Ecriture ======================| |
|
80 | rclk : in std_logic; | |
170 | --===========================================================| |
|
81 | ren : in std_logic; | |
171 |
|
82 | rdata : out std_logic_vector(DataSz-1 downto 0); | ||
172 | component APB_FifoWrite is |
|
83 | empty : out std_logic; | |
173 | generic ( |
|
84 | raddr : out std_logic_vector(abits-1 downto 0); | |
174 | pindex : integer := 0; |
|
85 | wclk : in std_logic; | |
175 | paddr : integer := 0; |
|
86 | wen : in std_logic; | |
176 | pmask : integer := 16#fff#; |
|
87 | wdata : in std_logic_vector(DataSz-1 downto 0); | |
177 | pirq : integer := 0; |
|
88 | full : out std_logic; | |
178 | abits : integer := 8; |
|
89 | waddr : out std_logic_vector(abits-1 downto 0) | |
179 | Data_sz : integer := 16; |
|
90 | ); | |
180 | Addr_sz : integer := 8; |
|
|||
181 | addr_max_int : integer := 256); |
|
|||
182 | port ( |
|
|||
183 | clk : in std_logic; |
|
|||
184 | rst : in std_logic; |
|
|||
185 | apbi : in apb_slv_in_type; |
|
|||
186 | ReadEnable : in std_logic; |
|
|||
187 | Empty : out std_logic; |
|
|||
188 | Full : out std_logic; |
|
|||
189 | DATA : out std_logic_vector(Data_sz-1 downto 0); |
|
|||
190 | apbo : out apb_slv_out_type |
|
|||
191 | ); |
|
|||
192 | end component; |
|
91 | end component; | |
193 |
|
92 | |||
194 |
|
93 | component ssram_plugin is | ||
195 | --component Top_FifoWrite is |
|
94 | generic (tech : integer := 0); | |
196 | -- generic( |
|
95 | port | |
197 | -- Data_sz : integer := 16; |
|
96 | ( | |
198 | -- Addr_sz : integer := 8; |
|
97 | clk : in std_logic; | |
199 | -- addr_max_int : integer := 256); |
|
98 | mem_ctrlr_o : in memory_out_type; | |
200 | -- port( |
|
99 | SSRAM_CLK : out std_logic; | |
201 |
|
|
100 | nBWa : out std_logic; | |
202 |
|
|
101 | nBWb : out std_logic; | |
203 |
|
|
102 | nBWc : out std_logic; | |
204 |
|
|
103 | nBWd : out std_logic; | |
205 | -- Data_in : in std_logic_vector(Data_sz-1 downto 0); |
|
104 | nBWE : out std_logic; | |
206 | -- Raddr : in std_logic_vector(addr_sz-1 downto 0); |
|
105 | nADSC : out std_logic; | |
207 |
|
|
106 | nADSP : out std_logic; | |
208 |
|
|
107 | nADV : out std_logic; | |
209 | -- Waddr : out std_logic_vector(addr_sz-1 downto 0); |
|
108 | nGW : out std_logic; | |
210 | -- Data_out : out std_logic_vector(Data_sz-1 downto 0) |
|
109 | nCE1 : out std_logic; | |
211 | -- ); |
|
110 | CE2 : out std_logic; | |
212 | --end component; |
|
111 | nCE3 : out std_logic; | |
213 |
|
112 | nOE : out std_logic; | ||
214 | --===========================================================| |
|
113 | MODE : out std_logic; | |
215 | --================== Demi FIFO Lecture ======================| |
|
114 | ZZ : out std_logic | |
216 | --===========================================================| |
|
115 | ); | |
217 |
|
||||
218 | component APB_FifoRead is |
|
|||
219 | generic ( |
|
|||
220 | pindex : integer := 0; |
|
|||
221 | paddr : integer := 0; |
|
|||
222 | pmask : integer := 16#fff#; |
|
|||
223 | pirq : integer := 0; |
|
|||
224 | abits : integer := 8; |
|
|||
225 | Data_sz : integer := 16; |
|
|||
226 | Addr_sz : integer := 8; |
|
|||
227 | addr_max_int : integer := 256); |
|
|||
228 | port ( |
|
|||
229 | clk : in std_logic; |
|
|||
230 | rst : in std_logic; |
|
|||
231 | apbi : in apb_slv_in_type; |
|
|||
232 | WriteEnable : in std_logic; |
|
|||
233 | RE : out std_logic; |
|
|||
234 | Full : out std_logic; |
|
|||
235 | Empty : out std_logic; |
|
|||
236 | DATA : in std_logic_vector(Data_sz-1 downto 0); |
|
|||
237 | dataTEST : out std_logic_vector(Data_sz-1 downto 0); |
|
|||
238 | apbo : out apb_slv_out_type |
|
|||
239 | ); |
|
|||
240 | end component; |
|
116 | end component; | |
241 |
|
117 | |||
242 |
|
||||
243 | --component Top_FifoRead is |
|
|||
244 | -- generic( |
|
|||
245 | -- Data_sz : integer := 16; |
|
|||
246 | -- Addr_sz : integer := 8; |
|
|||
247 | -- addr_max_int : integer := 256); |
|
|||
248 | -- port( |
|
|||
249 | -- clk : in std_logic; |
|
|||
250 | -- raz : in std_logic; |
|
|||
251 | -- flag_RE : in std_logic; |
|
|||
252 | -- flag_WR : in std_logic; |
|
|||
253 | -- Data_in : in std_logic_vector(Data_sz-1 downto 0); |
|
|||
254 | -- Waddr : in std_logic_vector(addr_sz-1 downto 0); |
|
|||
255 | -- full : out std_logic; |
|
|||
256 | -- empty : out std_logic; |
|
|||
257 | -- Raddr : out std_logic_vector(addr_sz-1 downto 0); |
|
|||
258 | -- Data_out : out std_logic_vector(Data_sz-1 downto 0) |
|
|||
259 | -- ); |
|
|||
260 | --end component; |
|
|||
261 |
|
||||
262 | end; |
|
118 | end; |
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1 | NO CONTENT: file was removed |
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NO CONTENT: file was removed |
1 | NO CONTENT: file was removed |
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NO CONTENT: file was removed |
1 | NO CONTENT: file was removed |
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NO CONTENT: file was removed |
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