diff --git a/APB_DEVICES/apb_devices_list.txt b/APB_DEVICES/apb_devices_list.txt --- a/APB_DEVICES/apb_devices_list.txt +++ b/APB_DEVICES/apb_devices_list.txt @@ -10,7 +10,7 @@ device LPP_CNA 7 device LPP_APB_ADC 8 device LPP_CHENILLARD 9 device LPP_IIR_CEL_FILTER 10 -device LPP_FIFO 11 +device LPP_FIFO_PID 11 device LPP_FFT 12 device LPP_MATRIX 13 device LPP_BALISE 14 diff --git a/LPP_drivers/exemples/BenchMatrix/main.c b/LPP_drivers/exemples/BenchMatrix/main.c --- a/LPP_drivers/exemples/BenchMatrix/main.c +++ b/LPP_drivers/exemples/BenchMatrix/main.c @@ -8,52 +8,101 @@ int main() { - int i=0; + int i=0,save; char temp[256]; + //int TblX[10] = {0x11,0x22,0x33,0x04,0x05,0x06,0x07,0x08,0x09,0x0a}; int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100}; int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105}; int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A}; - int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F}; - int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114}; + // int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F}; + // int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114}; int Table[256]; + + FIFO_Device* fifoX = openFIFO(0); DELAY_Device* delay0 = openDELAY(0); UART_Device* uart0 = openUART(0); - FIFO_Device* fifo0 = openFIFO(0); - FIFO_Device* fifo1 = openFIFO(1); - static MATRIX_Device* mspec; - mspec = openMatrix(0); - FIFO_Device* fifoOut = openFIFO(2); + FIFO_Device* fifoIn = openFIFO(1); + MATRIX_Device* mspec = openMatrix(0); + FIFO_Device* fifoOut = openFIFO(2); GPIO_Device* gpio0 = openGPIO(0); - printf("\nDebut Main\n\n"); Setup(delay0,30000000); gpio0->oen = 0x3; gpio0->Dout = 0x0; +/////////////////////////////////////////////////////////////////////////// mspec->Statu = 2; - FillFifo(fifo0,TblB1,256); - FillFifo(fifo1,TblB2,256); + FillFifo(fifoIn,0,TblB1); + FillFifo(fifoIn,1,TblB2); + gpio0->Dout = 0x1; - Delay_ms(delay0,10); - gpio0->Dout = 0x1; - for (i = 0 ; i < 256 ; i++) + while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS { - Table[i] = fifoOut->rwdata; + Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; + i++; } - + save = i; gpio0->Dout = 0x2; - sprintf(temp,"Reels\tImaginaires\n\r"); + + sprintf(temp,"\nReels\tImaginaires\n\r"); uartputs(uart0,temp); - for (i = 0 ; i < 256 ; i+=2) + for (i = 0 ; i < save ; i+=2) { sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]); uartputs(uart0,temp); } + i = 0; + gpio0->Dout = 0x0; - gpio0->Dout = 0x3; +/////////////////////////////////////////////////////////////////////////// + mspec->Statu = 1; + FillFifo(fifoIn,0,TblB1); + gpio0->Dout = 0x1; + Delay_us(delay0,20); + while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS + { + Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; + i++; + } + save = i; + gpio0->Dout = 0x2; + + sprintf(temp,"\nReels\n\r"); + uartputs(uart0,temp); + for (i = 0 ; i < save ; i++) + { + sprintf(temp,"%d\n\r",Table[i]); + uartputs(uart0,temp); + } + i = 0; + gpio0->Dout = 0x0; + +/////////////////////////////////////////////////////////////////////////// + mspec->Statu = 4; + FillFifo(fifoIn,0,TblB1); + FillFifo(fifoIn,1,TblB3); + gpio0->Dout = 0x1; + + while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS + { + Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; + i++; + } + save = i; + gpio0->Dout = 0x2; + + sprintf(temp,"\nReels\tImaginaires\n\r"); + uartputs(uart0,temp); + for (i = 0 ; i < save ; i+=2) + { + sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]); + uartputs(uart0,temp); + } + i = 0; + gpio0->Dout = 0x0; printf("\nFin Main\n\n"); return 0; @@ -65,17 +114,21 @@ int main() - - +/////////////////// Test R/W Fifo OKAI /////////////////////////////////// - - + /*fifoX->FIFOreg[(2*0)+FIFO_RWdata] = 0x11; + Table[1] = fifoX->FIFOreg[(2*0)+FIFO_RWdata]; + printf("data: %x\n",Table[1]); - - - - - + FillFifo(fifoX,0,TblX); + for (i = 1 ; i < 8 ; i++) + { + Table[i] = fifoX->FIFOreg[(2*0)+FIFO_RWdata] & Mask_2hex; + } + printf("data: %x\n",Table[1]); + printf("data: %x\n",Table[2]); + printf("data: %x\n",Table[3]); + printf("data: %x\n",Table[4]);*/ diff --git a/LPP_drivers/exemples/hello/Makefile b/LPP_drivers/exemples/hello/Makefile new file mode 100644 --- /dev/null +++ b/LPP_drivers/exemples/hello/Makefile @@ -0,0 +1,44 @@ +#------------------------------------------------------------------------------ +#-- This file is a part of the LPP VHDL IP LIBRARY +#-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS +#-- +#-- This program is free software; you can redistribute it and/or modify +#-- it under the terms of the GNU General Public License as published by +#-- the Free Software Foundation; either version 3 of the License, or +#-- (at your option) any later version. +#-- +#-- This program is distributed in the hope that it will be useful, +#-- but WITHOUT ANY WARRANTY; without even the implied warranty of +#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +#-- GNU General Public License for more details. +#-- +#-- You should have received a copy of the GNU General Public License +#-- along with this program; if not, write to the Free Software +#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +#------------------------------------------------------------------------------ + +include ../../rules.mk +LIBDIR= +INCPATH = ../../includes +SCRIPTDIR=../../scripts/ +LIBS= +INPUTFILE=main.c +EXEC=hello.bin +OUTBINDIR=bin/ + + +.PHONY:bin + +all:bin + @echo $(EXEC)" file created" + +clean: + rm -f *.{o,a} + + + +help:ruleshelp + @echo " all : makes an executable file called "$(EXEC) + @echo " in "$(OUTBINDIR) + @echo " clean : removes temporary files" + diff --git a/LPP_drivers/exemples/hello/main.c b/LPP_drivers/exemples/hello/main.c new file mode 100644 --- /dev/null +++ b/LPP_drivers/exemples/hello/main.c @@ -0,0 +1,26 @@ +/*------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------------*/ +#include "stdio.h" + + +int main() +{ + printf("hello World\n"); + return 0; +} diff --git a/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.c b/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.c --- a/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.c +++ b/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.c @@ -27,19 +27,18 @@ FIFO_Device* openFIFO(int count) { FIFO_Device* fifo0; - fifo0 = (FIFO_Device*) apbgetdevice(LPP_FIFO,VENDOR_LPP,count); + fifo0 = (FIFO_Device*) apbgetdevice(LPP_FIFO_PID,VENDOR_LPP,count); return fifo0; } -int FillFifo(FIFO_Device* dev,int Tbl[],int A) +int FillFifo(FIFO_Device* dev,int ID,int Tbl[]) { int i=0; - while(i <= A) + while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full) // TANT QUE full a 0 ALORS { - dev->rwdata = Tbl[i]; + dev->FIFOreg[(2*ID)+FIFO_RWdata] = Tbl[i]; i++; } - return 0; } diff --git a/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.h b/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.h --- a/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.h +++ b/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.h @@ -28,12 +28,15 @@ This library is written to work with LPP_APB_FIFO VHDL module from LPP's FreeVHDLIB. It represents a standard FIFO working, used in many type of application. + \todo Check "DEVICE1 => count = 2" function Open \author Martin Morlot martin.morlot@lpp.polytechnique.fr */ -#define FIFO_Empty 0x00000100 /**< Show that the FIFO is Empty */ -#define FIFO_Full 0x00001000 /**< Show that the FIFO is Full */ -#define Boucle 0x00110000 /**< Configuration for reused the same value of the FIFO */ -#define NoBoucle 0xFFEEFFFF /**< Unlock the previous configuration */ +#define FIFO_Ctrl 0 +#define FIFO_RWdata 1 +#define FIFO_Full 0x00010000 +#define FIFO_Empty 0x00000001 +#define Mask_2hex 0x000000FF +#define Mask_4hex 0x0000FFFF /*=================================================== @@ -45,18 +48,9 @@ */ struct APB_FIFO_REG { - int rwdata; /**< \brief Data register Write/Read */ - int raddr; /**< \brief Address register for the reading operation */ - int cfgreg; /**< \brief Configuration register composed of Read enable Flag [HEX 0] - Write enable Flag [HEX 1] - Empty Flag [HEX 2] - Full Flag [HEX 3] - ReUse Flag [HEX 4] - Lock Flag [HEX 5] - Dummy "C" [HEX 6/7] */ - int dummy0; /**< \brief Unused register, aesthetic interest */ - int dummy1; /**< \brief Unused register, aesthetic interest */ - int waddr; /**< \brief Address register for the writing operation */ + int IDreg; + int FIFOreg[2*8]; + }; typedef volatile struct APB_FIFO_REG FIFO_Device; @@ -75,16 +69,6 @@ typedef volatile struct APB_FIFO_REG FIF \return The pointer to the device. */ FIFO_Device* openFIFO(int count); - -/*! \fn int FillFifo(FIFO_Device* dev,int Tbl[],int A); - \brief a Fill in FIFO function. - - This Function fill in the FIFO with a table data. - - \param dev The FFT pointer. - \param Tbl[] The data table. - \param A The data table size. -*/ -int FillFifo(FIFO_Device* dev,int Tbl[],int A); +int FillFifo(FIFO_Device* dev,int ID,int Tbl[]); #endif diff --git a/LPP_drivers/scripts/load.txt b/LPP_drivers/scripts/load.txt --- a/LPP_drivers/scripts/load.txt +++ b/LPP_drivers/scripts/load.txt @@ -1,1 +1,1 @@ -load bin/BenchFIFO.bin +load bin/hello.bin diff --git a/lib/lpp/lpp_memory/APB_FIFO.vhd b/lib/lpp/lpp_memory/APB_FIFO.vhd --- a/lib/lpp/lpp_memory/APB_FIFO.vhd +++ b/lib/lpp/lpp_memory/APB_FIFO.vhd @@ -16,11 +16,15 @@ -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr ------------------------------------------------------------------------------ +-- APB_FIFO.vhd library ieee; use ieee.std_logic_1164.all; +use IEEE.numeric_std.all; +library techmap; +use techmap.gencomp.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; @@ -30,59 +34,242 @@ use lpp.lpp_amba.all; use lpp.apb_devices_list.all; use lpp.lpp_memory.all; ---! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba entity APB_FIFO is - generic ( +generic ( + tech : integer := apa3; pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; pirq : integer := 0; - abits : integer := 8; + abits : integer := 8; + FifoCnt : integer := 2; Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); + Addr_sz : integer := 9; + R : integer := 1; + W : integer := 1 + ); port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - Full : out std_logic; - Empty : out std_logic; - WR : out std_logic; - RE : out std_logic; - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + rclk : in std_logic; + wclk : in std_logic; + REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mémoire + WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'écriture en mémoire + Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire vide + Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire pleine + RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en entrée + WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en sortie + WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (écriture) + RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) + apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); -end APB_FIFO; - +end entity; architecture ar_APB_FIFO of APB_FIFO is -signal ReadEnable : std_logic; -signal WriteEnable : std_logic; -signal FlagEmpty : std_logic; -signal FlagFull : std_logic; ---signal ReUse : std_logic; ---signal Lock : std_logic; -signal RstMem : std_logic; -signal DataIn : std_logic_vector(Data_sz-1 downto 0); -signal DataOut : std_logic_vector(Data_sz-1 downto 0); -signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); -signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); +constant REVISION : integer := 1; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0), + 1 => apb_iobar(paddr, pmask)); + +type FIFO_ctrlr_Reg is record + FIFO_Ctrl : std_logic_vector(31 downto 0); + FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0); + FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0); +end record; + +type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg; +type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0); +type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0); + +signal Rec : FIFO_ctrlr_Reg_Vec; +signal PRdata : std_logic_vector(31 downto 0); +signal FIFO_ID : std_logic_vector(31 downto 0); +signal autoloaded : std_logic_vector(FifoCnt-1 downto 0); +signal sFull : std_logic_vector(FifoCnt-1 downto 0); +signal sEmpty : std_logic_vector(FifoCnt-1 downto 0); +signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0); +signal sWen : std_logic_vector(FifoCnt-1 downto 0); +signal sRen : std_logic_vector(FifoCnt-1 downto 0); +signal sRclk : std_logic; +signal sWclk : std_logic; +signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0); +signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0); +signal sRDATA : fifodatabus; +signal sWDATA : fifodatabus; +signal sWADDR : fifoaddressbus; +signal sRADDR : fifoaddressbus; + +type state_t is (idle,Read); +signal fiforeadfsmst : state_t; begin - APB : ApbDriver - generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,RstMem,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); +FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4)); +FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8)); +FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8)); + + +Write : if W /= 0 generate + FIFO_ID(4) <= '1'; + sWen <= sWen_APB; + sWclk <= clk; + Wrapb: for i in 0 to FifoCnt-1 generate + sWDATA(i) <= Rec(i).FIFO_Wdata; + end generate; +end generate; + +Writeext : if W = 0 generate + FIFO_ID(4) <= '0'; + sWen <= WEN; + sWclk <= Wclk; + Wrext: for i in 0 to FifoCnt-1 generate + sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i); + end generate; +end generate; + +Read : if R /= 0 generate + FIFO_ID(5) <= '1'; + sRen <= sRen_APB; + srclk <= clk; + Rdapb: for i in 0 to FifoCnt-1 generate + Rec(i).FIFO_Rdata <= sRDATA(i); + end generate; +end generate; + +Readext : if R = 0 generate + FIFO_ID(5) <= '0'; + sRen <= REN; + srclk <= rclk; + Drext: for i in 0 to FifoCnt-1 generate + RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i) <= sRDATA(i); + end generate; +end generate; + +ctrlregs: for i in 0 to FifoCnt-1 generate + RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i); + WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i); + Rec(i).FIFO_Ctrl(16) <= sFull(i); + Rec(i).FIFO_Ctrl(Addr_sz downto 1) <= sRADDR(i); + Rec(i).FIFO_Ctrl((Addr_sz+16) downto 17) <= sWADDR(i); ---|free|Waddrs|Full||free|Raddrs|empty| +end generate; -- 31 17 16 15 1 0 + +Empty <= sEmpty; +Full <= sFull; - DEVICE : Top_FIFO - generic map(Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,RstMem,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); +fifos: for i in 0 to FifoCnt-1 generate + FIFO0 : lpp_fifo + generic map (tech,Data_sz,Addr_sz) + port map(rst,srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i)); +end generate; + + process(rst,clk) + begin + if(rst='0')then + rstloop1: for i in 0 to FifoCnt-1 loop + Rec(i).FIFO_Wdata <= (others => '0'); + sWen_APB(i) <= '1'; + end loop; + elsif(clk'event and clk='1')then + --APB Write OP + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + writelp: for i in 0 to FifoCnt-1 loop + if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then + Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0); + sWen_APB(i) <= '0'; + end if; + end loop; + else + sWen_APB <= (others =>'1'); + end if; + --APB Read OP + if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then + if(apbi.paddr(abits-1 downto 2)="000000") then + PRdata <= FIFO_ID; + else + readlp: for i in 0 to FifoCnt-1 loop + if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then + PRdata <= Rec(i).FIFO_Ctrl; + elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then + PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata; + end if; + end loop; + end if; + end if; + end if; + apbo.pconfig <= pconfig; +end process; +apbo.prdata <= PRdata when apbi.penable = '1'; + + -Empty <= FlagEmpty; -Full <= FlagFull; -WR <= WriteEnable; -RE <= ReadEnable; +process(rst,clk) + begin + if(rst='0')then + fiforeadfsmst <= idle; + rstloop: for i in 0 to FifoCnt-1 loop + sRen_APB(i) <= '1'; + autoloaded(i) <= '1'; + Rec(i).FIFO_Ctrl(0) <= sEmpty(i); + end loop; + elsif clk'event and clk = '1' then + sEmpty_d <= sEmpty; + case fiforeadfsmst is + when idle => + idlelp: for i in 0 to FifoCnt-1 loop + if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then + if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then + autoloaded(i) <= '0'; + else + autoloaded(i) <= '1'; + end if; + sRen_APB(i) <= '0'; + fiforeadfsmst <= read; + Rec(i).FIFO_Ctrl(0) <= sEmpty(i); + else + sRen_APB(i) <= '1'; + end if; + end loop; + when read => + sRen_APB <= (others => '1'); + fiforeadfsmst <= idle; + when others => + fiforeadfsmst <= idle; + end case; + end if; +end process; -end ar_APB_FIFO; \ No newline at end of file + +end ar_APB_FIFO; + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_memory/APB_FifoRead.vhd b/lib/lpp/lpp_memory/APB_FifoRead.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/APB_FifoRead.vhd +++ /dev/null @@ -1,91 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library lpp; -use lpp.lpp_amba.all; -use lpp.apb_devices_list.all; -use lpp.lpp_memory.all; - ---! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba - -entity APB_FifoRead is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - WriteEnable : in std_logic; --! Demande d'écriture dans la mémoire, géré hors de l'IP - RE : out std_logic; - Full : out std_logic; --! Flag, Memoire pleine - Empty : out std_logic; --! Flag, Memoire vide - DATA : in std_logic_vector(Data_sz-1 downto 0); --! Données en entrée de la mémoire - dataTEST : out std_logic_vector(Data_sz-1 downto 0); - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus - ); -end APB_FifoRead; - ---! @details Gestion de la FIFO, écriture via le bus APB, lecture interne au FPGA - -architecture ar_APB_FifoRead of APB_FifoRead is - -signal Low : std_logic:='0'; -signal ReadEnable : std_logic; -signal FlagEmpty : std_logic; -signal FlagFull : std_logic; ---signal ReUse : std_logic; ---signal Lock : std_logic; -signal RstMem : std_logic; -signal DataIn : std_logic_vector(Data_sz-1 downto 0); -signal DataOut : std_logic_vector(Data_sz-1 downto 0); -signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); -signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); - -begin - - APB : ApbDriver - generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,RstMem,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); - - - FIFO : Top_FIFO - generic map(Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,RstMem,DATA,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); - -Empty <= FlagEmpty; -Full <= FlagFull; -RE <= ReadEnable; -dataTEST <= DataOut; - -end ar_APB_FifoRead; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/APB_FifoWrite.vhd b/lib/lpp/lpp_memory/APB_FifoWrite.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/APB_FifoWrite.vhd +++ /dev/null @@ -1,88 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library lpp; -use lpp.lpp_amba.all; -use lpp.apb_devices_list.all; -use lpp.lpp_memory.all; - ---! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba - -entity APB_FifoWrite is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - ReadEnable : in std_logic; --! Demande de lecture de la mémoire, géré hors de l'IP - Empty : out std_logic; --! Flag, Memoire vide - Full : out std_logic; --! Flag, Memoire pleine - DATA : out std_logic_vector(Data_sz-1 downto 0); --! Données en sortie de la mémoire - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus - ); -end APB_FifoWrite; - ---! @details Gestion de la FIFO, écriture via le bus APB, lecture interne au FPGA - -architecture ar_APB_FifoWrite of APB_FifoWrite is - -signal Low : std_logic:='0'; -signal WriteEnable : std_logic; -signal FlagEmpty : std_logic; -signal FlagFull : std_logic; ---signal ReUse : std_logic; ---signal Lock : std_logic; -signal RstMem : std_logic; -signal DataIn : std_logic_vector(Data_sz-1 downto 0); -signal DataOut : std_logic_vector(Data_sz-1 downto 0); -signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); -signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); - -begin - - APB : ApbDriver - generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,RstMem,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); - - - FIFO : Top_FIFO - generic map(Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,RstMem,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); - -DATA <= DataOut; -Empty <= FlagEmpty; -Full <= FlagFull; - -end ar_APB_FifoWrite; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/ApbDriver.vhd b/lib/lpp/lpp_memory/ApbDriver.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/ApbDriver.vhd +++ /dev/null @@ -1,173 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library lpp; -use lpp.lpp_amba.all; -use lpp.apb_devices_list.all; - ---! Driver APB "Générique" qui va faire le lien entre le bus Amba et la FIFO - -entity ApbDriver is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - LPP_DEVICE : integer; - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - ReadEnable : out std_logic; --! Instruction de lecture en mémoire - WriteEnable : out std_logic; --! Instruction d'écriture en mémoire - FlagEmpty : in std_logic; --! Flag, Mémoire vide - FlagFull : in std_logic; --! Flag, Mémoire pleine --- ReUse : out std_logic; --! Flag, Permet de relire la mémoire en boucle sans nouvelle données --- Lock : out std_logic; --! Flag, Permet de bloquer l'écriture dans la mémoire - RstMem : out std_logic; --! Flag, Reset "manuel" spécifique au composant - DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de données en entrée - DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de données en sortie - AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (écriture) - AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture) - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus - ); -end ApbDriver; - ---! @details Utilisable avec n'importe quelle IP VHDL de type FIFO - -architecture ar_ApbDriver of ApbDriver is - -constant REVISION : integer := 1; - -constant pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0), - 1 => apb_iobar(paddr, pmask)); - -type DEVICE_ctrlr_Reg is record - DEVICE_Cfg : std_logic_vector(4 downto 0); - DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0); - DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0); - DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0); - DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0); -end record; - -signal Rec : DEVICE_ctrlr_Reg; -signal Rdata : std_logic_vector(31 downto 0); - -signal FlagRE : std_logic; -signal FlagWR : std_logic; - -begin - -Rec.DEVICE_Cfg(2) <= FlagRE; -Rec.DEVICE_Cfg(1) <= FlagWR; -Rec.DEVICE_Cfg(3) <= FlagEmpty; -Rec.DEVICE_Cfg(4) <= FlagFull; ---ReUse <= Rec.DEVICE_Cfg(4); ---Lock <= Rec.DEVICE_Cfg(5); -RstMem <= Rec.DEVICE_Cfg(0); - -DataIn <= Rec.DEVICE_DataW; -Rec.DEVICE_DataR <= DataOut; -Rec.DEVICE_AddrW <= AddrIn; -Rec.DEVICE_AddrR <= AddrOut; - - - - process(rst,clk) - begin - if(rst='0')then - Rec.DEVICE_DataW <= (others => '0'); - FlagWR <= '0'; - FlagRE <= '0'; - Rec.DEVICE_Cfg(0) <= '0'; --- Rec.DEVICE_Cfg(5) <= '0'; --- Rec.DEVICE_Cfg(7) <= '0'; - - elsif(clk'event and clk='1')then - - --APB Write OP - if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => - FlagWR <= '1'; - Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0); - when "000010" => - Rec.DEVICE_Cfg(0) <= apbi.pwdata(0); --- Rec.DEVICE_Cfg(5) <= apbi.pwdata(20); --- Rec.DEVICE_Cfg(6) <= apbi.pwdata(24); - when others => - null; - end case; - else - FlagWR <= '0'; - end if; - - --APB Read OP - if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => - if(apbi.penable = '1')then - FlagRE <= '1'; - end if; - Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR; - when "000001" => --- Rdata(31 downto 8) <= X"AAAAAA"; - Rdata(Addr_sz-1 downto 0) <= Rec.DEVICE_AddrR; - when "000101" => --- Rdata(31 downto 8) <= X"AAAAAA"; - Rdata(Addr_sz-1 downto 0) <= Rec.DEVICE_AddrW; - when "000010" => - Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0); - Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1); - Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2); - Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3); - Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4); --- Rdata(31 downto 28) <= "000" & Rec.DEVICE_Cfg(7); --- Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5); --- Rdata(27 downto 24) <= "000" & Rec.DEVICE_Cfg(6); - Rdata(31 downto 20) <= X"CCC"; - when others => - Rdata <= (others => '0'); - end case; - else - FlagRE <= '0'; - end if; - - end if; - apbo.pconfig <= pconfig; - end process; - -apbo.prdata <= Rdata when apbi.penable = '1'; -WriteEnable <= FlagWR; -ReadEnable <= FlagRE; --when apbi.penable = '1'; - -end ar_ApbDriver; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/ApbFifoDriverV.vhd b/lib/lpp/lpp_memory/ApbFifoDriverV.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_memory/ApbFifoDriverV.vhd @@ -0,0 +1,186 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library lpp; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; + +--! Driver APB "Générique" qui va faire le lien entre le bus Amba et la FIFO + +entity ApbFifoDriverV is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + LPP_DEVICE : integer; + FifoCnt : integer := 1; + Data_sz : integer := 16; + Addr_sz : integer := 8; + addr_max_int : integer := 256); + port ( + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + ReadEnable : out std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mémoire + WriteEnable : out std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'écriture en mémoire + FlagEmpty : in std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire vide + FlagFull : in std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire pleine + ReUse : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Permet de relire la mémoire du début + Lock : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Permet de bloquer l'écriture dans la mémoire + DataIn : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en entrée + DataOut : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en sortie + AddrIn : in std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (écriture) + AddrOut : in std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) + apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + ); +end ApbFifoDriverV; + +--! @details Utilisable avec n'importe quelle IP VHDL de type FIFO + +architecture ar_ApbFifoDriverV of ApbFifoDriverV is + +constant REVISION : integer := 1; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0), + 1 => apb_iobar(paddr, pmask)); + +type DEVICE_ctrlr_Reg is record + DEVICE_Cfg : std_logic_vector(5 downto 0); + DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0); + DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0); + DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0); + DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0); +end record; + +type DEVICE_ctrlr_RegV is array(FifoCnt-1 downto 0) of DEVICE_ctrlr_Reg; + +signal Rec : DEVICE_ctrlr_RegV; +signal Rdata : std_logic_vector(31 downto 0); + +signal FlagRE : std_logic; +signal FlagWR : std_logic; + +begin + +fifoflags: for i in 0 to FifoCnt-1 generate: + + Rec(i).DEVICE_Cfg(0) <= FlagRE(i); + Rec(i).DEVICE_Cfg(1) <= FlagWR(i); + Rec(i).DEVICE_Cfg(2) <= FlagEmpty(i); + Rec(i).DEVICE_Cfg(3) <= FlagFull(i); + + ReUse(i) <= Rec(i).DEVICE_Cfg(4); + Lock(i) <= Rec(i).DEVICE_Cfg(5); + + DataIn(i*(Data_sz-1 downto 0)) <= Rec(i).DEVICE_DataW; + + Rec(i).DEVICE_DataR <= DataOut(i*(Data_sz-1 downto 0)); + Rec(i).DEVICE_AddrW <= AddrIn(i*(Addr_sz-1 downto 0)); + Rec(i).DEVICE_AddrR <= AddrOut(i*(Addr_sz-1 downto 0)); + + WriteEnable(i) <= FlagWR(i); + ReadEnable(i) <= FlagRE(i); + +end generate; + + + process(rst,clk) + begin + if(rst='0')then + Rec.DEVICE_DataW <= (others => '0'); + FlagWR <= '0'; + FlagRE <= '0'; + Rec.DEVICE_Cfg(4) <= '0'; + Rec.DEVICE_Cfg(5) <= '0'; + + elsif(clk'event and clk='1')then + + --APB Write OP + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + FlagWR <= '1'; + Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0); + when "000010" => + Rec.DEVICE_Cfg(4) <= apbi.pwdata(16); + Rec.DEVICE_Cfg(5) <= apbi.pwdata(20); + when others => + null; + end case; + else + FlagWR <= (others => '0'); + end if; + + --APB Read OP + if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then + case apbi.paddr(abits-1 downto 2) is + for i in 0 to FifoCnt-1 loop + if conv_integer(apbi.paddr(7 downto 3)) = i then + case apbi.paddr(2 downto 2) is + when "0" => + CoefsReg.numCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0)); + when "1" => + CoefsReg.numCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0)); + when others => + end case; + end if; + end loop; + when "000000" => + FlagRE <= '1'; + Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR; + when "000001" => + Rdata(31 downto 8) <= X"AAAAAA"; + Rdata(7 downto 0) <= Rec.DEVICE_AddrR; + when "000101" => + Rdata(31 downto 8) <= X"AAAAAA"; + Rdata(7 downto 0) <= Rec.DEVICE_AddrW; + when "000010" => + Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0); + Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1); + Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2); + Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3); + Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4); + Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5); + Rdata(31 downto 24) <= X"CC"; + when others => + Rdata <= (others => '0'); + end case; + else + FlagRE <= (others => '0'); + end if; + + end if; + apbo.pconfig <= pconfig; + end process; + +apbo.prdata <= Rdata when apbi.penable = '1'; + + +end ar_ApbFifoDriverV; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/Fifo_Read.vhd b/lib/lpp/lpp_memory/Fifo_Read.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/Fifo_Read.vhd +++ /dev/null @@ -1,101 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - ---! Programme de la FIFO de lecture - -entity Fifo_Read is -generic( - Addr_sz : integer := 8; - addr_max_int : integer := 256); -port( - clk,raz : in std_logic; --! Horloge et reset general du composant - flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire --- flag_WR : in std_logic; --- ReUse : in std_logic; --! Flag, Permet de relire la mémoire du début - Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'écriture dans la mémoire - empty : out std_logic; --! Flag, Mémoire vide - Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la mémoire - ); -end Fifo_Read; - ---! @details En aval de la SRAM Gaisler - -architecture ar_Fifo_Read of Fifo_Read is - -signal Rad_int : integer range 0 to addr_max_int; -signal Rad_int_reg : integer range 0 to addr_max_int; -signal Wad_int : integer range 0 to addr_max_int; -signal Wad_int_reg : integer range 0 to addr_max_int; -signal s_empty : std_logic; - -begin - process (clk,raz) - begin - if(raz='0')then - Rad_int <= 0; - s_empty <= '1'; - - elsif(clk' event and clk='1')then - Wad_int_reg <= Wad_int; - Rad_int_reg <= Rad_int; - - - if(flag_RE='1')then - - if(s_empty = '0')then - if(Rad_int=addr_max_int-1)then - Rad_int <= 0; --- elsif(Rad_int=Wad_int-1)then --- Rad_int <= Rad_int+1; --- s_empty <= '1'; - else - Rad_int <= Rad_int+1; - end if; - end if; - - if(Rad_int=Wad_int-1)then - s_empty <= '1'; - elsif(Rad_int=addr_max_int-1 and Wad_int=0)then - s_empty <= '1'; - end if; - - end if; - - - if(Wad_int_reg /= Wad_int)then - if(s_empty='1')then - s_empty <= '0'; - end if; - end if; - - end if; - - end process; - -Wad_int <= to_integer(unsigned(Waddr)); -Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz)); -empty <= s_empty; - -end ar_Fifo_Read; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/Fifo_Write.vhd b/lib/lpp/lpp_memory/Fifo_Write.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/Fifo_Write.vhd +++ /dev/null @@ -1,97 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - ---! Programme de la FIFO d'écriture - -entity Fifo_Write is -generic( - Addr_sz : integer := 8; - addr_max_int : integer := 256); -port( - clk,raz : in std_logic; --! Horloge et reset general du composant - flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire --- flag_RE : in std_logic; - Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la mémoire - full : out std_logic; --! Flag, Mémoire pleine - Waddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre d'écriture dans la mémoire - ); -end Fifo_Write; - ---! @details En amont de la SRAM Gaisler - -architecture ar_Fifo_Write of Fifo_Write is - -signal Wad_int : integer range 0 to addr_max_int; -signal Wad_int_reg : integer range 0 to addr_max_int; -signal Rad_int : integer range 0 to addr_max_int; -signal Rad_int_reg : integer range 0 to addr_max_int; -signal s_full : std_logic; - -begin - process (clk,raz) - begin - if(raz='0')then - Wad_int <= 0; - s_full <= '0'; - - elsif(clk' event and clk='1')then - Wad_int_reg <= Wad_int; - Rad_int_reg <= Rad_int; - - if(flag_WR='1')then - - if(s_full = '0')then - if(Wad_int=addr_max_int-1)then - Wad_int <= 0; --- elsif(Wad_int=Rad_int-1)then --- Wad_int <= Wad_int+1; --- s_full <= '1'; - else - Wad_int <= Wad_int+1; - end if; - end if; - - if(Wad_int=Rad_int-1)then - s_full <= '1'; - elsif(Wad_int=addr_max_int-1 and Rad_int=0)then - s_full <= '1'; - end if; - - end if; - - if(Rad_int_reg /= Rad_int)then - if(s_full='1')then - s_full <= '0'; - end if; - end if; - - end if; - end process; - -Rad_int <= to_integer(unsigned(Raddr)); -Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz)); -full <= s_full; - -end ar_Fifo_Write; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/LocalReset.vhd b/lib/lpp/lpp_memory/LocalReset.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/LocalReset.vhd +++ /dev/null @@ -1,70 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, Write_int to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr -------------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; - -entity LocalReset is - port( - clk : in std_logic; - raz : in std_logic; - Rz : in std_logic; - rstf : out std_logic - ); -end LocalReset; - - -architecture ar_LocalReset of LocalReset is - -signal Rz_reg : std_logic; - -type state is (st0); -signal ect : state; - -begin - process(clk,raz) - begin - - if(raz='0')then - rstf <= '0'; - ect <= st0; - - elsif(clk'event and clk='1')then - Rz_reg <= Rz; - - case ect is - - when st0 => - rstf <= '1'; - if(Rz_reg='0' and Rz='1')then - rstf <= '0'; - ect <= st0; - elsif(Rz_reg='1' and Rz='0')then - rstf <= '0'; - ect <= st0; - end if; - - end case; - end if; - end process; - -end ar_LocalReset; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/Pipeline.vhd b/lib/lpp/lpp_memory/Pipeline.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/Pipeline.vhd +++ /dev/null @@ -1,115 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.FIFO_Config.all; - ---! Programme qui va permettre de "pipeliner" la FIFO, donnée disponible en sortie dé son écriture en entrée de la FIFO - -entity PipeLine is -generic(Data_sz : integer := 16); -port( - clk,raz : in std_logic; --! Horloge et reset general du composant - Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Donnée en entrée de la FIFO, coté écriture - flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire - flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire - empty : in std_logic; --! Flag, Mémoire vide - Data_svg : out std_logic_vector(Data_sz-1 downto 0); - Data1 : out std_logic; - Data2 : out std_logic - ); -end PipeLine; - -architecture ar_PipeLine of PipeLine is - -type etat is (e0,e1,e2,st0,st1,st2); -signal ect : etat; - -begin - process (clk,raz) - begin - if(raz='0')then - Data1 <= '0'; - Data2 <= '0'; - ect <= e0; - - elsif(clk' event and clk='1')then - Data_svg <= Data_in; - - case ect is - when e0 => - Data2 <= '0'; - if(flag_WR='1')then - Data1 <= '1'; - ect <= st2; - end if; - - when st2 => - Data1 <= '0'; - ect <= e1; - - when e1 => - if(flag_RE='1')then - ect <= st0; - end if; - - when st0 => - ect <= st1; - - when st1 => - Data2 <= '1'; - ect <= e2; - - - when e2 => - if(empty='1')then - ect <= e0; - else - ect <= e2; - end if; - - - end case; - end if; - end process; - -end ar_PipeLine; - - - - - - - - - - - - - - - - - - - diff --git a/lib/lpp/lpp_memory/SSRAM_plugin.vhd b/lib/lpp/lpp_memory/SSRAM_plugin.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_memory/SSRAM_plugin.vhd @@ -0,0 +1,184 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2011, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +library gaisler; +use gaisler.misc.all; +use gaisler.memctrl.all; +library techmap; +use techmap.gencomp.all; +use techmap.allclkgen.all; + + + + +entity ssram_plugin is +generic (tech : integer := 0); +port +( + clk : in std_logic; + mem_ctrlr_o : in memory_out_type; + SSRAM_CLK : out std_logic; + nBWa : out std_logic; + nBWb : out std_logic; + nBWc : out std_logic; + nBWd : out std_logic; + nBWE : out std_logic; + nADSC : out std_logic; + nADSP : out std_logic; + nADV : out std_logic; + nGW : out std_logic; + nCE1 : out std_logic; + CE2 : out std_logic; + nCE3 : out std_logic; + nOE : out std_logic; + MODE : out std_logic; + ZZ : out std_logic +); +end entity; + + + + + + +architecture ar_ssram_plugin of ssram_plugin is + + +signal nADSPint : std_logic:='1'; +signal nOEint : std_logic:='1'; +signal RAMSN_reg: std_logic:='1'; +signal OEreg : std_logic:='1'; +signal nBWaint : std_logic:='1'; +signal nBWbint : std_logic:='1'; +signal nBWcint : std_logic:='1'; +signal nBWdint : std_logic:='1'; +signal nBWEint : std_logic:='1'; +signal nCE1int : std_logic:='1'; +signal CE2int : std_logic:='0'; +signal nCE3int : std_logic:='1'; + +Type stateT is (idle,st1,st2,st3,st4); +signal state : stateT; + +begin + +process(clk , mem_ctrlr_o.RAMSN(0)) +begin + if mem_ctrlr_o.RAMSN(0) ='1' then + state <= idle; + elsif clk ='1' and clk'event then + case state is + when idle => + state <= st1; + when st1 => + state <= st2; + when st2 => + state <= st3; + when st3 => + state <= st4; + when st4 => + state <= st1; + end case; + end if; +end process; + +ssram_clk_pad : outpad generic map (tech => tech) + port map (SSRAM_CLK,not clk); + + +nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0); +nBWa_pad : outpad generic map (tech => tech) + port map (nBWa,nBWaint); + +nBWbint <= mem_ctrlr_o.WRN(2)or mem_ctrlr_o.ramsn(0); +nBWb_pad : outpad generic map (tech => tech) + port map (nBWb, nBWbint); + +nBWcint <= mem_ctrlr_o.WRN(1)or mem_ctrlr_o.ramsn(0); +nBWc_pad : outpad generic map (tech => tech) + port map (nBWc, nBWcint); + +nBWdint <= mem_ctrlr_o.WRN(0)or mem_ctrlr_o.ramsn(0); +nBWd_pad : outpad generic map (tech => tech) + port map (nBWd, nBWdint); + +nBWEint <= mem_ctrlr_o.WRITEN or mem_ctrlr_o.ramsn(0); +nBWE_pad : outpad generic map (tech => tech) + port map (nBWE, nBWEint); + +nADSC_pad : outpad generic map (tech => tech) + port map (nADSC, '1'); + +--nADSPint <= not((RAMSN_reg xor mem_ctrlr_o.RAMSN(0)) and RAMSN_reg); +nADSPint <= '0' when state = st1 else '1'; + +process(clk) +begin + if clk'event and clk = '1' then + RAMSN_reg <= mem_ctrlr_o.RAMSN(0); + end if; +end process; + +nADSP_pad : outpad generic map (tech => tech) + port map (nADSP, nADSPint); + +nADV_pad : outpad generic map (tech => tech) + port map (nADV, '1'); + +nGW_pad : outpad generic map (tech => tech) + port map (nGW, '1'); + +nCE1int <= nADSPint or mem_ctrlr_o.address(31) or (not mem_ctrlr_o.address(30)) or mem_ctrlr_o.address(29) or mem_ctrlr_o.address(28); +CE2int <= (not mem_ctrlr_o.address(27)) and (not mem_ctrlr_o.address(26)) and (not mem_ctrlr_o.address(25)) and (not mem_ctrlr_o.address(24)); +nCE3int <= mem_ctrlr_o.address(23) or mem_ctrlr_o.address(22) or mem_ctrlr_o.address(21) or mem_ctrlr_o.address(20); + +nCE1_pad : outpad generic map (tech => tech) + port map (nCE1, nCE1int); + +CE2_pad : outpad generic map (tech => tech) + port map (CE2, CE2int); + +nCE3_pad : outpad generic map (tech => tech) + port map (nCE3, nCE3int); + +nOE_pad : outpad generic map (tech => tech) + port map (nOE, nOEint); + +process(clk) +begin + if clk'event and clk = '1' then + OEreg <= mem_ctrlr_o.OEN; + end if; +end process; + + +--nOEint <= OEreg or mem_ctrlr_o.RAMOEN(0); +nOEint <= '0' when state = st2 or state = st3 or state = st4 else '1'; + +MODE_pad : outpad generic map (tech => tech) + port map (MODE, '0'); + +ZZ_pad : outpad generic map (tech => tech) + port map (ZZ, '0'); + +end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/Top_FIFO.vhd b/lib/lpp/lpp_memory/Top_FIFO.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/Top_FIFO.vhd +++ /dev/null @@ -1,118 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -library techmap; -use techmap.gencomp.all; -use work.config.all; -use lpp.lpp_memory.all; - ---! Programme de la FIFO - -entity Top_FIFO is - generic( - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256 - ); - port( - clk,raz : in std_logic; --! Horloge et reset general du composant - flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire - flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire - RstMem : in std_logic; - Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrée du composant - Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'écriture - Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture - full : out std_logic; --! Flag, Mémoire pleine - empty : out std_logic; --! Flag, Mémoire vide - Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant - ); -end Top_FIFO; - ---! @details Une mémoire SRAM de chez Gaisler est utilisée, ---! associée a deux Drivers, un pour écrire l'autre pour lire cette mémoire - -architecture ar_Top_FIFO of Top_FIFO is - -component syncram_2p - generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0); - port ( - rclk : in std_ulogic; - renable : in std_ulogic; - raddress : in std_logic_vector((abits -1) downto 0); - dataout : out std_logic_vector((dbits -1) downto 0); - wclk : in std_ulogic; - write : in std_ulogic; - waddress : in std_logic_vector((abits -1) downto 0); - datain : in std_logic_vector((dbits -1) downto 0)); -end component; - -signal Raddr : std_logic_vector(addr_sz-1 downto 0); -signal Waddr : std_logic_vector(addr_sz-1 downto 0); -signal Data_int : std_logic_vector(Data_sz-1 downto 0); -signal Data_svg : std_logic_vector(Data_sz-1 downto 0); -signal s_empty : std_logic; -signal s_full : std_logic; -signal Data1 : std_logic; -signal Data2 : std_logic; -signal s_flag_RE : std_logic; -signal s_flag_WR : std_logic; -signal rstf : std_logic; - -begin - - Reset : entity LocalReset - port map(clk,raz,RstMem,rstf); - - WR : entity Fifo_Write - generic map(Addr_sz,addr_max_int) - port map(clk,rstf,s_flag_WR,Raddr,s_full,Waddr); - - SRAM : syncram_2p - generic map(CFG_MEMTECH,Addr_sz,Data_sz) - port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in); - - RE : entity Fifo_Read - generic map(Addr_sz,addr_max_int) - port map(clk,rstf,s_flag_RE,Waddr,s_empty,Raddr); - - PIPE : entity PipeLine - generic map(Data_sz) - port map(clk,rstf,Data_in,s_flag_RE,s_flag_WR,s_empty,Data_svg,Data1,Data2); - - -Data_out <= Data_svg when Data1='1' else - Data_int when Data2='1'; - -full <= s_full; -empty <= s_empty; -Addr_RE <= Raddr; -Addr_WR <= Waddr; - -s_flag_WR <= Flag_WR when s_full='0' else - '0'; - -s_flag_RE <= Flag_RE when s_empty='0' else - '0'; - -end ar_Top_FIFO; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/lpp_FIFO.vhd b/lib/lpp/lpp_memory/lpp_FIFO.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_memory/lpp_FIFO.vhd @@ -0,0 +1,158 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use lpp.lpp_memory.all; +library techmap; +use techmap.gencomp.all; + +entity lpp_fifo is +generic( + tech : integer := 0; + DataSz : integer range 1 to 32 := 8; + abits : integer range 2 to 12 := 8 + ); +port( + rstn : in std_logic; + rclk : in std_logic; + ren : in std_logic; + rdata : out std_logic_vector(DataSz-1 downto 0); + empty : out std_logic; + raddr : out std_logic_vector(abits-1 downto 0); + wclk : in std_logic; + wen : in std_logic; + wdata : in std_logic_vector(DataSz-1 downto 0); + full : out std_logic; + waddr : out std_logic_vector(abits-1 downto 0) +); +end entity; + + +architecture ar_lpp_fifo of lpp_fifo is + +signal sFull : std_logic:='0'; +signal sEmpty : std_logic:='1'; +signal sREN : std_logic:='0'; +signal sWEN : std_logic:='0'; + +signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0'); +signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0'); +signal Waddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0'); +signal Raddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0'); + +begin + +SRAM : syncram_2p +generic map(tech,abits,DataSz) +port map(RCLK,sREN,Raddr_vect,rdata,WCLK,sWEN,Waddr_vect,wdata); + +--RAM0: entity work.RAM_CEL +-- generic map(abits, DataSz) +-- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, RCLK, WCLK, rstn); + + +--============================= +-- Read section +--============================= +sREN <= not REN and not sempty; + +process (rclk,rstn) +begin + if(rstn='0')then + Raddr_vect <= (others =>'0'); + Raddr_vect_d <= (others =>'1'); + sempty <= '1'; + elsif(rclk'event and rclk='1')then + if(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then + sempty <= '1'; + elsif(Raddr_vect/=Waddr_vect) then + sempty <= '0'; + end if; + if(sREN='1' and sempty = '0') then + Raddr_vect <= std_logic_vector(unsigned(Raddr_vect) + 1); + Raddr_vect_d <= Raddr_vect; + end if; + + end if; +end process; + +--============================= +-- Write section +--============================= +sWEN <= not WEN and not sfull; + +process (wclk,rstn) +begin + if(rstn='0')then + Waddr_vect <= (others =>'0'); + Waddr_vect_d <= (others =>'1'); + sfull <= '0'; + elsif(wclk'event and wclk='1')then + if(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then + sfull <= '1'; + elsif(Raddr_vect/=Waddr_vect) then + sfull <= '0'; + end if; + if(sWEN='1' and sfull='0') then + Waddr_vect <= std_logic_vector(unsigned(Waddr_vect) +1); + Waddr_vect_d <= Waddr_vect; + end if; + + + end if; +end process; + + +full <= sFull; +empty <= sEmpty; +waddr <= Waddr_vect; +raddr <= Raddr_vect; + +end architecture; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -26,237 +26,93 @@ use grlib.amba.all; use std.textio.all; library lpp; use lpp.lpp_amba.all; +library gaisler; +use gaisler.misc.all; +use gaisler.memctrl.all; +library techmap; +use techmap.gencomp.all; --! Package contenant tous les programmes qui forment le composant intégré dans le léon package lpp_memory is ---===========================================================| ---=================== FIFO Complète =========================| ---===========================================================| - component APB_FIFO is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port ( - clk : in std_logic; - rst : in std_logic; - apbi : in apb_slv_in_type; - Full : out std_logic; - Empty : out std_logic; - WR : out std_logic; - RE : out std_logic; - apbo : out apb_slv_out_type - ); -end component; - - -component ApbDriver is - generic ( +generic ( + tech : integer := apa3; pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; pirq : integer := 0; abits : integer := 8; - LPP_DEVICE : integer; + FifoCnt : integer := 2; Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port ( - clk : in std_logic; - rst : in std_logic; - ReadEnable : out std_logic; - WriteEnable : out std_logic; - FlagEmpty : in std_logic; - FlagFull : in std_logic; --- ReUse : out std_logic; --- Lock : out std_logic; - RstMem : out std_logic; - DataIn : out std_logic_vector(Data_sz-1 downto 0); - DataOut : in std_logic_vector(Data_sz-1 downto 0); - AddrIn : in std_logic_vector(Addr_sz-1 downto 0); - AddrOut : in std_logic_vector(Addr_sz-1 downto 0); - apbi : in apb_slv_in_type; - apbo : out apb_slv_out_type - ); -end component; - - -component Top_FIFO is - generic( - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256 - ); - port( - clk,raz : in std_logic; - flag_RE : in std_logic; - flag_WR : in std_logic; --- ReUse : in std_logic; --- Lock : in std_logic; - RstMem : in std_logic; - Data_in : in std_logic_vector(Data_sz-1 downto 0); - Addr_RE : out std_logic_vector(addr_sz-1 downto 0); - Addr_WR : out std_logic_vector(addr_sz-1 downto 0); - full : out std_logic; - empty : out std_logic; - Data_out : out std_logic_vector(Data_sz-1 downto 0) + Addr_sz : integer := 9; + R : integer := 1; + W : integer := 1 ); -end component; - - -component Fifo_Read is - generic( - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port( - clk : in std_logic; - raz : in std_logic; - flag_RE : in std_logic; - Waddr : in std_logic_vector(addr_sz-1 downto 0); - empty : out std_logic; - Raddr : out std_logic_vector(addr_sz-1 downto 0) - ); -end component; - - -component Fifo_Write is - generic( - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port( - clk : in std_logic; - raz : in std_logic; - flag_WR : in std_logic; - Raddr : in std_logic_vector(addr_sz-1 downto 0); - full : out std_logic; - Waddr : out std_logic_vector(addr_sz-1 downto 0) - ); -end component; - - -component PipeLine is - generic(Data_sz : integer := 16); - port( - clk,raz : in std_logic; --! Horloge et reset general du composant - Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Donnée en entrée de la FIFO, coté écriture - flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire - flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire - empty : in std_logic; --! Flag, Mémoire vide - Data_svg : out std_logic_vector(Data_sz-1 downto 0); - Data1 : out std_logic; - Data2 : out std_logic + port ( + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + rclk : in std_logic; + wclk : in std_logic; + REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mémoire + WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'écriture en mémoire + Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire vide + Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire pleine + RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en entrée + WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en sortie + WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (écriture) + RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) + apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); end component; -component LocalReset is - port( - clk : in std_logic; - raz : in std_logic; - Rz : in std_logic; - rstf : out std_logic +component lpp_fifo is +generic( + tech : integer := 0; + DataSz : integer range 1 to 32 := 8; + abits : integer range 2 to 12 := 8 ); -end component; ---===========================================================| ---================= Demi FIFO Ecriture ======================| ---===========================================================| - -component APB_FifoWrite is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port ( - clk : in std_logic; - rst : in std_logic; - apbi : in apb_slv_in_type; - ReadEnable : in std_logic; - Empty : out std_logic; - Full : out std_logic; - DATA : out std_logic_vector(Data_sz-1 downto 0); - apbo : out apb_slv_out_type - ); +port( + rstn : in std_logic; + rclk : in std_logic; + ren : in std_logic; + rdata : out std_logic_vector(DataSz-1 downto 0); + empty : out std_logic; + raddr : out std_logic_vector(abits-1 downto 0); + wclk : in std_logic; + wen : in std_logic; + wdata : in std_logic_vector(DataSz-1 downto 0); + full : out std_logic; + waddr : out std_logic_vector(abits-1 downto 0) +); end component; - ---component Top_FifoWrite is --- generic( --- Data_sz : integer := 16; --- Addr_sz : integer := 8; --- addr_max_int : integer := 256); --- port( --- clk : in std_logic; --- raz : in std_logic; --- flag_RE : in std_logic; --- flag_WR : in std_logic; --- Data_in : in std_logic_vector(Data_sz-1 downto 0); --- Raddr : in std_logic_vector(addr_sz-1 downto 0); --- full : out std_logic; --- empty : out std_logic; --- Waddr : out std_logic_vector(addr_sz-1 downto 0); --- Data_out : out std_logic_vector(Data_sz-1 downto 0) --- ); ---end component; - ---===========================================================| ---================== Demi FIFO Lecture ======================| ---===========================================================| - -component APB_FifoRead is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port ( - clk : in std_logic; - rst : in std_logic; - apbi : in apb_slv_in_type; - WriteEnable : in std_logic; - RE : out std_logic; - Full : out std_logic; - Empty : out std_logic; - DATA : in std_logic_vector(Data_sz-1 downto 0); - dataTEST : out std_logic_vector(Data_sz-1 downto 0); - apbo : out apb_slv_out_type - ); +component ssram_plugin is +generic (tech : integer := 0); +port +( + clk : in std_logic; + mem_ctrlr_o : in memory_out_type; + SSRAM_CLK : out std_logic; + nBWa : out std_logic; + nBWb : out std_logic; + nBWc : out std_logic; + nBWd : out std_logic; + nBWE : out std_logic; + nADSC : out std_logic; + nADSP : out std_logic; + nADV : out std_logic; + nGW : out std_logic; + nCE1 : out std_logic; + CE2 : out std_logic; + nCE3 : out std_logic; + nOE : out std_logic; + MODE : out std_logic; + ZZ : out std_logic +); end component; - ---component Top_FifoRead is --- generic( --- Data_sz : integer := 16; --- Addr_sz : integer := 8; --- addr_max_int : integer := 256); --- port( --- clk : in std_logic; --- raz : in std_logic; --- flag_RE : in std_logic; --- flag_WR : in std_logic; --- Data_in : in std_logic_vector(Data_sz-1 downto 0); --- Waddr : in std_logic_vector(addr_sz-1 downto 0); --- full : out std_logic; --- empty : out std_logic; --- Raddr : out std_logic_vector(addr_sz-1 downto 0); --- Data_out : out std_logic_vector(Data_sz-1 downto 0) --- ); ---end component; - end;