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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_fft.all;
27 use work.fft_components.all;
28
29 entity FFT is
30 generic(
31 Data_sz : integer := 16;
32 NbData : integer := 256);
33 port(
34 clkm : in std_logic;
35 rstn : in std_logic;
36 FifoIN_Empty : in std_logic_vector(4 downto 0);
37 FifoIN_Data : in std_logic_vector(79 downto 0);
38 FifoOUT_Full : in std_logic_vector(4 downto 0);
39 Read : out std_logic_vector(4 downto 0);
40 Write : out std_logic_vector(4 downto 0);
41 ReUse : out std_logic_vector(4 downto 0);
42 Data : out std_logic_vector(79 downto 0)
43 );
44 end entity;
45
46
47 architecture ar_FFT of FFT is
48
49 signal Drive_Write : std_logic;
50 signal Drive_DataRE : std_logic_vector(15 downto 0);
51 signal Drive_DataIM : std_logic_vector(15 downto 0);
52
53 signal Start : std_logic;
54 signal FFT_Load : std_logic;
55 signal FFT_Ready : std_logic;
56 signal FFT_Valid : std_logic;
57 signal FFT_DataRE : std_logic_vector(15 downto 0);
58 signal FFT_DataIM : std_logic_vector(15 downto 0);
59
60 signal Link_Read : std_logic;
61
62 begin
63
64 Start <= '0';
65
66 DRIVE : Driver_FFT
67 generic map(Data_sz,NbData)
68 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM);
69
70 FFT0 : CoreFFT
71 generic map(
72 LOGPTS => gLOGPTS,
73 LOGLOGPTS => gLOGLOGPTS,
74 WSIZE => gWSIZE,
75 TWIDTH => gTWIDTH,
76 DWIDTH => gDWIDTH,
77 TDWIDTH => gTDWIDTH,
78 RND_MODE => gRND_MODE,
79 SCALE_MODE => gSCALE_MODE,
80 PTS => gPTS,
81 HALFPTS => gHALFPTS,
82 inBuf_RWDLY => gInBuf_RWDLY)
83 port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
84
85
86 LINK : Linker_FFT
87 generic map(Data_sz,NbData)
88 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data);
89
90
91 end architecture; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 --! Programme permetant de compl�menter ou non les entr�es de l'ALU, et ainsi de travailler avec des nombres n�gatifs
27
28 entity TwoComplementer is
29 generic(
30 Input_SZ : integer := 16);
31 port(
32 clk : in std_logic; --! Horloge du composant
33 reset : in std_logic; --! Reset general du composant
34 clr : in std_logic; --! Un reset sp�cifique au programme
35 TwoComp : in std_logic; --! Autorise l'utilisation du compl�ment
36 OP : in std_logic_vector(Input_SZ-1 downto 0); --! Op�rande d'entr�e
37 RES : out std_logic_vector(Input_SZ-1 downto 0) --! R�sultat, op�rande compl�ment� ou non
38 );
39 end TwoComplementer;
40
41
42 architecture ar_TwoComplementer of TwoComplementer is
43
44 signal REG : std_logic_vector(Input_SZ-1 downto 0);
45 signal OPinteger : integer;
46 signal RESCOMP : std_logic_vector(Input_SZ-1 downto 0);
47
48 begin
49
50 RES <= REG;
51 OPinteger <= to_integer(signed(OP));
52 RESCOMP <= std_logic_vector(to_signed(-OPinteger,Input_SZ));
53
54 process(clk,reset)
55 begin
56
57 if(reset='0')then
58 REG <= (others => '0');
59 elsif(clk'event and clk='1')then
60
61 if(clr='1')then
62 REG <= (others => '0');
63 elsif(TwoComp='1')then
64 REG <= RESCOMP;
65 else
66 REG <= OP;
67 end if;
68
69 end if;
70
71 end process;
72 end ar_TwoComplementer; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_demux.all;
27
28 entity Demultiplex is
29 generic(
30 Data_sz : integer range 1 to 32 := 16);
31 port(
32 clk : in std_logic;
33 rstn : in std_logic;
34
35 Read : in std_logic_vector(4 downto 0);
36
37 EmptyF0a : in std_logic_vector(4 downto 0);
38 EmptyF0b : in std_logic_vector(4 downto 0);
39 EmptyF1 : in std_logic_vector(4 downto 0);
40 EmptyF2 : in std_logic_vector(4 downto 0);
41
42 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
43 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
44 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
45 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
46
47 Read_DEMUX : out std_logic_vector(19 downto 0);
48 Empty : out std_logic_vector(4 downto 0);
49 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
50 );
51 end entity;
52
53
54 architecture ar_Demultiplex of Demultiplex is
55
56 signal DataCpt : std_logic_vector(3 downto 0);
57
58 begin
59
60 FLG0 : WatchFlag
61 port map(clk,rstn,EmptyF0a,EmptyF0b,EmptyF1,EmptyF2,DataCpt);
62
63 DEM : DEMUX
64 generic map(Data_sz)
65 port map(clk,rstn,Read,DataCpt,EmptyF0a,EmptyF0b,EmptyF1,EmptyF2,DataF0a,DataF0b,DataF1,DataF2,Read_DEMUX,Empty,Data);
66
67 end architecture;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_matrix.all;
27
28 entity MatriceSpectrale is
29 generic(
30 Input_SZ : integer := 16;
31 Result_SZ : integer := 32);
32 port(
33 clkm : in std_logic;
34 rstn : in std_logic;
35
36 FifoIN_Full : in std_logic_vector(4 downto 0);
37 FifoOUT_Full : in std_logic_vector(1 downto 0);
38 Data_IN : in std_logic_vector(79 downto 0);
39 ACQ : in std_logic;
40 FlagError : out std_logic;
41 Pong : out std_logic;
42 Write : out std_logic_vector(1 downto 0);
43 Read : out std_logic_vector(4 downto 0);
44 Data_OUT : out std_logic_vector(63 downto 0)
45 );
46 end entity;
47
48
49 architecture ar_MatriceSpectrale of MatriceSpectrale is
50
51 signal Matrix_Write : std_logic;
52 signal Matrix_Read : std_logic_vector(1 downto 0);
53 signal Matrix_Result : std_logic_vector(31 downto 0);
54
55 signal TopSM_Start : std_logic;
56 signal TopSM_Statu : std_logic_vector(3 downto 0);
57 signal TopSM_Data1 : std_logic_vector(15 downto 0);
58 signal TopSM_Data2 : std_logic_vector(15 downto 0);
59
60 begin
61
62 TopSM : TopSpecMatrix
63 generic map (Input_SZ)
64 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
65
66 SM : SpectralMatrix
67 generic map (Input_SZ,Result_SZ)
68 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
69
70 DISP : Dispatch
71 generic map(Result_SZ)
72 port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError);
73
74
75 end architecture;
76
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.numeric_std.ALL;
25 25 USE IEEE.std_logic_1164.ALL;
26 26
27 27 LIBRARY techmap;
28 28 USE techmap.gencomp.ALL;
29 29
30 30 LIBRARY lpp;
31 31 USE lpp.iir_filter.ALL;
32 32 USE lpp.general_purpose.ALL;
33 33
34 34 ENTITY IIR_CEL_CTRLR_v2 IS
35 35 GENERIC (
36 36 tech : INTEGER := apa3;
37 37 Mem_use : INTEGER := use_RAM;
38 38 Sample_SZ : INTEGER := 18;
39 39 Coef_SZ : INTEGER := 9;
40 40 Coef_Nb : INTEGER := 25;
41 41 Coef_sel_SZ : INTEGER := 5;
42 42 Cels_count : INTEGER := 5;
43 43 ChanelsCount : INTEGER := 8);
44 44 PORT (
45 45 rstn : IN STD_LOGIC;
46 46 clk : IN STD_LOGIC;
47 47
48 48 virg_pos : IN INTEGER;
49 49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
50 50
51 51 sample_in_val : IN STD_LOGIC;
52 52 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
53 53
54 54 sample_out_val : OUT STD_LOGIC;
55 55 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
56 56 END IIR_CEL_CTRLR_v2;
57 57
58 58 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_CEL_CTRLR_v2 IS
59 59
60 60 COMPONENT IIR_CEL_CTRLR_v2_DATAFLOW
61 61 GENERIC (
62 62 tech : INTEGER;
63 63 Mem_use : INTEGER;
64 64 Sample_SZ : INTEGER;
65 65 Coef_SZ : INTEGER;
66 66 Coef_Nb : INTEGER;
67 67 Coef_sel_SZ : INTEGER);
68 68 PORT (
69 69 rstn : IN STD_LOGIC;
70 70 clk : IN STD_LOGIC;
71 71 virg_pos : IN INTEGER;
72 72 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
73 73 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
74 74 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
75 75 ram_write : IN STD_LOGIC;
76 76 ram_read : IN STD_LOGIC;
77 77 raddr_rst : IN STD_LOGIC;
78 78 raddr_add1 : IN STD_LOGIC;
79 79 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
80 80 alu_sel_input : IN STD_LOGIC;
81 81 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
82 alu_ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
82 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
83 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
83 84 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
84 85 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
85 86 END COMPONENT;
86 87
87 88 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
88 89 GENERIC (
89 90 Coef_sel_SZ : INTEGER;
90 91 Cels_count : INTEGER;
91 92 ChanelsCount : INTEGER);
92 93 PORT (
93 94 rstn : IN STD_LOGIC;
94 95 clk : IN STD_LOGIC;
95 96 sample_in_val : IN STD_LOGIC;
96 97 sample_in_rot : OUT STD_LOGIC;
97 98 sample_out_val : OUT STD_LOGIC;
98 99 sample_out_rot : OUT STD_LOGIC;
99 100 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
100 101 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
101 102 ram_write : OUT STD_LOGIC;
102 103 ram_read : OUT STD_LOGIC;
103 104 raddr_rst : OUT STD_LOGIC;
104 105 raddr_add1 : OUT STD_LOGIC;
105 106 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
106 107 alu_sel_input : OUT STD_LOGIC;
107 108 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
108 alu_ctrl : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
109 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
109 110 END COMPONENT;
110 111
111 112 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
112 113 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
113 114 SIGNAL ram_write : STD_LOGIC;
114 115 SIGNAL ram_read : STD_LOGIC;
115 116 SIGNAL raddr_rst : STD_LOGIC;
116 117 SIGNAL raddr_add1 : STD_LOGIC;
117 118 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 119 SIGNAL alu_sel_input : STD_LOGIC;
119 120 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
120 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(3 DOWNTO 0);
121 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
121 122
122 123 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
123 124 SIGNAL sample_in_rotate : STD_LOGIC;
124 125 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
125 126 SIGNAL sample_out_val_s : STD_LOGIC;
126 127 SIGNAL sample_out_val_s2 : STD_LOGIC;
127 128 SIGNAL sample_out_rot_s : STD_LOGIC;
128 129 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
129 130
130 131 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
131 132
132 133 BEGIN
133 134
134 135 IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW
135 136 GENERIC MAP (
136 137 tech => tech,
137 138 Mem_use => Mem_use,
138 139 Sample_SZ => Sample_SZ,
139 140 Coef_SZ => Coef_SZ,
140 141 Coef_Nb => Coef_Nb,
141 142 Coef_sel_SZ => Coef_sel_SZ)
142 143 PORT MAP (
143 144 rstn => rstn,
144 145 clk => clk,
145 146 virg_pos => virg_pos,
146 147 coefs => coefs,
147 148 --CTRL
148 149 in_sel_src => in_sel_src,
149 150 ram_sel_Wdata => ram_sel_Wdata,
150 151 ram_write => ram_write,
151 152 ram_read => ram_read,
152 153 raddr_rst => raddr_rst,
153 154 raddr_add1 => raddr_add1,
154 155 waddr_previous => waddr_previous,
155 156 alu_sel_input => alu_sel_input,
156 157 alu_sel_coeff => alu_sel_coeff,
157 158 alu_ctrl => alu_ctrl,
159 alu_comp => "00",
158 160 --DATA
159 161 sample_in => sample_in_s,
160 162 sample_out => sample_out_s);
161 163
162 164
163 165 IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
164 166 GENERIC MAP (
165 167 Coef_sel_SZ => Coef_sel_SZ,
166 168 Cels_count => Cels_count,
167 169 ChanelsCount => ChanelsCount)
168 170 PORT MAP (
169 171 rstn => rstn,
170 172 clk => clk,
171 173 sample_in_val => sample_in_val,
172 174 sample_in_rot => sample_in_rotate,
173 175 sample_out_val => sample_out_val_s,
174 176 sample_out_rot => sample_out_rot_s,
175 177
176 178 in_sel_src => in_sel_src,
177 179 ram_sel_Wdata => ram_sel_Wdata,
178 180 ram_write => ram_write,
179 181 ram_read => ram_read,
180 182 raddr_rst => raddr_rst,
181 183 raddr_add1 => raddr_add1,
182 184 waddr_previous => waddr_previous,
183 185 alu_sel_input => alu_sel_input,
184 186 alu_sel_coeff => alu_sel_coeff,
185 187 alu_ctrl => alu_ctrl);
186 188
187 189 -----------------------------------------------------------------------------
188 190 -- SAMPLE IN
189 191 -----------------------------------------------------------------------------
190 192 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
191 193
192 194 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
193 195 PROCESS (clk, rstn)
194 196 BEGIN -- PROCESS
195 197 IF rstn = '0' THEN -- asynchronous reset (active low)
196 198 sample_in_buf(I, J) <= '0';
197 199 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
198 200 IF sample_in_val = '1' THEN
199 201 sample_in_buf(I, J) <= sample_in(I, J);
200 202 ELSIF sample_in_rotate = '1' THEN
201 203 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
202 204 END IF;
203 205 END IF;
204 206 END PROCESS;
205 207 END GENERATE loop_all_chanel;
206 208
207 209 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
208 210
209 211 END GENERATE loop_all_sample;
210 212
211 213 -----------------------------------------------------------------------------
212 214 -- SAMPLE OUT
213 215 -----------------------------------------------------------------------------
214 216 PROCESS (clk, rstn)
215 217 BEGIN -- PROCESS
216 218 IF rstn = '0' THEN -- asynchronous reset (active low)
217 219 sample_out_val <= '0';
218 220 sample_out_val_s2 <= '0';
219 221 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
220 222 sample_out_val <= sample_out_val_s2;
221 223 sample_out_val_s2 <= sample_out_val_s;
222 224 END IF;
223 225 END PROCESS;
224 226
225 227 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
226 228 PROCESS (clk, rstn)
227 229 BEGIN -- PROCESS
228 230 IF rstn = '0' THEN -- asynchronous reset (active low)
229 231 sample_out_s2(ChanelsCount-1, I) <= '0';
230 232 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
231 233 IF sample_out_rot_s = '1' THEN
232 234 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
233 235 END IF;
234 236 END IF;
235 237 END PROCESS;
236 238 END GENERATE chanel_HIGH;
237 239
238 240 chanel_more : IF ChanelsCount > 1 GENERATE
239 241 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
240 242 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
241 243 PROCESS (clk, rstn)
242 244 BEGIN -- PROCESS
243 245 IF rstn = '0' THEN -- asynchronous reset (active low)
244 246 sample_out_s2(J-1, I) <= '0';
245 247 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
246 248 IF sample_out_rot_s = '1' THEN
247 249 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
248 250 END IF;
249 251 END IF;
250 252 END PROCESS;
251 253 END GENERATE all_bit;
252 254 END GENERATE all_chanel;
253 255 END GENERATE chanel_more;
254 256
255 257 sample_out <= sample_out_s2;
256 258 END ar_IIR_CEL_CTRLR_v2;
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more Cdetails.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.numeric_std.ALL;
25 25 USE IEEE.std_logic_1164.ALL;
26 26 LIBRARY lpp;
27 27 USE lpp.iir_filter.ALL;
28 28 USE lpp.general_purpose.ALL;
29 29
30 30 ENTITY IIR_CEL_CTRLR_v2_CONTROL IS
31 31 GENERIC (
32 32 Coef_sel_SZ : INTEGER;
33 33 Cels_count : INTEGER := 5;
34 34 ChanelsCount : INTEGER := 1);
35 35 PORT (
36 36 rstn : IN STD_LOGIC;
37 37 clk : IN STD_LOGIC;
38 38
39 39 sample_in_val : IN STD_LOGIC;
40 40 sample_in_rot : OUT STD_LOGIC;
41 41 sample_out_val : OUT STD_LOGIC;
42 42 sample_out_rot : OUT STD_LOGIC;
43 43
44 44 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
45 45 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
46 46 ram_write : OUT STD_LOGIC;
47 47 ram_read : OUT STD_LOGIC;
48 48 raddr_rst : OUT STD_LOGIC;
49 49 raddr_add1 : OUT STD_LOGIC;
50 50 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
51 51 alu_sel_input : OUT STD_LOGIC;
52 52 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
53 alu_ctrl : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
53 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
54 54 );
55 55 END IIR_CEL_CTRLR_v2_CONTROL;
56 56
57 57 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_CONTROL OF IIR_CEL_CTRLR_v2_CONTROL IS
58 58
59 59 TYPE fsmIIR_CEL_T IS (waiting,
60 60 first_read,
61 61 compute_b0,
62 62 compute_b1,
63 63 compute_b2,
64 64 compute_a1,
65 65 compute_a2,
66 66 LAST_CEL,
67 67 wait_valid_last_output,
68 68 wait_valid_last_output_2);
69 69 SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T;
70 70
71 71 SIGNAL alu_selected_coeff : INTEGER;
72 72 SIGNAL Chanel_ongoing : INTEGER;
73 73 SIGNAL Cel_ongoing : INTEGER;
74 74
75 75 BEGIN
76 76
77 77 alu_sel_coeff <= STD_LOGIC_VECTOR(to_unsigned(alu_selected_coeff, Coef_sel_SZ));
78 78
79 79 PROCESS (clk, rstn)
80 80 BEGIN -- PROCESS
81 81 IF rstn = '0' THEN -- asynchronous reset (active low)
82 82 --REG -------------------------------------------------------------------
83 83 in_sel_src <= (OTHERS => '0'); --
84 84 --RAM_WRitE -------------------------------------------------------------
85 85 ram_sel_Wdata <= "00"; --
86 86 ram_write <= '0'; --
87 87 waddr_previous <= "00"; --
88 88 --RAM_READ --------------------------------------------------------------
89 89 ram_read <= '0'; --
90 90 raddr_rst <= '0'; --
91 91 raddr_add1 <= '0'; --
92 92 --ALU -------------------------------------------------------------------
93 93 alu_selected_coeff <= 0; --
94 94 alu_sel_input <= '0'; --
95 alu_ctrl <= (OTHERS => '0'); --
95 alu_ctrl <= ctrl_IDLE; --
96 96 --OUT
97 97 sample_out_val <= '0'; --
98 98 sample_out_rot <= '0'; --
99 99
100 100 Chanel_ongoing <= 0; --
101 101 Cel_ongoing <= 0; --
102 102 sample_in_rot <= '0';
103 103
104 104 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
105 105
106 106 CASE IIR_CEL_STATE IS
107 107 WHEN waiting =>
108 108 sample_out_rot <= '0';
109 109 sample_in_rot <= '0';
110 110 sample_out_val <= '0';
111 alu_ctrl <= "0100";
111 alu_ctrl <= ctrl_CLRMAC;
112 112 alu_selected_coeff <= 0;
113 113 in_sel_src <= "01";
114 114 ram_read <= '0';
115 115 ram_sel_Wdata <= "00";
116 116 ram_write <= '0';
117 117 waddr_previous <= "00";
118 118 IF sample_in_val = '1' THEN
119 119 raddr_rst <= '0';
120 120 alu_sel_input <= '1';
121 121 ram_read <= '1';
122 122 raddr_add1 <= '1';
123 123 IIR_CEL_STATE <= first_read;
124 124 Chanel_ongoing <= Chanel_ongoing + 1;
125 125 Cel_ongoing <= 1;
126 126 ELSE
127 127 raddr_add1 <= '0';
128 128 raddr_rst <= '1';
129 129 Chanel_ongoing <= 0;
130 130 Cel_ongoing <= 0;
131 131 END IF;
132 132
133 133 WHEN first_read =>
134 134 IIR_CEL_STATE <= compute_b2;
135 135 ram_read <= '1';
136 136 raddr_add1 <= '1';
137 alu_ctrl <= "0010";
137 alu_ctrl <= ctrl_MULT;
138 138 alu_sel_input <= '1';
139 139 in_sel_src <= "01";
140 140
141 141
142 142 WHEN compute_b2 =>
143 143 sample_out_rot <= '0';
144 144
145 145 sample_in_rot <= '0';
146 146 sample_out_val <= '0';
147 147
148 148 alu_sel_input <= '1';
149 149 --
150 150 ram_sel_Wdata <= "10";
151 151 ram_write <= '1';
152 152 waddr_previous <= "10";
153 153 --
154 154 ram_read <= '1';
155 155 raddr_rst <= '0';
156 156 raddr_add1 <= '0';
157 157 IF Cel_ongoing = 1 THEN
158 158 in_sel_src <= "00";
159 159 ELSE
160 160 in_sel_src <= "11";
161 161 END IF;
162 162 alu_selected_coeff <= alu_selected_coeff+1;
163 alu_ctrl <= "0001";
163 alu_ctrl <= ctrl_MAC;
164 164 IIR_CEL_STATE <= compute_b1;
165 165
166 166 WHEN compute_b1 =>
167 167 sample_in_rot <= '0';
168 168 alu_sel_input <= '0';
169 169 --
170 170 ram_sel_Wdata <= "00";
171 171 ram_write <= '1';
172 172 waddr_previous <= "01";
173 173 --
174 174 ram_read <= '1';
175 175 raddr_rst <= '0';
176 176 raddr_add1 <= '1';
177 177 sample_out_rot <= '0';
178 178 IF Cel_ongoing = 1 THEN
179 179 in_sel_src <= "10";
180 180 sample_out_val <= '0';
181 181 ELSE
182 182 sample_out_val <= '0';
183 183 in_sel_src <= "00";
184 184 END IF;
185 185 alu_selected_coeff <= alu_selected_coeff+1;
186 alu_ctrl <= "0001";
186 alu_ctrl <= ctrl_MAC;
187 187 IIR_CEL_STATE <= compute_b0;
188 188
189 189 WHEN compute_b0 =>
190 190 sample_out_rot <= '0';
191 191 sample_out_val <= '0';
192 192 sample_in_rot <= '0';
193 193 alu_sel_input <= '1';
194 194 ram_sel_Wdata <= "00";
195 195 ram_write <= '0';
196 196 waddr_previous <= "01";
197 197 ram_read <= '1';
198 198 raddr_rst <= '0';
199 199 raddr_add1 <= '0';
200 200 in_sel_src <= "10";
201 201 alu_selected_coeff <= alu_selected_coeff+1;
202 alu_ctrl <= "0001";
202 alu_ctrl <= ctrl_MAC;
203 203 IIR_CEL_STATE <= compute_a2;
204 204 IF Cel_ongoing = Cels_count THEN
205 205 sample_in_rot <= '1';
206 206 ELSE
207 207 sample_in_rot <= '0';
208 208 END IF;
209 209
210 210 WHEN compute_a2 =>
211 211 sample_out_val <= '0';
212 212 sample_out_rot <= '0';
213 213 alu_sel_input <= '1';
214 214 ram_sel_Wdata <= "00";
215 215 ram_write <= '0';
216 216 waddr_previous <= "01";
217 217 ram_read <= '1';
218 218 raddr_rst <= '0';
219 219 IF Cel_ongoing = Cels_count THEN
220 220 raddr_add1 <= '1';
221 221 ELSE
222 222 raddr_add1 <= '0';
223 223 END IF;
224 224 in_sel_src <= "00";
225 225 alu_selected_coeff <= alu_selected_coeff+1;
226 alu_ctrl <= "0001";
226 alu_ctrl <= ctrl_MAC;
227 227 IIR_CEL_STATE <= compute_a1;
228 228 sample_in_rot <= '0';
229 229
230 230 WHEN compute_a1 =>
231 231 sample_out_val <= '0';
232 232 sample_out_rot <= '0';
233 233 alu_sel_input <= '0';
234 234 ram_sel_Wdata <= "00";
235 235 ram_write <= '0';
236 236 waddr_previous <= "01";
237 237 ram_read <= '1';
238 238 raddr_rst <= '0';
239 alu_ctrl <= "0010";
239 alu_ctrl <= ctrl_MULT;
240 240 sample_in_rot <= '0';
241 241 IF Cel_ongoing = Cels_count THEN
242 242 alu_selected_coeff <= 0;
243 243
244 244 ram_sel_Wdata <= "10";
245 245 raddr_add1 <= '1';
246 246 ram_write <= '1';
247 247 waddr_previous <= "10";
248 248
249 249 IF Chanel_ongoing = ChanelsCount THEN
250 250 IIR_CEL_STATE <= wait_valid_last_output;
251 251 ELSE
252 252 Chanel_ongoing <= Chanel_ongoing + 1;
253 253 Cel_ongoing <= 1;
254 254 IIR_CEL_STATE <= LAST_CEL;
255 255 in_sel_src <= "01";
256 256 END IF;
257 257 ELSE
258 258 raddr_add1 <= '1';
259 259 alu_selected_coeff <= alu_selected_coeff+1;
260 260 Cel_ongoing <= Cel_ongoing+1;
261 261 IIR_CEL_STATE <= compute_b2;
262 262 END IF;
263 263
264 264 WHEN LAST_CEL =>
265 265 alu_sel_input <= '1';
266 266 IIR_CEL_STATE <= compute_b2;
267 267 raddr_add1 <= '1';
268 268 ram_sel_Wdata <= "01";
269 269 ram_write <= '1';
270 270 waddr_previous <= "10";
271 271 sample_out_rot <= '1';
272 272
273 273
274 274 WHEN wait_valid_last_output =>
275 275 IIR_CEL_STATE <= wait_valid_last_output_2;
276 276 sample_in_rot <= '0';
277 alu_ctrl <= "0000";
277 alu_ctrl <= ctrl_IDLE;
278 278 alu_selected_coeff <= 0;
279 279 in_sel_src <= "01";
280 280 ram_read <= '0';
281 281 raddr_rst <= '1';
282 282 raddr_add1 <= '1';
283 283 ram_sel_Wdata <= "01";
284 284 ram_write <= '1';
285 285 waddr_previous <= "10";
286 286 Chanel_ongoing <= 0;
287 287 Cel_ongoing <= 0;
288 288 sample_out_val <= '0';
289 289 sample_out_rot <= '1';
290 290
291 291 WHEN wait_valid_last_output_2 =>
292 292 IIR_CEL_STATE <= waiting;
293 293 sample_in_rot <= '0';
294 alu_ctrl <= "0000";
294 alu_ctrl <= ctrl_IDLE;
295 295 alu_selected_coeff <= 0;
296 296 in_sel_src <= "01";
297 297 ram_read <= '0';
298 298 raddr_rst <= '1';
299 299 raddr_add1 <= '1';
300 300 ram_sel_Wdata <= "10";
301 301 ram_write <= '1';
302 302 waddr_previous <= "10";
303 303 Chanel_ongoing <= 0;
304 304 Cel_ongoing <= 0;
305 305 sample_out_val <= '1';
306 306 sample_out_rot <= '0';
307 307 WHEN OTHERS => NULL;
308 308 END CASE;
309 309
310 310 END IF;
311 311 END PROCESS;
312 312
313 END ar_IIR_CEL_CTRLR_v2_CONTROL;
313 END ar_IIR_CEL_CTRLR_v2_CONTROL; No newline at end of file
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY lpp;
26 26 USE lpp.iir_filter.ALL;
27 27 USE lpp.general_purpose.ALL;
28 28
29 29
30 30
31 31 ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS
32 32 GENERIC(
33 33 tech : INTEGER := 0;
34 34 Mem_use : INTEGER := use_RAM;
35 35 Sample_SZ : INTEGER := 16;
36 36 Coef_SZ : INTEGER := 9;
37 37 Coef_Nb : INTEGER := 30;
38 38 Coef_sel_SZ : INTEGER := 5
39 39 );
40 40 PORT(
41 41 rstn : IN STD_LOGIC;
42 42 clk : IN STD_LOGIC;
43 43 -- PARAMETER
44 44 virg_pos : IN INTEGER;
45 45 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
46 46 -- CONTROL
47 47 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 48 --
49 49 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 50 ram_write : IN STD_LOGIC;
51 51 ram_read : IN STD_LOGIC;
52 52 raddr_rst : IN STD_LOGIC;
53 53 raddr_add1 : IN STD_LOGIC;
54 54 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
55 55 --
56 56 alu_sel_input : IN STD_LOGIC;
57 57 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
58 alu_ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE)
58 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE)
59 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
59 60 -- DATA
60 61 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
61 62 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)
62 63 );
63 64 END IIR_CEL_CTRLR_v2_DATAFLOW;
64 65
65 66 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLOW OF IIR_CEL_CTRLR_v2_DATAFLOW IS
66 67
67 68 COMPONENT RAM_CTRLR_v2
68 69 GENERIC (
69 70 tech : INTEGER;
70 71 Input_SZ_1 : INTEGER;
71 72 Mem_use : INTEGER);
72 73 PORT (
73 74 rstn : IN STD_LOGIC;
74 75 clk : IN STD_LOGIC;
75 76 ram_write : IN STD_LOGIC;
76 77 ram_read : IN STD_LOGIC;
77 78 raddr_rst : IN STD_LOGIC;
78 79 raddr_add1 : IN STD_LOGIC;
79 80 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
80 81 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
81 82 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
82 83 END COMPONENT;
83 84
84 85 SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
85 86 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
86 87 SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
87 88 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
88 89 SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
89 90 SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0);
90 91
91 92 SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0);
92 93 SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0);
93 94
94 95 SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0);
95 96
96 97 BEGIN
97 98
98 99 -----------------------------------------------------------------------------
99 100 -- INPUT
100 101 -----------------------------------------------------------------------------
101 102 PROCESS (clk, rstn)
102 103 BEGIN -- PROCESS
103 104 IF rstn = '0' THEN -- asynchronous reset (active low)
104 105 reg_sample_in <= (OTHERS => '0');
105 106 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
106 107 CASE in_sel_src IS
107 108 WHEN "00" => reg_sample_in <= reg_sample_in;
108 109 WHEN "01" => reg_sample_in <= sample_in;
109 110 WHEN "10" => reg_sample_in <= ram_output;
110 111 WHEN "11" => reg_sample_in <= alu_output;
111 112 WHEN OTHERS => NULL;
112 113 END CASE;
113 114 END IF;
114 115 END PROCESS;
115 116
116 117
117 118 -----------------------------------------------------------------------------
118 119 -- RAM + CTRL
119 120 -----------------------------------------------------------------------------
120 121
121 122 ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE
122 123 alu_output WHEN ram_sel_Wdata = "01" ELSE
123 124 ram_output;
124 125
125 126 RAM_CTRLR_v2_1: RAM_CTRLR_v2
126 127 GENERIC MAP (
127 128 tech => tech,
128 129 Input_SZ_1 => Sample_SZ,
129 130 Mem_use => Mem_use)
130 131 PORT MAP (
131 132 clk => clk,
132 133 rstn => rstn,
133 134 ram_write => ram_write,
134 135 ram_read => ram_read,
135 136 raddr_rst => raddr_rst,
136 137 raddr_add1 => raddr_add1,
137 138 waddr_previous => waddr_previous,
138 139 sample_in => ram_input,
139 140 sample_out => ram_output);
140 141
141 142 -----------------------------------------------------------------------------
142 143 -- MAC_ACC
143 144 -----------------------------------------------------------------------------
144 145 -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE)
145 146 -- Data In : mac_sample, mac_coef
146 147 -- Data Out: mac_output
147 148
148 149 alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output;
149 150
150 151 coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE
151 152 coeff_in: IF I < Coef_Nb GENERATE
152 153 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
153 154 arrayCoeff(I,J) <= coefs(Coef_SZ*I+J);
154 155 END GENERATE all_bit;
155 156 END GENERATE coeff_in;
156 157 coeff_null: IF I > (Coef_Nb -1) GENERATE
157 158 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
158 159 arrayCoeff(I,J) <= '0';
159 160 END GENERATE all_bit;
160 161 END GENERATE coeff_null;
161 162 END GENERATE coefftable;
162 163
163 164 Coeff_Mux : MUXN
164 165 GENERIC MAP (
165 166 Input_SZ => Coef_SZ,
166 167 NbStage => Coef_sel_SZ)
167 168 PORT MAP (
168 169 sel => alu_sel_coeff,
169 170 INPUT => arrayCoeff,
170 171 RES => alu_coef_s);
171 172
172 173
173 174 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
174 175 alu_coef(J) <= alu_coef_s(J);
175 176 END GENERATE all_bit;
176 177
177 178 -----------------------------------------------------------------------------
178 179 -- TODO : just for Synthesis test
179 180
180 181 --PROCESS (clk, rstn)
181 182 --BEGIN
182 183 -- IF rstn = '0' THEN
183 184 -- alu_coef <= (OTHERS => '0');
184 185 -- ELSIF clk'event AND clk = '1' THEN
185 186 -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP
186 187 -- alu_coef(J) <= alu_coef_s(J);
187 188 -- END LOOP all_bit;
188 189 -- END IF;
189 190 --END PROCESS;
190 191
191 192 -----------------------------------------------------------------------------
192 193
193 194
194 195 ALU_1: ALU
195 196 GENERIC MAP (
196 197 Arith_en => 1,
197 198 Input_SZ_1 => Sample_SZ,
198 199 Input_SZ_2 => Coef_SZ)
199 200 PORT MAP (
200 201 clk => clk,
201 202 reset => rstn,
202 203 ctrl => alu_ctrl,
204 comp => alu_comp,
203 205 OP1 => alu_sample,
204 206 OP2 => alu_coef,
205 207 RES => alu_output_s);
206 208
207 209 alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos);
208 210
209 211 sample_out <= alu_output;
210 212
211 213 END ar_IIR_CEL_CTRLR_v2_DATAFLOW;
212 214
213 215
214 216
215 217
216 218
217 219
218 220
219 221
220 222
221 223
222 224
223 225
224 226
225 227
226 228
227 229
228 230
229 231
230 232
231 233
232 234
233 235
234 236
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236 238
237 239
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240 242
241 243
242 244
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244 246
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246 248
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@@ -1,244 +1,259
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 use lpp.lpp_memory.all;
30 29 use work.fft_components.all;
31 30
32 31 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
33 32
34 33 package lpp_fft is
35 34
36 35 component APB_FFT is
37 36 generic (
38 37 pindex : integer := 0;
39 38 paddr : integer := 0;
40 39 pmask : integer := 16#fff#;
41 40 pirq : integer := 0;
42 41 abits : integer := 8;
43 42 Data_sz : integer := 16
44 43 );
45 44 port (
46 45 clk : in std_logic;
47 46 rst : in std_logic; --! Reset general du composant
48 47 apbi : in apb_slv_in_type;
49 48 apbo : out apb_slv_out_type
50 49 );
51 50 end component;
52 51
53 52
54 53 component APB_FFT_half is
55 54 generic (
56 55 pindex : integer := 0;
57 56 paddr : integer := 0;
58 57 pmask : integer := 16#fff#;
59 58 pirq : integer := 0;
60 59 abits : integer := 8;
61 60 Data_sz : integer := 16
62 61 );
63 62 port (
64 63 clk : in std_logic; --! Horloge du composant
65 64 rst : in std_logic; --! Reset general du composant
66 65 Ren : in std_logic;
67 66 ready : out std_logic;
68 67 valid : out std_logic;
69 68 DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
70 69 DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
71 70 OUTfill : out std_logic;
72 71 OUTwrite : out std_logic;
73 72 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
74 73 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
75 74 );
76 75 end component;
77 76
77 component FFT is
78 generic(
79 Data_sz : integer := 16;
80 NbData : integer := 256);
81 port(
82 clkm : in std_logic;
83 rstn : in std_logic;
84 FifoIN_Empty : in std_logic_vector(4 downto 0);
85 FifoIN_Data : in std_logic_vector(79 downto 0);
86 FifoOUT_Full : in std_logic_vector(4 downto 0);
87 Read : out std_logic_vector(4 downto 0);
88 Write : out std_logic_vector(4 downto 0);
89 ReUse : out std_logic_vector(4 downto 0);
90 Data : out std_logic_vector(79 downto 0)
91 );
92 end component;
78 93
79 94 component Flag_Extremum is
80 95 port(
81 96 clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
82 97 load : in std_logic; --! Signal en provenance de CoreFFT
83 98 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
84 99 fill : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C)
85 100 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
86 101 );
87 102 end component;
88 103
89 104
90 105 component Linker_FFT is
91 106 generic(
92 107 Data_sz : integer range 1 to 32 := 16;
93 108 NbData : integer range 1 to 512 := 256
94 109 );
95 110 port(
96 111 clk : in std_logic;
97 112 rstn : in std_logic;
98 113 Ready : in std_logic;
99 114 Valid : in std_logic;
100 115 Full : in std_logic_vector(4 downto 0);
101 116 Data_re : in std_logic_vector(Data_sz-1 downto 0);
102 117 Data_im : in std_logic_vector(Data_sz-1 downto 0);
103 118 Read : out std_logic;
104 119 Write : out std_logic_vector(4 downto 0);
105 120 ReUse : out std_logic_vector(4 downto 0);
106 121 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
107 122 );
108 123 end component;
109 124
110 125
111 126 component Driver_FFT is
112 127 generic(
113 128 Data_sz : integer range 1 to 32 := 16;
114 129 NbData : integer range 1 to 512 := 256
115 130 );
116 131 port(
117 132 clk : in std_logic;
118 133 rstn : in std_logic;
119 134 Load : in std_logic;
120 135 Empty : in std_logic_vector(4 downto 0);
121 136 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
122 137 Valid : out std_logic;
123 138 Read : out std_logic_vector(4 downto 0);
124 139 Data_re : out std_logic_vector(Data_sz-1 downto 0);
125 140 Data_im : out std_logic_vector(Data_sz-1 downto 0)
126 141 );
127 142 end component;
128 143
129 144 component FFTamont is
130 145 generic(
131 146 Data_sz : integer range 1 to 32 := 16;
132 147 NbData : integer range 1 to 512 := 256
133 148 );
134 149 port(
135 150 clk : in std_logic;
136 151 rstn : in std_logic;
137 152 Load : in std_logic;
138 153 Empty : in std_logic;
139 154 DATA : in std_logic_vector(Data_sz-1 downto 0);
140 155 Valid : out std_logic;
141 156 Read : out std_logic;
142 157 Data_re : out std_logic_vector(Data_sz-1 downto 0);
143 158 Data_im : out std_logic_vector(Data_sz-1 downto 0)
144 159 );
145 160 end component;
146 161
147 162 component FFTaval is
148 163 generic(
149 164 Data_sz : integer range 1 to 32 := 8;
150 165 NbData : integer range 1 to 512 := 256
151 166 );
152 167 port(
153 168 clk : in std_logic;
154 169 rstn : in std_logic;
155 170 Ready : in std_logic;
156 171 Valid : in std_logic;
157 172 Full : in std_logic;
158 173 Data_re : in std_logic_vector(Data_sz-1 downto 0);
159 174 Data_im : in std_logic_vector(Data_sz-1 downto 0);
160 175 Read : out std_logic;
161 176 Write : out std_logic;
162 177 ReUse : out std_logic;
163 178 DATA : out std_logic_vector(Data_sz-1 downto 0)
164 179 );
165 180 end component;
166 181 --==============================================================|
167 182 --================== IP VHDL de la FFT actel ===================|
168 183 --================ non partag� dans la VHD_Lib =================|
169 184 --==============================================================|
170 185
171 186 component CoreFFT IS
172 187 GENERIC (
173 188 LOGPTS : integer := gLOGPTS;
174 189 LOGLOGPTS : integer := gLOGLOGPTS;
175 190 WSIZE : integer := gWSIZE;
176 191 TWIDTH : integer := gTWIDTH;
177 192 DWIDTH : integer := gDWIDTH;
178 193 TDWIDTH : integer := gTDWIDTH;
179 194 RND_MODE : integer := gRND_MODE;
180 195 SCALE_MODE : integer := gSCALE_MODE;
181 196 PTS : integer := gPTS;
182 197 HALFPTS : integer := gHALFPTS;
183 198 inBuf_RWDLY : integer := gInBuf_RWDLY );
184 199 PORT (
185 200 clk,ifiStart,ifiNreset : IN std_logic;
186 201 ifiD_valid, ifiRead_y : IN std_logic;
187 202 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
188 203 ifoLoad, ifoPong : OUT std_logic;
189 204 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
190 205 ifoY_valid, ifoY_rdy : OUT std_logic);
191 206 END component;
192 207
193 208
194 209 component actar is
195 210 port( DataA : in std_logic_vector(15 downto 0); DataB : in
196 211 std_logic_vector(15 downto 0); Mult : out
197 212 std_logic_vector(31 downto 0);Clock : in std_logic) ;
198 213 end component;
199 214
200 215 component actram is
201 216 port( DI : in std_logic_vector(31 downto 0); DO : out
202 217 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
203 218 WADDR : in std_logic_vector(6 downto 0); RADDR : in
204 219 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
205 220 std_logic) ;
206 221 end component;
207 222
208 223 component switch IS
209 224 GENERIC ( DWIDTH : integer := 32 );
210 225 PORT (
211 226 clk, sel, validIn : IN std_logic;
212 227 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
213 228 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
214 229 validOut : OUT std_logic);
215 230 END component;
216 231
217 232 component twid_rA IS
218 233 GENERIC (LOGPTS : integer := 8;
219 234 LOGLOGPTS : integer := 3 );
220 235 PORT (clk : IN std_logic;
221 236 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
222 237 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
223 238 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
224 239 END component;
225 240
226 241 component counter IS
227 242 GENERIC (
228 243 WIDTH : integer := 7;
229 244 TERMCOUNT : integer := 127 );
230 245 PORT (
231 246 clk, nGrst, rst, cntEn : IN std_logic;
232 247 tc : OUT std_logic;
233 248 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
234 249 END component;
235 250
236 251
237 252 component twiddle IS
238 253 PORT (
239 254 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
240 255 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
241 256 END component;
242 257
243 258
244 259 end; No newline at end of file
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@@ -1,77 +1,63
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
26 USE lpp.general_purpose.ALL;
27 --IDLE = 0000
28 --MAC = 0001
29 --MULT = 0010 and set MULT in ADD reg
30 --ADD = 0011
31 --CLRMAC = 0100
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
27
28 --! Une ALU : Arithmetic and logical unit, permettant de r�aliser une ou plusieurs op�ration
32 29
33
34 ENTITY ALU IS
35 GENERIC(
36 Arith_en : INTEGER := 1;
37 Logic_en : INTEGER := 1;
38 Input_SZ_1 : INTEGER := 16;
39 Input_SZ_2 : INTEGER := 9
40
30 entity ALU is
31 generic(
32 Arith_en : integer := 1;
33 Logic_en : integer := 1;
34 Input_SZ_1 : integer := 16;
35 Input_SZ_2 : integer := 16);
36 port(
37 clk : in std_logic; --! Horloge du composant
38 reset : in std_logic; --! Reset general du composant
39 ctrl : in std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
40 comp : in std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes
41 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
42 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Second Op�rande
43 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) --! R�sultat de l'op�ration
41 44 );
42 PORT(
43 clk : IN STD_LOGIC;
44 reset : IN STD_LOGIC;
45 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
47 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
48 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
49 );
50 END ENTITY;
45 end ALU;
51 46
52 ARCHITECTURE ar_ALU OF ALU IS
53
54 SIGNAL clr_MAC : STD_LOGIC := '1';
55
56 BEGIN
57 clr_MAC <= '1' WHEN ctrl = "0100" OR ctrl = "0101" OR ctrl = "0110" ELSE '0';
47 --! @details S�lection grace a l'entr�e "ctrl" :
48 --! Pause : IDLE = 000
49 --! Multiplieur/Accumulateur : MAC = 001
50 --! Multiplication : MULT = 010
51 --! Addition : ADD = 011
52 --! Reset du MAC : CLRMAC = 100
53 architecture ar_ALU of ALU is
58 54
59 arith : IF Arith_en = 1 GENERATE
60 MACinst : MAC
61 GENERIC MAP(Input_SZ_1, Input_SZ_2)
62 PORT MAP(clk, reset, clr_MAC, ctrl(1 DOWNTO 0), OP1, OP2, RES);
63 END GENERATE;
64
65 END ARCHITECTURE;
66
67
55 begin
68 56
69
70
71
72
57 arith : if Arith_en = 1 generate
58 MACinst : MAC
59 generic map(Input_SZ_1,Input_SZ_2)
60 port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES);
61 end generate;
73 62
74
75
76
77
63 end architecture; No newline at end of file
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@@ -1,262 +1,294
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY lpp;
26 26 USE lpp.general_purpose.ALL;
27 27 --TODO
28 28 --terminer le testbensh puis changer le resize dans les instanciations
29 29 --par un resize sur un vecteur en combi
30 30
31 31
32 32 ENTITY MAC IS
33 33 GENERIC(
34 34 Input_SZ_A : INTEGER := 8;
35 35 Input_SZ_B : INTEGER := 8
36 36
37 37 );
38 38 PORT(
39 39 clk : IN STD_LOGIC;
40 40 reset : IN STD_LOGIC;
41 41 clr_MAC : IN STD_LOGIC;
42 42 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
43 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
43 44 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
44 45 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
45 46 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
46 47 );
47 48 END MAC;
48 49
49 50
50 51
51 52
52 53 ARCHITECTURE ar_MAC OF MAC IS
53 54
54 SIGNAL add, mult : STD_LOGIC;
55 SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
55 signal add,mult : std_logic;
56 signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
56 57
57 SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
58 SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
59 SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
60
58 signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
59 signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
60 signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
61 61
62 SIGNAL MACMUXsel : STD_LOGIC;
63 SIGNAL OP1_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
64 SIGNAL OP2_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
65
62 signal MACMUXsel : std_logic;
63 signal OP1_2C_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
64 signal OP2_2C_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
66 65
66 signal OP1_2C : std_logic_vector(Input_SZ_A-1 downto 0);
67 signal OP2_2C : std_logic_vector(Input_SZ_B-1 downto 0);
67 68
68 SIGNAL MACMUX2sel : STD_LOGIC;
69 signal MACMUX2sel : std_logic;
69 70
70 SIGNAL add_D : STD_LOGIC;
71 SIGNAL OP1_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
72 SIGNAL OP2_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
73 SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
74 SIGNAL MACMUXsel_D : STD_LOGIC;
75 SIGNAL MACMUX2sel_D : STD_LOGIC;
76 SIGNAL MACMUX2sel_D_D : STD_LOGIC;
77 SIGNAL clr_MAC_D : STD_LOGIC;
78 SIGNAL clr_MAC_D_D : STD_LOGIC;
71 signal add_D : std_logic;
72 signal OP1_2C_D : std_logic_vector(Input_SZ_A-1 downto 0);
73 signal OP2_2C_D : std_logic_vector(Input_SZ_B-1 downto 0);
74 signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
75 signal MACMUXsel_D : std_logic;
76 signal MACMUX2sel_D : std_logic;
77 signal MACMUX2sel_D_D : std_logic;
78 signal clr_MAC_D : std_logic;
79 signal clr_MAC_D_D : std_logic;
80 signal MAC_MUL_ADD_2C_D : std_logic_vector(1 downto 0);
79 81
80 82 SIGNAL load_mult_result : STD_LOGIC;
81 83 SIGNAL load_mult_result_D : STD_LOGIC;
82 84
83 85 BEGIN
84 86
85 87
86 88
87 89
88 90 --==============================================================
89 91 --=============M A C C O N T R O L E R=========================
90 92 --==============================================================
91 93 MAC_CONTROLER1 : MAC_CONTROLER
92 94 PORT MAP(
93 95 ctrl => MAC_MUL_ADD,
94 96 MULT => mult,
95 97 ADD => add,
96 98 LOAD_ADDER => load_mult_result,
97 99 MACMUX_sel => MACMUXsel,
98 100 MACMUX2_sel => MACMUX2sel
99 101
100 102 );
101 103 --==============================================================
102 104
103 105
104 106
105 107
106 108 --==============================================================
107 109 --=============M U L T I P L I E R==============================
108 110 --==============================================================
109 111 Multiplieri_nst : Multiplier
110 112 GENERIC MAP(
111 113 Input_SZ_A => Input_SZ_A,
112 114 Input_SZ_B => Input_SZ_B
113 115 )
114 PORT MAP(
116 port map(
115 117 clk => clk,
116 118 reset => reset,
117 119 mult => mult,
118 OP1 => OP1,
119 OP2 => OP2,
120 OP1 => OP1_2C,
121 OP2 => OP2_2C,
120 122 RES => MULTout
121 123 );
122 124 --==============================================================
123 125
124 126 PROCESS (clk, reset)
125 127 BEGIN -- PROCESS
126 128 IF reset = '0' THEN -- asynchronous reset (active low)
127 129 load_mult_result_D <= '0';
128 130 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
129 131 load_mult_result_D <= load_mult_result;
130 132 END IF;
131 133 END PROCESS;
132 134
133 135 --==============================================================
134 136 --======================A D D E R ==============================
135 137 --==============================================================
136 138 adder_inst : Adder
137 139 GENERIC MAP(
138 140 Input_SZ_A => Input_SZ_A+Input_SZ_B,
139 141 Input_SZ_B => Input_SZ_A+Input_SZ_B
140 142 )
141 143 PORT MAP(
142 144 clk => clk,
143 145 reset => reset,
144 146 clr => clr_MAC_D,
145 147 load => load_mult_result_D,
146 148 add => add_D,
147 149 OP1 => ADDERinA,
148 150 OP2 => ADDERinB,
149 151 RES => ADDERout
150 152 );
153
151 154 --==============================================================
155 --===================TWO COMPLEMENTERS==========================
156 --==============================================================
157 TWO_COMPLEMENTER1 : TwoComplementer
158 generic map(
159 Input_SZ => Input_SZ_A
160 )
161 port map(
162 clk => clk,
163 reset => reset,
164 clr => clr_MAC,
165 TwoComp => Comp_2C(0),
166 OP => OP1,
167 RES => OP1_2C
168 );
152 169
153 170
171 TWO_COMPLEMENTER2 : TwoComplementer
172 generic map(
173 Input_SZ => Input_SZ_B
174 )
175 port map(
176 clk => clk,
177 reset => reset,
178 clr => clr_MAC,
179 TwoComp => Comp_2C(1),
180 OP => OP2,
181 RES => OP2_2C
182 );
183 --==============================================================
184
154 185 clr_MACREG1 : MAC_REG
155 186 GENERIC MAP(size => 1)
156 187 PORT MAP(
157 188 reset => reset,
158 189 clk => clk,
159 190 D(0) => clr_MAC,
160 191 Q(0) => clr_MAC_D
161 192 );
162 193
163 194 addREG : MAC_REG
164 195 GENERIC MAP(size => 1)
165 196 PORT MAP(
166 197 reset => reset,
167 198 clk => clk,
168 199 D(0) => add,
169 200 Q(0) => add_D
170 201 );
171 202
172 203 OP1REG : MAC_REG
173 GENERIC MAP(size => Input_SZ_A)
174 PORT MAP(
204 generic map(size => Input_SZ_A)
205 port map(
175 206 reset => reset,
176 207 clk => clk,
177 D => OP1,
178 Q => OP1_D
208 D => OP1_2C,
209 Q => OP1_2C_D
179 210 );
180 211
212
181 213 OP2REG : MAC_REG
182 GENERIC MAP(size => Input_SZ_B)
183 PORT MAP(
214 generic map(size => Input_SZ_B)
215 port map(
184 216 reset => reset,
185 217 clk => clk,
186 D => OP2,
187 Q => OP2_D
218 D => OP2_2C,
219 Q => OP2_2C_D
188 220 );
189 221
190 222 MULToutREG : MAC_REG
191 223 GENERIC MAP(size => Input_SZ_A+Input_SZ_B)
192 224 PORT MAP(
193 225 reset => reset,
194 226 clk => clk,
195 227 D => MULTout,
196 228 Q => MULTout_D
197 229 );
198 230
199 231 MACMUXselREG : MAC_REG
200 232 GENERIC MAP(size => 1)
201 233 PORT MAP(
202 234 reset => reset,
203 235 clk => clk,
204 236 D(0) => MACMUXsel,
205 237 Q(0) => MACMUXsel_D
206 238 );
207 239
208 240 MACMUX2selREG : MAC_REG
209 241 GENERIC MAP(size => 1)
210 242 PORT MAP(
211 243 reset => reset,
212 244 clk => clk,
213 245 D(0) => MACMUX2sel,
214 246 Q(0) => MACMUX2sel_D
215 247 );
216 248
217 249 MACMUX2selREG2 : MAC_REG
218 250 GENERIC MAP(size => 1)
219 251 PORT MAP(
220 252 reset => reset,
221 253 clk => clk,
222 254 D(0) => MACMUX2sel_D,
223 255 Q(0) => MACMUX2sel_D_D
224 256 );
225 257
226 258 --==============================================================
227 259 --======================M A C M U X ===========================
228 260 --==============================================================
229 261 MACMUX_inst : MAC_MUX
230 262 GENERIC MAP(
231 263 Input_SZ_A => Input_SZ_A+Input_SZ_B,
232 264 Input_SZ_B => Input_SZ_A+Input_SZ_B
233 265
234 266 )
235 267 PORT MAP(
236 268 sel => MACMUXsel_D,
237 269 INA1 => ADDERout,
238 INA2 => OP2_D_Resz,
270 INA2 => OP2_2C_D_Resz,
239 271 INB1 => MULTout,
240 INB2 => OP1_D_Resz,
272 INB2 => OP1_2C_D_Resz,
241 273 OUTA => ADDERinA,
242 274 OUTB => ADDERinB
243 275 );
244 OP1_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_D), Input_SZ_A+Input_SZ_B));
245 OP2_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_D), Input_SZ_A+Input_SZ_B));
276 OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B));
277 OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B));
246 278 --==============================================================
247 279
248 280
249 281 --==============================================================
250 282 --======================M A C M U X2 ==========================
251 283 --==============================================================
252 284 MAC_MUX2_inst : MAC_MUX2
253 285 GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B)
254 286 PORT MAP(
255 287 sel => MACMUX2sel_D_D,
256 288 RES2 => MULTout_D,
257 289 RES1 => ADDERout,
258 290 RES => RES
259 291 );
260 292 --==============================================================
261 293
262 294 END ar_MAC;
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@@ -1,248 +1,271
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 --UPDATE
23 23 -------------------------------------------------------------------------------
24 24 -- 14-03-2013 - Jean-christophe Pellion
25 25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
26 26 -------------------------------------------------------------------------------
27 27
28 28 LIBRARY ieee;
29 29 USE ieee.std_logic_1164.ALL;
30 30
31 31
32 32
33 33 PACKAGE general_purpose IS
34 34
35 35
36 36
37 37 COMPONENT Clk_divider IS
38 38 GENERIC(OSC_freqHz : INTEGER := 50000000;
39 39 TargetFreq_Hz : INTEGER := 50000);
40 40 PORT (clk : IN STD_LOGIC;
41 41 reset : IN STD_LOGIC;
42 42 clk_divided : OUT STD_LOGIC);
43 43 END COMPONENT;
44 44
45 45
46 46 COMPONENT Clk_divider2 IS
47 47 generic(N : integer := 16);
48 48 port(
49 49 clk_in : in std_logic;
50 50 clk_out : out std_logic);
51 51 END COMPONENT;
52 52
53 53 COMPONENT Adder IS
54 54 GENERIC(
55 55 Input_SZ_A : INTEGER := 16;
56 56 Input_SZ_B : INTEGER := 16
57 57
58 58 );
59 59 PORT(
60 60 clk : IN STD_LOGIC;
61 61 reset : IN STD_LOGIC;
62 62 clr : IN STD_LOGIC;
63 63 load : IN STD_LOGIC;
64 64 add : IN STD_LOGIC;
65 65 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
66 66 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
67 67 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
68 68 );
69 69 END COMPONENT;
70 70
71 71 COMPONENT ADDRcntr IS
72 72 PORT(
73 73 clk : IN STD_LOGIC;
74 74 reset : IN STD_LOGIC;
75 75 count : IN STD_LOGIC;
76 76 clr : IN STD_LOGIC;
77 77 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
78 78 );
79 79 END COMPONENT;
80 80
81 81 COMPONENT ALU IS
82 82 GENERIC(
83 83 Arith_en : INTEGER := 1;
84 84 Logic_en : INTEGER := 1;
85 85 Input_SZ_1 : INTEGER := 16;
86 86 Input_SZ_2 : INTEGER := 9
87 87
88 88 );
89 89 PORT(
90 90 clk : IN STD_LOGIC;
91 91 reset : IN STD_LOGIC;
92 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
92 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
93 comp : IN STD_LOGIC_VECTOR(1 downto 0);
93 94 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
94 95 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
95 96 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
96 97 );
97 98 END COMPONENT;
98 99
100 ---------------------------------------------------------
101 -------- // S�lection grace a l'entr�e "ctrl" \\ --------
102 ---------------------------------------------------------
103 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
104 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
105 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
106 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
107 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
108 ---------------------------------------------------------
99 109
100 110 COMPONENT MAC IS
101 111 GENERIC(
102 112 Input_SZ_A : INTEGER := 8;
103 113 Input_SZ_B : INTEGER := 8
104 114
105 115 );
106 116 PORT(
107 117 clk : IN STD_LOGIC;
108 118 reset : IN STD_LOGIC;
109 119 clr_MAC : IN STD_LOGIC;
110 120 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
121 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
111 122 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
112 123 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
113 124 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
114 125 );
115 126 END COMPONENT;
116 127
128 COMPONENT TwoComplementer is
129 generic(
130 Input_SZ : integer := 16);
131 port(
132 clk : in std_logic; --! Horloge du composant
133 reset : in std_logic; --! Reset general du composant
134 clr : in std_logic; --! Un reset sp�cifique au programme
135 TwoComp : in std_logic; --! Autorise l'utilisation du compl�ment
136 OP : in std_logic_vector(Input_SZ-1 downto 0); --! Op�rande d'entr�e
137 RES : out std_logic_vector(Input_SZ-1 downto 0) --! R�sultat, op�rande compl�ment� ou non
138 );
139 end COMPONENT;
117 140
118 141 COMPONENT MAC_CONTROLER IS
119 142 PORT(
120 143 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
121 144 MULT : OUT STD_LOGIC;
122 145 ADD : OUT STD_LOGIC;
123 146 LOAD_ADDER : out std_logic;
124 147 MACMUX_sel : OUT STD_LOGIC;
125 148 MACMUX2_sel : OUT STD_LOGIC
126 149 );
127 150 END COMPONENT;
128 151
129 152 COMPONENT MAC_MUX IS
130 153 GENERIC(
131 154 Input_SZ_A : INTEGER := 16;
132 155 Input_SZ_B : INTEGER := 16
133 156
134 157 );
135 158 PORT(
136 159 sel : IN STD_LOGIC;
137 160 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
138 161 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
139 162 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
140 163 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
141 164 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
142 165 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
143 166 );
144 167 END COMPONENT;
145 168
146 169
147 170 COMPONENT MAC_MUX2 IS
148 171 GENERIC(Input_SZ : INTEGER := 16);
149 172 PORT(
150 173 sel : IN STD_LOGIC;
151 174 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
152 175 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
153 176 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
154 177 );
155 178 END COMPONENT;
156 179
157 180
158 181 COMPONENT MAC_REG IS
159 182 GENERIC(size : INTEGER := 16);
160 183 PORT(
161 184 reset : IN STD_LOGIC;
162 185 clk : IN STD_LOGIC;
163 186 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
164 187 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
165 188 );
166 189 END COMPONENT;
167 190
168 191
169 192 COMPONENT MUX2 IS
170 193 GENERIC(Input_SZ : INTEGER := 16);
171 194 PORT(
172 195 sel : IN STD_LOGIC;
173 196 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
174 197 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
175 198 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
176 199 );
177 200 END COMPONENT;
178 201
179 202 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
180 203 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
181 204
182 205 COMPONENT MUXN
183 206 GENERIC (
184 207 Input_SZ : INTEGER;
185 208 NbStage : INTEGER);
186 209 PORT (
187 210 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
188 211 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
189 212 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
190 213 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
191 214 END COMPONENT;
192 215
193 216
194 217
195 218 COMPONENT Multiplier IS
196 219 GENERIC(
197 220 Input_SZ_A : INTEGER := 16;
198 221 Input_SZ_B : INTEGER := 16
199 222
200 223 );
201 224 PORT(
202 225 clk : IN STD_LOGIC;
203 226 reset : IN STD_LOGIC;
204 227 mult : IN STD_LOGIC;
205 228 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
206 229 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
207 230 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
208 231 );
209 232 END COMPONENT;
210 233
211 234 COMPONENT REG IS
212 235 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
213 236 PORT(
214 237 reset : IN STD_LOGIC;
215 238 clk : IN STD_LOGIC;
216 239 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
217 240 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
218 241 );
219 242 END COMPONENT;
220 243
221 244
222 245
223 246 COMPONENT RShifter IS
224 247 GENERIC(
225 248 Input_SZ : INTEGER := 16;
226 249 shift_SZ : INTEGER := 4
227 250 );
228 251 PORT(
229 252 clk : IN STD_LOGIC;
230 253 reset : IN STD_LOGIC;
231 254 shift : IN STD_LOGIC;
232 255 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
233 256 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
234 257 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
235 258 );
236 259 END COMPONENT;
237 260
238 261 COMPONENT SYNC_FF
239 262 GENERIC (
240 263 NB_FF_OF_SYNC : INTEGER);
241 264 PORT (
242 265 clk : IN STD_LOGIC;
243 266 rstn : IN STD_LOGIC;
244 267 A : IN STD_LOGIC;
245 268 A_sync : OUT STD_LOGIC);
246 269 END COMPONENT;
247 270
248 271 END;
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@@ -1,612 +1,619
1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19
20 20
21 21 library ieee;
22 22 use ieee.std_logic_1164.all;
23 23 library grlib;
24 24 use grlib.amba.all;
25 25 use grlib.stdlib.all;
26 26 library techmap;
27 27 use techmap.gencomp.all;
28 28 library gaisler;
29 29 use gaisler.memctrl.all;
30 30 use gaisler.leon3.all;
31 31 use gaisler.uart.all;
32 32 use gaisler.misc.all;
33 33 library esa;
34 34 use esa.memoryctrl.all;
35 35 use work.config.all;
36 36 library lpp;
37 37 use lpp.lpp_amba.all;
38 38 use lpp.lpp_memory.all;
39 39 use lpp.lpp_uart.all;
40 40 use lpp.lpp_matrix.all;
41 41 use lpp.lpp_delay.all;
42 42 use lpp.lpp_fft.all;
43 43 use lpp.fft_components.all;
44 44 use lpp.lpp_ad_conv.all;
45 45 use lpp.iir_filter.all;
46 46 use lpp.general_purpose.all;
47 47 use lpp.Filtercfg.all;
48 use lpp.lpp_demux.all;
49 use lpp.lpp_top_lfr_pkg.all;
48 50
49 51 entity leon3mp is
50 52 generic (
51 53 fabtech : integer := CFG_FABTECH;
52 54 memtech : integer := CFG_MEMTECH;
53 55 padtech : integer := CFG_PADTECH;
54 56 clktech : integer := CFG_CLKTECH;
55 57 disas : integer := CFG_DISAS; -- Enable disassembly to console
56 58 dbguart : integer := CFG_DUART; -- Print UART on console
57 59 pclow : integer := CFG_PCLOW
58 60 );
59 61 port (
60 62 clk50MHz : in std_ulogic;
61 63 reset : in std_ulogic;
62 64 ramclk : out std_logic;
63 65
64 66 ahbrxd : in std_ulogic; -- DSU rx data
65 67 ahbtxd : out std_ulogic; -- DSU tx data
66 68 dsubre : in std_ulogic;
67 69 dsuact : out std_ulogic;
68 70 urxd1 : in std_ulogic; -- UART1 rx data
69 71 utxd1 : out std_ulogic; -- UART1 tx data
70 72 errorn : out std_ulogic;
71 73
72 74 address : out std_logic_vector(18 downto 0);
73 75 data : inout std_logic_vector(31 downto 0);
74 76 gpio : inout std_logic_vector(6 downto 0); -- I/O port
75 77
76 78 nBWa : out std_logic;
77 79 nBWb : out std_logic;
78 80 nBWc : out std_logic;
79 81 nBWd : out std_logic;
80 82 nBWE : out std_logic;
81 83 nADSC : out std_logic;
82 84 nADSP : out std_logic;
83 85 nADV : out std_logic;
84 86 nGW : out std_logic;
85 87 nCE1 : out std_logic;
86 88 CE2 : out std_logic;
87 89 nCE3 : out std_logic;
88 90 nOE : out std_logic;
89 91 MODE : out std_logic;
90 92 SSRAM_CLK : out std_logic;
91 93 ZZ : out std_logic;
92 94 ---------------------------------------------------------------------
93 95 --- AJOUT TEST ------------------------In/Out-----------------------
94 96 ---------------------------------------------------------------------
95 97 -- UART
96 98 UART_RXD : in std_logic;
97 99 UART_TXD : out std_logic;
100 -- ACQ
101 Clk_49Mhz : IN STD_LOGIC;
102 CNV_CH1 : OUT STD_LOGIC;
103 SCK_CH1 : OUT STD_LOGIC;
104 SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
98 105 -- ADC
99 106 -- ADC_in : in AD7688_in(4 downto 0);
100 107 -- ADC_out : out AD7688_out;
101 108 -- Bias_Fails : out std_logic;
102 109 -- CNA
103 110 -- DAC_SYNC : out std_logic;
104 111 -- DAC_SCLK : out std_logic;
105 112 -- DAC_DATA : out std_logic;
106 113 -- Diver
107 114 SPW1_EN : out std_logic;
108 115 SPW2_EN : out std_logic;
109 116 TEST : out std_logic_vector(3 downto 0);
110 117
111 118 BP : in std_logic;
112 119 ---------------------------------------------------------------------
113 120 led : out std_logic_vector(1 downto 0)
114 121 );
115 122 end;
116 123
117 124 architecture Behavioral of leon3mp is
118 125
119 126 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
120 127 CFG_GRETH+CFG_AHB_JTAG;
121 128 constant maxahbm : integer := maxahbmsp;
122 129
123 130 --Clk & Rst g�n�
124 131 signal vcc : std_logic_vector(4 downto 0);
125 132 signal gnd : std_logic_vector(4 downto 0);
126 133 signal resetnl : std_ulogic;
127 134 signal clk2x : std_ulogic;
128 135 signal lclk : std_ulogic;
129 136 signal lclk2x : std_ulogic;
130 137 signal clkm : std_ulogic;
131 138 signal rstn : std_ulogic;
132 139 signal rstraw : std_ulogic;
133 140 signal pciclk : std_ulogic;
134 141 signal sdclkl : std_ulogic;
135 142 signal cgi : clkgen_in_type;
136 143 signal cgo : clkgen_out_type;
137 144 --- AHB / APB
138 145 signal apbi : apb_slv_in_type;
139 146 signal apbo : apb_slv_out_vector := (others => apb_none);
140 147 signal ahbsi : ahb_slv_in_type;
141 148 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
142 149 signal ahbmi : ahb_mst_in_type;
143 150 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
144 151 --UART
145 152 signal ahbuarti : uart_in_type;
146 153 signal ahbuarto : uart_out_type;
147 154 signal apbuarti : uart_in_type;
148 155 signal apbuarto : uart_out_type;
149 156 --MEM CTRLR
150 157 signal memi : memory_in_type;
151 158 signal memo : memory_out_type;
152 159 signal wpo : wprot_out_type;
153 160 signal sdo : sdram_out_type;
154 161 --IRQ
155 162 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
156 163 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
157 164 --Timer
158 165 signal gpti : gptimer_in_type;
159 166 signal gpto : gptimer_out_type;
160 167 --GPIO
161 168 signal gpioi : gpio_in_type;
162 169 signal gpioo : gpio_out_type;
163 170 --DSU
164 171 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
165 172 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
166 173 signal dsui : dsu_in_type;
167 174 signal dsuo : dsu_out_type;
168 175
169 176 ---------------------------------------------------------------------
170 177 --- AJOUT TEST ------------------------Signaux----------------------
171 178 ---------------------------------------------------------------------
172 179 -- FIFOs
173 signal FifoIN_Full : std_logic_vector(4 downto 0);
174 signal FifoIN_Empty : std_logic_vector(4 downto 0);
175 signal FifoIN_Data : std_logic_vector(79 downto 0);
180 signal FifoF0a_Full : std_logic_vector(4 downto 0);
181 signal FifoF0a_Empty : std_logic_vector(4 downto 0);
182 signal FifoF0a_Data : std_logic_vector(79 downto 0);
183 signal FifoF0b_Full : std_logic_vector(4 downto 0);
184 signal FifoF0b_Empty : std_logic_vector(4 downto 0);
185 signal FifoF0b_Data : std_logic_vector(79 downto 0);
186 signal FifoF1_Full : std_logic_vector(4 downto 0);
187 signal FifoF1_Empty : std_logic_vector(4 downto 0);
188 signal FifoF1_Data : std_logic_vector(79 downto 0);
189 signal FifoF3_Full : std_logic_vector(4 downto 0);
190 signal FifoF3_Empty : std_logic_vector(4 downto 0);
191 signal FifoF3_Data : std_logic_vector(79 downto 0);
176 192
177 193 signal FifoINT_Full : std_logic_vector(4 downto 0);
178 194 signal FifoINT_Data : std_logic_vector(79 downto 0);
179 195
180 signal FifoOUT_FullV : std_logic;
196 --signal FifoOUT_FullV : std_logic;
181 197 signal FifoOUT_Full : std_logic_vector(1 downto 0);
182 signal Matrix_WriteV : std_logic_vector(0 downto 0);
198 --signal Matrix_WriteV : std_logic_vector(0 downto 0);
183 199
184 200 -- MATRICE SPECTRALE
185 signal Matrix_Write : std_logic;
186 signal Matrix_Read : std_logic_vector(1 downto 0);
187 signal Matrix_Result : std_logic_vector(31 downto 0);
201 signal SM_FlagError : std_logic;
202 signal SM_Pong : std_logic;
203 signal SM_Read : std_logic_vector(4 downto 0);
204 signal SM_Write : std_logic_vector(1 downto 0);
205 signal SM_Data : std_logic_vector(63 downto 0);
188 206
189 signal TopSM_Start : std_logic;
190 signal TopSM_Statu : std_logic_vector(3 downto 0);
191 signal TopSM_Read : std_logic_vector(4 downto 0);
192 signal TopSM_Data1 : std_logic_vector(15 downto 0);
193 signal TopSM_Data2 : std_logic_vector(15 downto 0);
194
195 signal Disp_FlagError : std_logic;
196 signal Disp_Pong : std_logic;
197 signal Disp_Write : std_logic_vector(1 downto 0);--
198 signal Disp_Data : std_logic_vector(63 downto 0);--
199 207 signal Dma_acq : std_logic;
200 208
201 209 -- FFT
202 signal Drive_Write : std_logic;
203 signal Drive_Read : std_logic_vector(4 downto 0);
204 signal Drive_DataRE : std_logic_vector(15 downto 0);
205 signal Drive_DataIM : std_logic_vector(15 downto 0);
210 signal FFT_Read : std_logic_vector(4 downto 0);
211 signal FFT_Write : std_logic_vector(4 downto 0);
212 signal FFT_ReUse : std_logic_vector(4 downto 0);
213 signal FFT_Data : std_logic_vector(79 downto 0);
206 214
207 signal Start : std_logic;
208 signal RstnFFT : std_logic;
209 signal FFT_Load : std_logic;
210 signal FFT_Ready : std_logic;
211 signal FFT_Valid : std_logic;
212 signal FFT_DataRE : std_logic_vector(15 downto 0);
213 signal FFT_DataIM : std_logic_vector(15 downto 0);
215 -- DEMUX
216 signal DEMU_Read : std_logic_vector(19 downto 0);
217 signal DEMU_Empty : std_logic_vector(4 downto 0);
218 signal DEMU_Data : std_logic_vector(79 downto 0);
214 219
215 signal Link_Read : std_logic;
216 signal Link_Write : std_logic_vector(4 downto 0);
217 signal Link_ReUse : std_logic_vector(4 downto 0);
218 signal Link_Data : std_logic_vector(79 downto 0);
220 -- ACQ
221 signal TopACQ_WenF0a : STD_LOGIC_VECTOR(4 DOWNTO 0);
222 signal TopACQ_WenF0b : STD_LOGIC_VECTOR(4 DOWNTO 0);
223 signal TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
224 signal TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
225 signal TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
226 signal TopACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0);
227 signal TopACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
219 228
220 229 -- ADC
221 signal SmplClk : std_logic;
222 signal ADC_DataReady : std_logic;
223 signal ADC_SmplOut : Samples_out(4 downto 0);
224 signal enableADC : std_logic;
225
226 signal WG_Write : std_logic_vector(4 downto 0);
227 signal WG_ReUse : std_logic_vector(4 downto 0);
228 signal WG_DATA : std_logic_vector(79 downto 0);
229 signal s_out : std_logic_vector(79 downto 0);
230
231 signal fuller : std_logic_vector(4 downto 0);
232 signal reader : std_logic_vector(4 downto 0);
233 signal try : std_logic_vector(1 downto 0);
234 signal TXDint : std_logic;
235
236 -- IIR Filter
237 signal sample_clk_out : std_logic;
238
239 signal Rd : std_logic_vector(0 downto 0);
240 signal Ept : std_logic_vector(4 downto 0);
241
242 signal Bwr : std_logic_vector(0 downto 0);
243 signal Bre : std_logic_vector(0 downto 0);
244 signal DataTMP : std_logic_vector(15 downto 0);
245 signal FullUp : std_logic_vector(0 downto 0);
246 signal EmptyUp : std_logic_vector(0 downto 0);
247 signal FullDown : std_logic_vector(0 downto 0);
248 signal EmptyDown : std_logic_vector(0 downto 0);
230 --signal SmplClk : std_logic;
231 --signal ADC_DataReady : std_logic;
232 --signal ADC_SmplOut : Samples_out(4 downto 0);
233 --signal enableADC : std_logic;
234 --
235 --signal WG_Write : std_logic_vector(4 downto 0);
236 --signal WG_ReUse : std_logic_vector(4 downto 0);
237 --signal WG_DATA : std_logic_vector(79 downto 0);
238 --signal s_out : std_logic_vector(79 downto 0);
239 --
240 --signal fuller : std_logic_vector(4 downto 0);
241 --signal reader : std_logic_vector(4 downto 0);
242 --signal try : std_logic_vector(1 downto 0);
243 --signal TXDint : std_logic;
244 --
245 ---- IIR Filter
246 --signal sample_clk_out : std_logic;
247 --
248 --signal Rd : std_logic_vector(0 downto 0);
249 --signal Ept : std_logic_vector(4 downto 0);
250 --
251 --signal Bwr : std_logic_vector(0 downto 0);
252 --signal Bre : std_logic_vector(0 downto 0);
253 --signal DataTMP : std_logic_vector(15 downto 0);
254 --signal FullUp : std_logic_vector(0 downto 0);
255 --signal EmptyUp : std_logic_vector(0 downto 0);
256 --signal FullDown : std_logic_vector(0 downto 0);
257 --signal EmptyDown : std_logic_vector(0 downto 0);
249 258 ---------------------------------------------------------------------
250 259 constant IOAEN : integer := CFG_CAN;
251 260 constant boardfreq : integer := 50000;
252 261
253 262 begin
254 263
255 264 ---------------------------------------------------------------------
256 265 --- AJOUT TEST -------------------------------------IPs-------------
257 266 ---------------------------------------------------------------------
258 267 led(1 downto 0) <= gpio(1 downto 0);
259 268
260 269 --- COM USB ---------------------------------------------------------
261 270 -- MemIn0 : APB_FifoWrite
262 271 -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
263 272 -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5));
264 273 --
265 274 -- BUF0 : APB_USB
266 275 -- generic map (6,6,DataMax => 1024)
267 276 -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6));
268 277 --
269 278 -- MemOut0 : APB_FifoRead
270 279 -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
271 280 -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7));
272 281 --
273 282 --slrd <= usb_Read;
274 283 --slwr <= usb_Write;
275 284
276 285 --- CNA -------------------------------------------------------------
277 286
278 287 -- CONV : APB_CNA
279 288 -- generic map (5,5)
280 289 -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA);
281 290
282 291 --TEST(0) <= SmplClk;
283 292 --TEST(1) <= WG_Write(0);
284 293 --TEST(2) <= Fuller(0);
285 294 --TEST(3) <= s_out(s_out'length-1);
286 295
287 296
288 297 --SPW1_EN <= '1';
289 298 --SPW2_EN <= '0';
290 299
291 300 --- CAN -------------------------------------------------------------
292 301
293 302 -- Divider : Clk_divider
294 303 -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576)
295 304 -- Port map(clkm,rstn,SmplClk);
296 305 --
297 306 -- ADC : AD7688_drvr
298 307 -- generic map (ChanelCount => 5, clkkHz => 24_576)
299 308 -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out);
300 309 --
301 310 -- WG : WriteGen_ADC
302 311 -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
303 312 --
304 313 --enableADC <= gpio(0);
305 314 --Bias_Fails <= '0';
306 315 --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
307 316 --
308 317 --
309 318 -- MemIn1 : APB_FIFO
310 319 -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
311 320 -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
312 321
322 TopACQ : lpp_top_acq
323 port map('1',CNV_CH1,SCK_CH1,SDO_CH1,Clk_49Mhz,rstn,clkm,rstn,TopACQ_WenF0a,TopACQ_WenF0b,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3);
324
325 --- FIFO IN -------------------------------------------------------------
326
327 Memf0a : lppFIFOxN
328 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
329 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0a,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0a_Data,FifoF0a_Full,FifoF0a_Empty);
330
331 Memf0b : lppFIFOxN
332 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
333 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0b,DEMU_Read(9 downto 5),TopACQ_DataF0,FifoF0b_Data,FifoF0b_Full,FifoF0b_Empty);
334
335 Memf1 : lppFIFOxN
336 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
337 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(14 downto 10),TopACQ_DataF1,FifoF1_Data,FifoF1_Full,FifoF1_Empty);
338
339 Memf3 : lppFIFOxN
340 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
341 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(19 downto 15),TopACQ_DataF3,FifoF3_Data,FifoF3_Full,FifoF3_Empty);
342
343 --- DEMUX -------------------------------------------------------------
344
345 DEMUX0 : Demultiplex
346 generic map(Data_sz => 16)
347 port map(clkm,rstn,FFT_Read,FifoF0a_Empty,FifoF0b_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0a_Data,FifoF0b_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data);
348
313 349 --- FFT -------------------------------------------------------------
314 350
315 MemIn : APB_FIFO
316 generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
317 port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8));
318
319 DRIVE : Driver_FFT
320 generic map(Data_sz => 16)
321 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Drive_Read,Drive_DataRE,Drive_DataIM);
322
323 Start <= '0';
351 -- MemIn : APB_FIFO
352 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
353 -- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8));
324 354
325 FFT : CoreFFT
326 generic map(
327 LOGPTS => gLOGPTS,
328 LOGLOGPTS => gLOGLOGPTS,
329 WSIZE => gWSIZE,
330 TWIDTH => gTWIDTH,
331 DWIDTH => gDWIDTH,
332 TDWIDTH => gTDWIDTH,
333 RND_MODE => gRND_MODE,
334 SCALE_MODE => gSCALE_MODE,
335 PTS => gPTS,
336 HALFPTS => gHALFPTS,
337 inBuf_RWDLY => gInBuf_RWDLY)
338 port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
339
340 LINK : Linker_FFT
341 generic map(Data_sz => 16)
342 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoINT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Link_Write,Link_ReUse,Link_Data);
355 FFT0 : FFT
356 generic map(Data_sz => 16,NbData => 256)
357 port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
343 358
344 359 ----- LINK MEMORY -------------------------------------------------------
345 360
346 361 -- MemOut : APB_FIFO
347 362 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0)
348 363 -- port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9));
349 364
350 365 MemInt : lppFIFOxN
351 366 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1')
352 port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open);
367 port map(rstn,clkm,clkm,FFT_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
353 368
354 369 -- MemIn : APB_FIFO
355 370 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
356 371 -- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8));
357 372
358 373 ----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
359 374
360 TopSM : TopSpecMatrix
361 generic map (Input_SZ => 16)
362 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoINT_Full,FifoINT_Data,TopSM_Start,TopSM_Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
363
364 SM : SpectralMatrix
375 SM0 : MatriceSpectrale
365 376 generic map (Input_SZ => 16, Result_SZ => 32)
366 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
377 port map(clkm,rstn,FifoINT_Full,FifoOUT_Full,FifoINT_Data,Dma_acq,SM_FlagError,SM_Pong,SM_Write,SM_Read,SM_Data);
367 378
368 379 Dma_acq <= '1';
369 380
370 DISP : Dispatch
371 generic map(Data_SZ => 32)
372 port map(clkm,rstn,Dma_acq,Matrix_Result,Matrix_Write,FifoOUT_Full,Disp_Data,Disp_Write,Disp_Pong,Disp_FlagError);
373
374 381 MemOut : APB_FIFO
375 382 generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
376 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Disp_Write,open,FifoOUT_Full,open,Disp_Data,open,open,apbi,apbo(9));
383 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
377 384
378 385 ----- FIFO -------------------------------------------------------------
379 386
380 387 Memtest : APB_FIFO
381 388 generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
382 389 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5));
383 390
384 391 --***************************************TEST DEMI-FIFO********************************************************************************
385 392 -- MemIn : APB_FIFO
386 393 -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
387 394 -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8));
388 395 --
389 396 -- Pont : Bridge
390 397 -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0));
391 398 --
392 399 -- MemOut : APB_FIFO
393 400 -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
394 401 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9));
395 402 --*************************************************************************************************************************************
396 403
397 404 --- UART -------------------------------------------------------------
398 405
399 406 COM0 : APB_UART
400 407 generic map (pindex => 4, paddr => 4)
401 408 port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD);
402 409
403 410 --- DELAY ------------------------------------------------------------
404 411
405 412 -- Delay0 : APB_Delay
406 413 -- generic map (pindex => 4, paddr => 4)
407 414 -- port map (clkm,rstn,apbi,apbo(4));
408 415
409 416 --- IIR Filter -------------------------------------------------------
410 417 --Test(0) <= sample_clk_out;
411 418 --
412 419 --
413 420 -- IIR1: APB_IIR_Filter
414 421 -- generic map(
415 422 -- tech => CFG_MEMTECH,
416 423 -- pindex => 8,
417 424 -- paddr => 8,
418 425 -- Sample_SZ => Sample_SZ,
419 426 -- ChanelsCount => ChanelsCount,
420 427 -- Coef_SZ => Coef_SZ,
421 428 -- CoefCntPerCel => CoefCntPerCel,
422 429 -- Cels_count => Cels_count,
423 430 -- virgPos => virgPos
424 431 -- )
425 432 -- port map(
426 433 -- rst => rstn,
427 434 -- clk => clkm,
428 435 -- apbi => apbi,
429 436 -- apbo => apbo(8),
430 437 -- sample_clk_out => sample_clk_out,
431 438 -- GOtest => Test(1),
432 439 -- CoefsInitVal => (others => '1')
433 440 -- );
434 441 ----------------------------------------------------------------------
435 442
436 443 ----------------------------------------------------------------------
437 444 --- Reset and Clock generation -------------------------------------
438 445 ----------------------------------------------------------------------
439 446
440 447 vcc <= (others => '1'); gnd <= (others => '0');
441 448 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
442 449
443 450 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
444 451
445 452
446 453 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
447 454
448 455 clkgen0 : clkgen -- clock generator
449 456 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
450 457 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
451 458 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
452 459
453 460 ramclk <= clkm;
454 461 process(lclk2x)
455 462 begin
456 463 if lclk2x'event and lclk2x = '1' then
457 464 lclk <= not lclk;
458 465 end if;
459 466 end process;
460 467
461 468 ----------------------------------------------------------------------
462 469 --- LEON3 processor / DSU / IRQ ------------------------------------
463 470 ----------------------------------------------------------------------
464 471
465 472 l3 : if CFG_LEON3 = 1 generate
466 473 cpu : for i in 0 to CFG_NCPU-1 generate
467 474 u0 : leon3s -- LEON3 processor
468 475 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
469 476 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
470 477 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
471 478 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
472 479 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
473 480 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
474 481 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
475 482 irqi(i), irqo(i), dbgi(i), dbgo(i));
476 483 end generate;
477 484 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
478 485
479 486 dsugen : if CFG_DSU = 1 generate
480 487 dsu0 : dsu3 -- LEON3 Debug Support Unit
481 488 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
482 489 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
483 490 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
484 491 -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
485 492 dsui.enable <= '1';
486 493 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
487 494 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
488 495 end generate;
489 496 end generate;
490 497
491 498 nodsu : if CFG_DSU = 0 generate
492 499 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
493 500 end generate;
494 501
495 502 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
496 503 irqctrl0 : irqmp -- interrupt controller
497 504 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
498 505 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
499 506 end generate;
500 507 irq3 : if CFG_IRQ3_ENABLE = 0 generate
501 508 x : for i in 0 to CFG_NCPU-1 generate
502 509 irqi(i).irl <= "0000";
503 510 end generate;
504 511 apbo(2) <= apb_none;
505 512 end generate;
506 513
507 514 ----------------------------------------------------------------------
508 515 --- Memory controllers ---------------------------------------------
509 516 ----------------------------------------------------------------------
510 517
511 518 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
512 519 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
513 520
514 521 memi.brdyn <= '1'; memi.bexcn <= '1';
515 522 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
516 523
517 524 bdr : for i in 0 to 3 generate
518 525 data_pad : iopadv generic map (tech => padtech, width => 8)
519 526 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
520 527 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
521 528 end generate;
522 529
523 530
524 531 addr_pad : outpadv generic map (width => 19, tech => padtech)
525 532 port map (address, memo.address(20 downto 2));
526 533
527 534
528 535 SSRAM_0:entity ssram_plugin
529 536 generic map (tech => padtech)
530 537 port map
531 538 (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
532 539
533 540 ----------------------------------------------------------------------
534 541 --- AHB CONTROLLER -------------------------------------------------
535 542 ----------------------------------------------------------------------
536 543
537 544 ahb0 : ahbctrl -- AHB arbiter/multiplexer
538 545 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
539 546 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
540 547 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
541 548 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
542 549
543 550 ----------------------------------------------------------------------
544 551 --- AHB UART -------------------------------------------------------
545 552 ----------------------------------------------------------------------
546 553
547 554 dcomgen : if CFG_AHB_UART = 1 generate
548 555 dcom0: ahbuart -- Debug UART
549 556 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
550 557 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
551 558 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
552 559 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
553 560 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
554 561 end generate;
555 562 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
556 563
557 564 ----------------------------------------------------------------------
558 565 --- APB Bridge -----------------------------------------------------
559 566 ----------------------------------------------------------------------
560 567
561 568 apb0 : apbctrl -- AHB/APB bridge
562 569 generic map (hindex => 1, haddr => CFG_APBADDR)
563 570 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
564 571
565 572 ----------------------------------------------------------------------
566 573 --- GPT Timer ------------------------------------------------------
567 574 ----------------------------------------------------------------------
568 575
569 576 gpt : if CFG_GPT_ENABLE /= 0 generate
570 577 timer0 : gptimer -- timer unit
571 578 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
572 579 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
573 580 nbits => CFG_GPT_TW)
574 581 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
575 582 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
576 583 -- led(4) <= gpto.wdog;
577 584 end generate;
578 585 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
579 586
580 587
581 588 ----------------------------------------------------------------------
582 589 --- APB UART -------------------------------------------------------
583 590 ----------------------------------------------------------------------
584 591
585 592 ua1 : if CFG_UART1_ENABLE /= 0 generate
586 593 uart1 : apbuart -- UART 1
587 594 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
588 595 fifosize => CFG_UART1_FIFO)
589 596 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
590 597 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
591 598 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
592 599 -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
593 600 end generate;
594 601 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
595 602
596 603 ----------------------------------------------------------------------
597 604 --- GPIO -----------------------------------------------------------
598 605 ----------------------------------------------------------------------
599 606
600 607 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
601 608 grgpio0: grgpio
602 609 generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
603 610 port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
604 611
605 612 pio_pads : for i in 0 to 6 generate
606 613 pio_pad : iopad generic map (tech => padtech)
607 614 port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
608 615 end generate;
609 616 end generate;
610 617
611 618
612 619 end Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,65 +1,81
1 -- WatchFlag.vhd
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
2 22 library IEEE;
3 23 use IEEE.std_logic_1164.all;
4 24 use IEEE.numeric_std.all;
5 25
6 26 entity WatchFlag is
7 27 port(
8 28 clk : in std_logic;
9 29 rstn : in std_logic;
10 30
11 FullF0a : in std_logic_vector(4 downto 0);
12 FullF0b : in std_logic_vector(4 downto 0);
13 FullF1 : in std_logic_vector(4 downto 0);
14 FullF2 : in std_logic_vector(4 downto 0);
15
16 31 EmptyF0a : in std_logic_vector(4 downto 0);
17 32 EmptyF0b : in std_logic_vector(4 downto 0);
18 33 EmptyF1 : in std_logic_vector(4 downto 0);
19 34 EmptyF2 : in std_logic_vector(4 downto 0);
20 35
21 36 DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a
22 37 );
23 38 end entity;
24 39
25 40
26 41 architecture ar_WatchFlag of WatchFlag is
27 42
28 43 constant FlagSet : std_logic_vector(4 downto 0) := (others =>'1');
44 constant OneToSet : std_logic_vector(4 downto 0) := "01111";
29 45
30 46 begin
31 47 process(clk,rstn)
32 48 begin
33 49 if(rstn='0')then
34 50 DataCpt <= (others => '0');
35 51
36 52 elsif(clk'event and clk='1')then
37 53
38 if(FullF0a = FlagSet)then
54 if(EmptyF0a = OneToSet)then
39 55 DataCpt(0) <= '1';
40 56 elsif(EmptyF0a = FlagSet)then
41 57 DataCpt(0) <= '0';
42 58 end if;
43 59
44 if(FullF0b = FlagSet)then
60 if(EmptyF0b = OneToSet)then
45 61 DataCpt(1) <= '1';
46 62 elsif(EmptyF0b = FlagSet)then
47 63 DataCpt(1) <= '0';
48 64 end if;
49 65
50 if(FullF1 = FlagSet)then
66 if(EmptyF1 = OneToSet)then
51 67 DataCpt(2) <= '1';
52 68 elsif(EmptyF1 = FlagSet)then
53 69 DataCpt(2) <= '0';
54 70 end if;
55 71
56 if(FullF2 = FlagSet)then
72 if(EmptyF2 = OneToSet)then
57 73 DataCpt(3) <= '1';
58 74 elsif(EmptyF2 = FlagSet)then
59 75 DataCpt(3) <= '0';
60 76 end if;
61 77
62 78 end if;
63 79 end process;
64 80
65 81 end architecture; No newline at end of file
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@@ -1,81 +1,103
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29
30 30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31 31
32 32 package lpp_demux is
33 33
34
35 component Demultiplex is
36 generic(
37 Data_sz : integer range 1 to 32 := 16);
38 port(
39 clk : in std_logic;
40 rstn : in std_logic;
41
42 Read : in std_logic_vector(4 downto 0);
43
44 EmptyF0a : in std_logic_vector(4 downto 0);
45 EmptyF0b : in std_logic_vector(4 downto 0);
46 EmptyF1 : in std_logic_vector(4 downto 0);
47 EmptyF2 : in std_logic_vector(4 downto 0);
48
49 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
50 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
51 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
52 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
53
54 Read_DEMUX : out std_logic_vector(19 downto 0);
55 Empty : out std_logic_vector(4 downto 0);
56 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
57 );
58 end component;
59
60
34 61 component DEMUX is
35 62 generic(
36 63 Data_sz : integer range 1 to 32 := 16);
37 64 port(
38 65 clk : in std_logic;
39 66 rstn : in std_logic;
40 67
41 68 Read : in std_logic_vector(4 downto 0);
42 69 DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a
43 70
44 71 EmptyF0a : in std_logic_vector(4 downto 0);
45 72 EmptyF0b : in std_logic_vector(4 downto 0);
46 73 EmptyF1 : in std_logic_vector(4 downto 0);
47 74 EmptyF2 : in std_logic_vector(4 downto 0);
48 75
49 76 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
50 77 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
51 78 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
52 79 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
53 80
54 81 Read_DEMUX : out std_logic_vector(19 downto 0);
55 82 Empty : out std_logic_vector(4 downto 0);
56 83 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
57 84 );
58 85 end component;
59 86
60 87
61 88 component WatchFlag is
62 89 port(
63 90 clk : in std_logic;
64 91 rstn : in std_logic;
65 92
66 FullF0a : in std_logic_vector(4 downto 0);
67 FullF0b : in std_logic_vector(4 downto 0);
68 FullF1 : in std_logic_vector(4 downto 0);
69 FullF2 : in std_logic_vector(4 downto 0);
70
71 93 EmptyF0a : in std_logic_vector(4 downto 0);
72 94 EmptyF0b : in std_logic_vector(4 downto 0);
73 95 EmptyF1 : in std_logic_vector(4 downto 0);
74 96 EmptyF2 : in std_logic_vector(4 downto 0);
75 97
76 98 DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a
77 99 );
78 100 end component;
79 101
80 102
81 103 end; No newline at end of file
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@@ -1,212 +1,217
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
25 27
26 28 --! Driver de l'ALU
27 29
28 30 entity ALU_Driver is
29 31 generic(
30 32 Input_SZ_1 : integer := 16;
31 33 Input_SZ_2 : integer := 16);
32 34 port(
33 35 clk : in std_logic; --! Horloge du composant
34 36 reset : in std_logic; --! Reset general du composant
35 37 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donn�e d'entr�e
36 38 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donn�e d'entr�e
37 39 Take : in std_logic; --! Flag, op�rande r�cup�r�
38 40 Received : in std_logic; --! Flag, R�sultat bien ressu
39 41 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
40 42 Valid : out std_logic; --! Flag, R�sultat disponible
41 43 Read : out std_logic; --! Flag, op�rande disponible
42 CTRL : out std_logic_vector(4 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
44 CTRL : out std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
45 COMP : out std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes
43 46 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
44 47 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande
45 48 );
46 49 end ALU_Driver;
47 50
48 51 --! @details Les op�randes sont issue des donn�es d'entr�es et associ� aux bonnes valeurs sur CTRL, les diff�rentes op�rations sont effectu�es
49 52
50 53 architecture ar_ALU_Driver of ALU_Driver is
51 54
52 55 signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0);
53 56 signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0);
54 57 signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0);
55 58 signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0);
56 59
57 60 signal go_st : std_logic;
58 61 signal Take_reg : std_logic;
59 62 signal Received_reg : std_logic;
60 63
61 type etat is (eX,e0,e1,e2,e3,e4,e5,idle,idle2,idle3);
64 type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW);
62 65 signal ect : etat;
63 66 signal st : etat;
64 67
65 68 begin
66 69 process(clk,reset)
67 70 begin
68 71
69 72 if(reset='0')then
70 73 ect <= eX;
71 74 st <= e0;
72 75 go_st <= '0';
73 CTRL <= "10000";
76 CTRL <= ctrl_CLRMAC;
77 COMP <= "00"; -- pas de complement
74 78 Read <= '0';
75 79 Valid <= '0';
76 80 Take_reg <= '0';
77 81 Received_reg <= '0';
78 82
79 83 elsif(clk'event and clk='1')then
80 84 Take_reg <= Take;
81 85 Received_reg <= Received;
82 86
83 87 case ect is
84 88 when eX =>
85 89 go_st <= '0';
86 90 Read <= '1';
87 CTRL <= "10000";
91 CTRL <= ctrl_CLRMAC;
88 92 ect <= e0;
89 93
90 94 when e0 =>
91 95 OP1re <= IN1;
92 96 if(Conjugate='1')then --
93 97 OP2re <= IN1; --
94 98 else --
95 99 OP2re <= IN2; -- modif 23/06/11
96 100 end if; --
97 101 if(Take_reg='0' and Take='1')then
98 102 read <= '0';
99 103 ect <= e1;
100 104 end if;
101 105
102 106 when e1 =>
103 107 OP1 <= OP1re;
104 108 OP2 <= OP2re;
105 CTRL <= "00001";
109 CTRL <= ctrl_MAC;
106 110 Read <= '1';
107 ect <= idle;
111 ect <= eY;
108 112
109 when idle =>
113 when eY =>
110 114 OP1im <= IN1;
111 115 if(Conjugate='1')then --
112 116 OP2im <= IN1; --
113 117 else --
114 118 OP2im <= IN2; -- modif 23/06/11
115 119 end if; --
116 CTRL <= "00000";
120 CTRL <= ctrl_IDLE;
117 121 if(Take_reg='1' and Take='0')then
118 122 Read <= '0';
119 123 ect <= e2;
120 124 end if;
121 125
122 126 when e2 =>
123 127 OP1 <= OP1im;
124 128 OP2 <= OP2im;
125 CTRL <= "00001";
126 ect <= idle2;
129 CTRL <= ctrl_MAC;
130 ect <= eZ;
127 131
128 when idle2 =>
129 CTRL <= "00000";
132 when eZ =>
133 CTRL <= ctrl_IDLE;
130 134 go_st <= '1';
131 135 if(Received_reg='0' and Received='1')then
132 136 if(Conjugate='1')then
133 137 ect <= eX;
134 138 else
135 139 ect <= e3;
136 140 end if;
137 141 end if;
138 142
139 143 when e3 =>
140 CTRL <= "10000";
144 CTRL <= ctrl_CLRMAC;
141 145 go_st <= '0';
142 146 ect <= e4;
143 147
144 148 when e4 =>
145 149 OP1 <= OP1im;
146 150 OP2 <= OP2re;
147 CTRL <= "00001";
151 CTRL <= ctrl_MAC;
148 152 ect <= e5;
149 153
150 154 when e5 =>
151 155 OP1 <= OP1re;
152 156 OP2 <= OP2im;
153 CTRL <= "01001";
154 ect <= idle3;
157 COMP <= "10";
158 ect <= eW;
155 159
156 when idle3 =>
157 CTRL <= "00000";
160 when eW =>
161 CTRL <= ctrl_IDLE;
162 COMP <= "00";
158 163 go_st <= '1';
159 164 if(Received_reg='1' and Received='0')then
160 165 ect <= eX;
161 166 end if;
162 167 end case;
163 168 ---------------------------------------------------------------------------------
164 169 case st is
165 170 when e0 =>
166 171 if(go_st='1')then
167 172 st <= e1;
168 173 end if;
169 174
170 175 when e1 =>
171 176 Valid <= '1';
172 177 st <= e2;
173 178
174 179 when e2 =>
175 180 if(Received_reg='0' and Received='1')then
176 181 Valid <= '0';
177 182 if(Conjugate='1')then
178 st <= idle2;
183 st <= eY;
179 184 else
180 st <= idle;
185 st <= eX;
181 186 end if;
182 187 end if;
183 188
184 when idle =>
189 when eX =>
185 190 st <= e3;
186 191
187 192 when e3 =>
188 193 if(go_st='1')then
189 194 st <= e4;
190 195 end if;
191 196
192 197 when e4 =>
193 198 Valid <= '1';
194 199 st <= e5;
195 200
196 201 when e5 =>
197 202 if(Received_reg='1' and Received='0')then
198 203 Valid <= '0';
199 st <= idle2;
204 st <= eY;
200 205 end if;
201 206
202 when idle2 =>
207 when eY =>
203 208 st <= e0;
204 209
205 210 when others =>
206 211 null;
207 212 end case;
208 213
209 214 end if;
210 215 end process;
211 216
212 217 end ar_ALU_Driver; No newline at end of file
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@@ -1,66 +1,68
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 library lpp;
25 26 use lpp.lpp_matrix.all;
27 use lpp.general_purpose.all;
26 28
27 29 --! Programme de calcule de Matrice Spectral, compos� d'une ALU et de son Driver
28 30
29 31 entity Matrix is
30 32 generic(
31 33 Input_SZ : integer := 16);
32 34 port(
33 35 clk : in std_logic; --! Horloge du composant
34 36 raz : in std_logic; --! Reset general du composant
35 37 IN1 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e
36 38 IN2 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e
37 39 Take : in std_logic; --! Flag, op�rande r�cup�r�
38 40 Received : in std_logic; --! Flag, R�sultat bien ressu
39 41 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
40 42 Valid : out std_logic; --! Flag, R�sultat disponible
41 43 Read : out std_logic; --! Flag, op�rande disponible
42 44 Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! R�sultat du calcul
43 45 );
44 46 end Matrix;
45 47
46 48
47 49 architecture ar_Matrix of Matrix is
48 50
49 signal CTRL : std_logic_vector(4 downto 0);
51 signal CTRL : std_logic_vector(2 downto 0);
52 signal COMP : std_logic_vector(1 downto 0);
50 53 signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
51 54 signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
52 55
53 56 begin
54 57
55 58 DRIVE : ALU_Driver
56 59 generic map(Input_SZ,Input_SZ)
57 port map(clk,raz,IN1,IN2,Take,Received,Conjugate,Valid,Read,CTRL,OP1,OP2);
60 port map(clk,raz,IN1,IN2,Take,Received,Conjugate,Valid,Read,CTRL,COMP,OP1,OP2);
58 61
59 62
60 ALU : ALU_v2
63 ALU0 : ALU
61 64 generic map(1,0,Input_SZ,Input_SZ)
62 port map(clk,raz,CTRL,OP1,OP2,Result);
65 port map(clk,raz,CTRL,COMP,OP1,OP2,Result);
63 66
64 67
65 68 end ar_Matrix;
66
Show file before | Show file after | Hide comments
@@ -1,278 +1,253
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29
30 30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31 31
32 32 package lpp_matrix is
33 33
34 34 component APB_Matrix is
35 35 generic (
36 36 pindex : integer := 0;
37 37 paddr : integer := 0;
38 38 pmask : integer := 16#fff#;
39 39 pirq : integer := 0;
40 40 abits : integer := 8;
41 41 Input_SZ : integer := 16;
42 42 Result_SZ : integer := 32);
43 43 port (
44 44 clk : in std_logic;
45 45 rst : in std_logic;
46 46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 48 Full : in std_logic_vector(1 downto 0);
49 49 Empty : in std_logic_vector(1 downto 0);
50 50 ReadFIFO : out std_logic_vector(1 downto 0);
51 51 FullFIFO : in std_logic;
52 52 WriteFIFO : out std_logic;
53 53 Result : out std_logic_vector(Result_SZ-1 downto 0);
54 54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
55 55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
56 56 );
57 57 end component;
58 58
59 component MatriceSpectrale is
60 generic(
61 Input_SZ : integer := 16;
62 Result_SZ : integer := 32);
63 port(
64 clkm : in std_logic;
65 rstn : in std_logic;
66
67 FifoIN_Full : in std_logic_vector(4 downto 0);
68 FifoOUT_Full : in std_logic_vector(1 downto 0);
69 Data_IN : in std_logic_vector(79 downto 0);
70 ACQ : in std_logic;
71 FlagError : out std_logic;
72 Pong : out std_logic;
73 Write : out std_logic_vector(1 downto 0);
74 Read : out std_logic_vector(4 downto 0);
75 Data_OUT : out std_logic_vector(63 downto 0)
76 );
77 end component;
78
79
59 80 component TopSpecMatrix is
60 81 generic(
61 82 Input_SZ : integer := 16);
62 83 port(
63 84 clk : in std_logic;
64 85 rstn : in std_logic;
65 86 Write : in std_logic;
66 87 ReadIn : in std_logic_vector(1 downto 0);
67 88 Full : in std_logic_vector(4 downto 0);
68 89 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
69 90 Start : out std_logic;
70 91 ReadOut : out std_logic_vector(4 downto 0);
71 92 Statu : out std_logic_vector(3 downto 0);
72 93 DATA1 : out std_logic_vector(Input_SZ-1 downto 0);
73 94 DATA2 : out std_logic_vector(Input_SZ-1 downto 0)
74 95 );
75 96 end component;
76 97
77 98
78 99 component Top_MatrixSpec is
79 100 generic(
80 101 Input_SZ : integer := 16;
81 102 Result_SZ : integer := 32);
82 103 port(
83 104 clk : in std_logic;
84 105 reset : in std_logic;
85 106 Statu : in std_logic_vector(3 downto 0);
86 107 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
87 108 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
88 109 Full : in std_logic_vector(1 downto 0);
89 110 Empty : in std_logic_vector(1 downto 0);
90 111 ReadFIFO : out std_logic_vector(1 downto 0);
91 112 FullFIFO : in std_logic;
92 113 WriteFIFO : out std_logic;
93 114 Result : out std_logic_vector(Result_SZ-1 downto 0)
94 115 );
95 116 end component;
96 117
97 118 component SpectralMatrix is
98 119 generic(
99 120 Input_SZ : integer := 16;
100 121 Result_SZ : integer := 32);
101 122 port(
102 123 clk : in std_logic;
103 124 reset : in std_logic;
104 125 Start : in std_logic;
105 126 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
106 127 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
107 128 Statu : in std_logic_vector(3 downto 0);
108 129 -- FullFIFO : in std_logic;
109 130 ReadFIFO : out std_logic_vector(1 downto 0);
110 131 WriteFIFO : out std_logic;
111 132 Result : out std_logic_vector(Result_SZ-1 downto 0)
112 133 );
113 134 end component;
114 135
115 136
116 137 component Matrix is
117 138 generic(
118 139 Input_SZ : integer := 16);
119 140 port(
120 141 clk : in std_logic;
121 142 raz : in std_logic;
122 143 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
123 144 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
124 145 Take : in std_logic;
125 146 Received : in std_logic;
126 147 Conjugate : in std_logic;
127 148 Valid : out std_logic;
128 149 Read : out std_logic;
129 150 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
130 151 );
131 152 end component;
132 153
133 154 component GetResult is
134 155 generic(
135 156 Result_SZ : integer := 32);
136 157 port(
137 158 clk : in std_logic;
138 159 raz : in std_logic;
139 160 Valid : in std_logic;
140 161 Conjugate : in std_logic;
141 162 Res : in std_logic_vector(Result_SZ-1 downto 0);
142 163 -- Full : in std_logic;
143 164 WriteFIFO : out std_logic;
144 165 Received : out std_logic;
145 166 Result : out std_logic_vector(Result_SZ-1 downto 0)
146 167 );
147 168 end component;
148 169
149 170
150 171 component TopMatrix_PDR is
151 172 generic(
152 173 Input_SZ : integer := 16;
153 174 Result_SZ : integer := 32);
154 175 port(
155 176 clk : in std_logic;
156 177 reset : in std_logic;
157 178 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
158 179 FULLin : in std_logic_vector(4 downto 0);
159 180 READin : in std_logic_vector(1 downto 0);
160 181 WRITEin : in std_logic;
161 182 FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
162 183 FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
163 184 Start : out std_logic;
164 185 Read : out std_logic_vector(4 downto 0);
165 186 Statu : out std_logic_vector(3 downto 0)
166 187 );
167 188 end component;
168 189
169 190
170 191 component Dispatch is
171 192 generic(
172 193 Data_SZ : integer := 32);
173 194 port(
174 195 clk : in std_logic;
175 196 reset : in std_logic;
176 197 Acq : in std_logic;
177 198 Data : in std_logic_vector(Data_SZ-1 downto 0);
178 199 Write : in std_logic;
179 200 Full : in std_logic_vector(1 downto 0);
180 201 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
181 202 FifoWrite : out std_logic_vector(1 downto 0);
182 203 Pong : out std_logic;
183 204 Error : out std_logic
184 205 );
185 206 end component;
186 207
187 208
188 209 component DriveInputs is
189 210 port(
190 211 clk : in std_logic;
191 212 raz : in std_logic;
192 213 Read : in std_logic;
193 214 Conjugate : in std_logic;
194 215 Take : out std_logic;
195 216 ReadFIFO : out std_logic_vector(1 downto 0)
196 217 );
197 218 end component;
198 219
199 220 component Starter is
200 221 port(
201 222 clk : in std_logic;
202 223 raz : in std_logic;
203 224 Full : in std_logic_vector(1 downto 0);
204 225 Empty : in std_logic_vector(1 downto 0);
205 226 Statu : in std_logic_vector(3 downto 0);
206 227 Write : in std_logic;
207 228 Start : out std_logic
208 229 );
209 230 end component;
210 231
211 232 component ALU_Driver is
212 233 generic(
213 234 Input_SZ_1 : integer := 16;
214 235 Input_SZ_2 : integer := 16);
215 236 port(
216 237 clk : in std_logic;
217 238 reset : in std_logic;
218 239 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
219 240 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
220 241 Take : in std_logic;
221 242 Received : in std_logic;
222 243 Conjugate : in std_logic;
223 244 Valid : out std_logic;
224 245 Read : out std_logic;
225 CTRL : out std_logic_vector(4 downto 0);
246 CTRL : out std_logic_vector(2 downto 0);
247 COMP : out std_logic_vector(1 downto 0);
226 248 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
227 249 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
228 250 );
229 251 end component;
230 252
231
232 component ALU_v2 is
233 generic(
234 Arith_en : integer := 1;
235 Logic_en : integer := 1;
236 Input_SZ_1 : integer := 16;
237 Input_SZ_2 : integer := 9);
238 port(
239 clk : in std_logic;
240 reset : in std_logic;
241 ctrl : in std_logic_vector(4 downto 0);
242 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
243 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
244 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
245 );
246 end component;
247
248
249 component MAC_v2 is
250 generic(
251 Input_SZ_A : integer := 8;
252 Input_SZ_B : integer := 8);
253 port(
254 clk : in std_logic;
255 reset : in std_logic;
256 clr_MAC : in std_logic;
257 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
258 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
259 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
260 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
261 );
262 end component;
263
264
265 component TwoComplementer is
266 generic(
267 Input_SZ : integer := 16);
268 port(
269 clk : in std_logic;
270 reset : in std_logic;
271 clr : in std_logic;
272 TwoComp : in std_logic;
273 OP : in std_logic_vector(Input_SZ-1 downto 0);
274 RES : out std_logic_vector(Input_SZ-1 downto 0)
275 );
276 end component;
277
278 253 end; No newline at end of file
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@@ -1,354 +1,354
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 LIBRARY lpp;
4 4 USE lpp.lpp_ad_conv.ALL;
5 5 USE lpp.iir_filter.ALL;
6 6 USE lpp.FILTERcfg.ALL;
7 7 USE lpp.lpp_memory.ALL;
8 8 USE lpp.lpp_top_lfr_pkg.ALL;
9 9 LIBRARY techmap;
10 10 USE techmap.gencomp.ALL;
11 11
12 12 ENTITY lpp_top_acq IS
13 13 GENERIC(
14 14 tech : INTEGER := 0
15 15 );
16 16 PORT (
17 17 -- ADS7886
18 18 cnv_run : IN STD_LOGIC;
19 19 cnv : OUT STD_LOGIC;
20 20 sck : OUT STD_LOGIC;
21 21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
22 22 --
23 23 cnv_clk : IN STD_LOGIC; -- clk 49 MHz
24 24 cnv_rstn : IN STD_LOGIC;
25 25 --
26 26 clk : IN STD_LOGIC;
27 27 rstn : IN STD_LOGIC;
28 28 --
29 29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 30 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
31 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 32 --
33 33 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
34 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 35 --
36 36 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
37 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38 38 --
39 39 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
40 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0)
40 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
41 41 );
42 42 END lpp_top_acq;
43 43
44 44 ARCHITECTURE tb OF lpp_top_acq IS
45 45
46 46 COMPONENT Downsampling
47 47 GENERIC (
48 48 ChanelCount : INTEGER;
49 49 SampleSize : INTEGER;
50 50 DivideParam : INTEGER);
51 51 PORT (
52 52 clk : IN STD_LOGIC;
53 53 rstn : IN STD_LOGIC;
54 54 sample_in_val : IN STD_LOGIC;
55 55 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
56 56 sample_out_val : OUT STD_LOGIC;
57 57 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
58 58 END COMPONENT;
59 59
60 60 -----------------------------------------------------------------------------
61 61 CONSTANT ChanelCount : INTEGER := 8;
62 62 CONSTANT ncycle_cnv_high : INTEGER := 79;
63 63 CONSTANT ncycle_cnv : INTEGER := 500;
64 64
65 65 -----------------------------------------------------------------------------
66 66 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
67 67 SIGNAL sample_val : STD_LOGIC;
68 68 SIGNAL sample_val_delay : STD_LOGIC;
69 69 -----------------------------------------------------------------------------
70 70 CONSTANT Coef_SZ : INTEGER := 9;
71 71 CONSTANT CoefCntPerCel : INTEGER := 6;
72 72 CONSTANT CoefPerCel : INTEGER := 5;
73 73 CONSTANT Cels_count : INTEGER := 5;
74 74
75 75 -- SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
76 76 SIGNAL coefs_JC : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
77 77 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
78 78 -- SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 79 --
80 80 SIGNAL sample_filter_JC_out_val : STD_LOGIC;
81 81 SIGNAL sample_filter_JC_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 82 --
83 83 SIGNAL sample_filter_JC_out_r_val : STD_LOGIC;
84 84 SIGNAL sample_filter_JC_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
85 85 -----------------------------------------------------------------------------
86 86 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
87 87 SIGNAL sample_downsampling_out_val : STD_LOGIC;
88 88 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
89 89 --
90 90 SIGNAL sample_f0_val : STD_LOGIC;
91 91 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
92 92 --
93 93 SIGNAL sample_f0_0_val : STD_LOGIC;
94 94 SIGNAL sample_f0_1_val : STD_LOGIC;
95 95 SIGNAL counter_f0 : INTEGER;
96 96 -----------------------------------------------------------------------------
97 97 SIGNAL sample_f1_val : STD_LOGIC;
98 98 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
99 99 --
100 100 SIGNAL sample_f2_val : STD_LOGIC;
101 101 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
102 102 --
103 103 SIGNAL sample_f3_val : STD_LOGIC;
104 104 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
105 105
106 106 BEGIN
107 107
108 108 -- component instantiation
109 109 -----------------------------------------------------------------------------
110 110 DIGITAL_acquisition : ADS7886_drvr
111 111 GENERIC MAP (
112 112 ChanelCount => ChanelCount,
113 113 ncycle_cnv_high => ncycle_cnv_high,
114 114 ncycle_cnv => ncycle_cnv)
115 115 PORT MAP (
116 116 cnv_clk => cnv_clk, --
117 117 cnv_rstn => cnv_rstn, --
118 118 cnv_run => cnv_run, --
119 119 cnv => cnv, --
120 120 clk => clk, --
121 121 rstn => rstn, --
122 122 sck => sck, --
123 123 sdo => sdo(ChanelCount-1 DOWNTO 0), --
124 124 sample => sample,
125 125 sample_val => sample_val);
126 126
127 127 -----------------------------------------------------------------------------
128 128
129 129 PROCESS (clk, rstn)
130 130 BEGIN -- PROCESS
131 131 IF rstn = '0' THEN -- asynchronous reset (active low)
132 132 sample_val_delay <= '0';
133 133 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
134 134 sample_val_delay <= sample_val;
135 135 END IF;
136 136 END PROCESS;
137 137
138 138 -----------------------------------------------------------------------------
139 139 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
140 140 SampleLoop : FOR j IN 0 TO 15 GENERATE
141 141 sample_filter_in(i, j) <= sample(i)(j);
142 142 END GENERATE;
143 143
144 144 sample_filter_in(i, 16) <= sample(i)(15);
145 145 sample_filter_in(i, 17) <= sample(i)(15);
146 146 END GENERATE;
147 147
148 148 -- coefs <= CoefsInitValCst;
149 149 coefs_JC <= CoefsInitValCst_JC;
150 150
151 151 --FILTER : IIR_CEL_CTRLR
152 152 -- GENERIC MAP (
153 153 -- tech => 0,
154 154 -- Sample_SZ => 18,
155 155 -- ChanelsCount => ChanelCount,
156 156 -- Coef_SZ => Coef_SZ,
157 157 -- CoefCntPerCel => CoefCntPerCel,
158 158 -- Cels_count => Cels_count,
159 159 -- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
160 160 -- PORT MAP (
161 161 -- reset => rstn,
162 162 -- clk => clk,
163 163 -- sample_clk => sample_val_delay,
164 164 -- sample_in => sample_filter_in,
165 165 -- sample_out => sample_filter_out,
166 166 -- virg_pos => 7,
167 167 -- GOtest => OPEN,
168 168 -- coefs => coefs);
169 169
170 170 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
171 171 GENERIC MAP (
172 172 tech => 0,
173 Mem_use => use_CEL,
173 Mem_use => use_RAM,
174 174 Sample_SZ => 18,
175 175 Coef_SZ => Coef_SZ,
176 176 Coef_Nb => 25, -- TODO
177 177 Coef_sel_SZ => 5, -- TODO
178 178 Cels_count => Cels_count,
179 179 ChanelsCount => ChanelCount)
180 180 PORT MAP (
181 181 rstn => rstn,
182 182 clk => clk,
183 183 virg_pos => 7,
184 184 coefs => coefs_JC,
185 185 sample_in_val => sample_val_delay,
186 186 sample_in => sample_filter_in,
187 187 sample_out_val => sample_filter_JC_out_val,
188 188 sample_out => sample_filter_JC_out);
189 189
190 190 -----------------------------------------------------------------------------
191 191 PROCESS (clk, rstn)
192 192 BEGIN -- PROCESS
193 193 IF rstn = '0' THEN -- asynchronous reset (active low)
194 194 sample_filter_JC_out_r_val <= '0';
195 195 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
196 196 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
197 197 sample_filter_JC_out_r(I, J) <= '0';
198 198 END LOOP rst_all_bits;
199 199 END LOOP rst_all_chanel;
200 200 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
201 201 sample_filter_JC_out_r_val <= sample_filter_JC_out_val;
202 202 IF sample_filter_JC_out_val = '1' THEN
203 203 sample_filter_JC_out_r <= sample_filter_JC_out;
204 204 END IF;
205 205 END IF;
206 206 END PROCESS;
207 207
208 208 -----------------------------------------------------------------------------
209 209 -- F0 -- @24.576 kHz
210 210 -----------------------------------------------------------------------------
211 211 Downsampling_f0 : Downsampling
212 212 GENERIC MAP (
213 213 ChanelCount => ChanelCount,
214 214 SampleSize => 18,
215 215 DivideParam => 4)
216 216 PORT MAP (
217 217 clk => clk,
218 218 rstn => rstn,
219 219 sample_in_val => sample_filter_JC_out_val ,
220 220 sample_in => sample_filter_JC_out,
221 221 sample_out_val => sample_f0_val,
222 222 sample_out => sample_f0);
223 223
224 all_bit_sample_f0 : FOR I IN 17 DOWNTO 0 GENERATE
224 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
225 225 sample_f0_wdata(I) <= sample_f0(0, I);
226 sample_f0_wdata(18*1+I) <= sample_f0(1, I);
227 sample_f0_wdata(18*2+I) <= sample_f0(2, I);
228 sample_f0_wdata(18*3+I) <= sample_f0(6, I);
229 sample_f0_wdata(18*4+I) <= sample_f0(7, I);
226 sample_f0_wdata(16*1+I) <= sample_f0(1, I);
227 sample_f0_wdata(16*2+I) <= sample_f0(2, I);
228 sample_f0_wdata(16*3+I) <= sample_f0(6, I);
229 sample_f0_wdata(16*4+I) <= sample_f0(7, I);
230 230 END GENERATE all_bit_sample_f0;
231 231
232 232 PROCESS (clk, rstn)
233 233 BEGIN -- PROCESS
234 234 IF rstn = '0' THEN -- asynchronous reset (active low)
235 235 counter_f0 <= 0;
236 236 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
237 237 IF sample_f0_val = '1' THEN
238 238 IF counter_f0 = 511 THEN
239 239 counter_f0 <= 0;
240 240 ELSE
241 241 counter_f0 <= counter_f0 + 1;
242 242 END IF;
243 243 END IF;
244 244 END IF;
245 245 END PROCESS;
246 246
247 247 sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0';
248 248 sample_f0_0_wen <= NOT(sample_f0_0_val) &
249 249 NOT(sample_f0_0_val) &
250 250 NOT(sample_f0_0_val) &
251 251 NOT(sample_f0_0_val) &
252 252 NOT(sample_f0_0_val);
253 253
254 254 sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0';
255 255 sample_f0_1_wen <= NOT(sample_f0_1_val) &
256 256 NOT(sample_f0_1_val) &
257 257 NOT(sample_f0_1_val) &
258 258 NOT(sample_f0_1_val) &
259 259 NOT(sample_f0_1_val);
260 260
261 261
262 262 -----------------------------------------------------------------------------
263 263 -- F1 -- @4096 Hz
264 264 -----------------------------------------------------------------------------
265 265 Downsampling_f1 : Downsampling
266 266 GENERIC MAP (
267 267 ChanelCount => ChanelCount,
268 268 SampleSize => 18,
269 269 DivideParam => 6)
270 270 PORT MAP (
271 271 clk => clk,
272 272 rstn => rstn,
273 273 sample_in_val => sample_f0_val ,
274 274 sample_in => sample_f0,
275 275 sample_out_val => sample_f1_val,
276 276 sample_out => sample_f1);
277 277
278 278 sample_f1_wen <= NOT(sample_f1_val) &
279 279 NOT(sample_f1_val) &
280 280 NOT(sample_f1_val) &
281 281 NOT(sample_f1_val) &
282 282 NOT(sample_f1_val);
283 283
284 all_bit_sample_f1 : FOR I IN 17 DOWNTO 0 GENERATE
284 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
285 285 sample_f1_wdata(I) <= sample_f1(0, I);
286 sample_f1_wdata(18*1+I) <= sample_f1(1, I);
287 sample_f1_wdata(18*2+I) <= sample_f1(2, I);
288 sample_f1_wdata(18*3+I) <= sample_f1(6, I);
289 sample_f1_wdata(18*4+I) <= sample_f1(7, I);
286 sample_f1_wdata(16*1+I) <= sample_f1(1, I);
287 sample_f1_wdata(16*2+I) <= sample_f1(2, I);
288 sample_f1_wdata(16*3+I) <= sample_f1(6, I);
289 sample_f1_wdata(16*4+I) <= sample_f1(7, I);
290 290 END GENERATE all_bit_sample_f1;
291 291
292 292 -----------------------------------------------------------------------------
293 293 -- F2 -- @16 Hz
294 294 -----------------------------------------------------------------------------
295 295 Downsampling_f2 : Downsampling
296 296 GENERIC MAP (
297 297 ChanelCount => ChanelCount,
298 298 SampleSize => 18,
299 299 DivideParam => 256)
300 300 PORT MAP (
301 301 clk => clk,
302 302 rstn => rstn,
303 303 sample_in_val => sample_f1_val ,
304 304 sample_in => sample_f1,
305 305 sample_out_val => sample_f2_val,
306 306 sample_out => sample_f2);
307 307
308 308 sample_f2_wen <= NOT(sample_f2_val) &
309 309 NOT(sample_f2_val) &
310 310 NOT(sample_f2_val) &
311 311 NOT(sample_f2_val) &
312 312 NOT(sample_f2_val);
313 313
314 all_bit_sample_f2 : FOR I IN 17 DOWNTO 0 GENERATE
314 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
315 315 sample_f2_wdata(I) <= sample_f2(0, I);
316 sample_f2_wdata(18*1+I) <= sample_f2(1, I);
317 sample_f2_wdata(18*2+I) <= sample_f2(2, I);
318 sample_f2_wdata(18*3+I) <= sample_f2(6, I);
319 sample_f2_wdata(18*4+I) <= sample_f2(7, I);
316 sample_f2_wdata(16*1+I) <= sample_f2(1, I);
317 sample_f2_wdata(16*2+I) <= sample_f2(2, I);
318 sample_f2_wdata(16*3+I) <= sample_f2(6, I);
319 sample_f2_wdata(16*4+I) <= sample_f2(7, I);
320 320 END GENERATE all_bit_sample_f2;
321 321
322 322 -----------------------------------------------------------------------------
323 323 -- F3 -- @256 Hz
324 324 -----------------------------------------------------------------------------
325 325 Downsampling_f3 : Downsampling
326 326 GENERIC MAP (
327 327 ChanelCount => ChanelCount,
328 328 SampleSize => 18,
329 329 DivideParam => 96)
330 330 PORT MAP (
331 331 clk => clk,
332 332 rstn => rstn,
333 333 sample_in_val => sample_f0_val ,
334 334 sample_in => sample_f0,
335 335 sample_out_val => sample_f3_val,
336 336 sample_out => sample_f3);
337 337
338 338 sample_f3_wen <= (NOT sample_f3_val) &
339 339 (NOT sample_f3_val) &
340 340 (NOT sample_f3_val) &
341 341 (NOT sample_f3_val) &
342 342 (NOT sample_f3_val);
343 343
344 all_bit_sample_f3 : FOR I IN 17 DOWNTO 0 GENERATE
344 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
345 345 sample_f3_wdata(I) <= sample_f3(0, I);
346 sample_f3_wdata(18*1+I) <= sample_f3(1, I);
347 sample_f3_wdata(18*2+I) <= sample_f3(2, I);
348 sample_f3_wdata(18*3+I) <= sample_f3(6, I);
349 sample_f3_wdata(18*4+I) <= sample_f3(7, I);
346 sample_f3_wdata(16*1+I) <= sample_f3(1, I);
347 sample_f3_wdata(16*2+I) <= sample_f3(2, I);
348 sample_f3_wdata(16*3+I) <= sample_f3(6, I);
349 sample_f3_wdata(16*4+I) <= sample_f3(7, I);
350 350 END GENERATE all_bit_sample_f3;
351 351
352 352
353 353
354 354 END tb;
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@@ -1,36 +1,36
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 LIBRARY lpp;
4 4 USE lpp.lpp_ad_conv.ALL;
5 5 USE lpp.iir_filter.ALL;
6 6 USE lpp.FILTERcfg.ALL;
7 7 USE lpp.lpp_memory.ALL;
8 8 LIBRARY techmap;
9 9 USE techmap.gencomp.ALL;
10 10
11 11 PACKAGE lpp_top_lfr_pkg IS
12 12
13 13 COMPONENT lpp_top_acq
14 14 GENERIC (
15 15 tech : integer);
16 16 PORT (
17 17 cnv_run : IN STD_LOGIC;
18 18 cnv : OUT STD_LOGIC;
19 19 sck : OUT STD_LOGIC;
20 20 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
21 21 cnv_clk : IN STD_LOGIC;
22 22 cnv_rstn : IN STD_LOGIC;
23 23 clk : IN STD_LOGIC;
24 24 rstn : IN STD_LOGIC;
25 sample_f0_0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
26 sample_f0_1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
27 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
28 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
30 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
32 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0));
25 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
26 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
27 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
28 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
34 34 END COMPONENT;
35 35
36 END lpp_top_lfr_pkg;
36 END lpp_top_lfr_pkg; No newline at end of file
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