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1 -- APB_CNA.vhd
2
3 library ieee;
4 use ieee.std_logic_1164.all;
5 library grlib;
6 use grlib.amba.all;
7 use grlib.stdlib.all;
8 use grlib.devices.all;
9 library lpp;
10 use lpp.lpp_amba.all;
11 use lpp.lpp_cna.all;
12
13
14 entity APB_CNA is
15 generic (
16 pindex : integer := 0;
17 paddr : integer := 0;
18 pmask : integer := 16#fff#;
19 pirq : integer := 0;
20 abits : integer := 8);
21 port (
22 clk : in std_logic;
23 rst : in std_logic;
24 apbi : in apb_slv_in_type;
25 apbo : out apb_slv_out_type;
26 SYNC : out std_logic;
27 SCLK : out std_logic;
28 DATA : out std_logic
29 );
30 end APB_CNA;
31
32
33 architecture ar_APB_CNA of APB_CNA is
34
35 constant REVISION : integer := 1;
36
37 constant pconfig : apb_config_type := (
38 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
39 1 => apb_iobar(paddr, pmask));
40
41 signal flag_nw : std_logic;
42 signal bp : std_logic;
43 signal Rz : std_logic;
44 signal flag_sd : std_logic;
45
46 type CNA_ctrlr_Reg is record
47 CNA_Cfg : std_logic_vector(3 downto 0);
48 CNA_Data : std_logic_vector(15 downto 0);
49 end record;
50
51 signal Rec : CNA_ctrlr_Reg;
52 signal Rdata : std_logic_vector(31 downto 0);
53
54 begin
55
56 bp <= Rec.CNA_Cfg(0);
57 flag_nw <= Rec.CNA_Cfg(1);
58 Rec.CNA_Cfg(2) <= flag_sd;
59 Rec.CNA_Cfg(3) <= Rz;
60
61
62 CONVERTER : entity Work.CNA_TabloC
63 port map(clk,rst,flag_nw,bp,Rec.CNA_Data,SYNC,SCLK,Rz,flag_sd,Data);
64
65
66 process(rst,clk)
67 begin
68 if(rst='0')then
69 Rec.CNA_Data <= (others => '0');
70
71 elsif(clk'event and clk='1')then
72
73
74 --APB Write OP
75 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
76 case apbi.paddr(abits-1 downto 2) is
77 when "000000" =>
78 Rec.CNA_Cfg(1 downto 0) <= apbi.pwdata(1 downto 0);
79 when "000001" =>
80 Rec.CNA_Data <= apbi.pwdata(15 downto 0);
81 when others =>
82 null;
83 end case;
84 end if;
85
86 --APB READ OP
87 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
88 case apbi.paddr(abits-1 downto 2) is
89 when "000000" =>
90 Rdata(31 downto 4) <= X"ABCDEF5";
91 Rdata(3 downto 0) <= Rec.CNA_Cfg;
92 when "000001" =>
93 Rdata(31 downto 16) <= X"FD18";
94 Rdata(15 downto 0) <= Rec.CNA_Data;
95 when others =>
96 Rdata <= (others => '0');
97 end case;
98 end if;
99
100 end if;
101 apbo.pconfig <= pconfig;
102 end process;
103
104 apbo.prdata <= Rdata when apbi.penable = '1';
105 end ar_APB_CNA; No newline at end of file
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@@ -0,0 +1,71
1 -- CNA_TabloC.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5 use work.Convertisseur_config.all;
6
7 entity CNA_TabloC is
8 port(
9 clock : in std_logic;
10 rst : in std_logic;
11 flag_nw : in std_logic;
12 bp : in std_logic;
13 Data_C : in std_logic_vector(15 downto 0);
14 SYNC : out std_logic;
15 SCLK : out std_logic;
16 Rz : out std_logic;
17 flag_sd : out std_logic;
18 Data : out std_logic
19 );
20 end CNA_TabloC;
21
22
23 architecture ar_CNA_TabloC of CNA_TabloC is
24
25 component CLKINT
26 port( A : in std_logic := 'U';
27 Y : out std_logic);
28 end component;
29
30 signal clk : std_logic;
31 --signal reset : std_logic;
32
33 signal raz : std_logic;
34 signal sys_clk : std_logic;
35 signal Data_int : std_logic_vector(15 downto 0);
36 signal OKAI_send : std_logic;
37
38 begin
39
40
41 CLKINT_0 : CLKINT
42 port map(A => clock, Y => clk);
43
44 CLKINT_1 : CLKINT
45 port map(A => rst, Y => raz);
46
47
48 SystemCLK : entity work.Clock_Serie
49 generic map (nb_serial)
50 port map (clk,raz,sys_clk);
51
52
53 Signal_sync : entity work.GeneSYNC_flag
54 port map (clk,raz,flag_nw,sys_clk,OKAI_send,SYNC);
55
56
57 Serial : entity work.serialize
58 port map (clk,raz,sys_clk,Data_int,OKAI_send,flag_sd,Data);
59
60
61 --raz <= not reset;
62 Rz <= raz;
63 SCLK <= not sys_clk;
64 --Data_Cvec <= std_logic_vector(to_unsigned(Data_C,12));
65 --Data_TOT <= "0001" & Data_Cvec;
66
67 with bp select
68 Data_int <= X"9555" when '1',
69 Data_C when others;
70
71 end ar_CNA_TabloC; No newline at end of file
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@@ -0,0 +1,24
1 -- Convertisseur_config.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 Package Convertisseur_config is
7
8
9 --===========================================================|
10 --================= Valeurs Sinus 1Khz ======================|
11 --===========================================================|
12 type Tbl is array(natural range <>) of std_logic_vector(11 downto 0);
13 constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF");
14
15 --constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80");
16
17
18 --===========================================================|
19 --============= Fr�quence de s�rialisation ==================|
20 --===========================================================|
21 constant Freq_serial : integer := 1_000_000;
22 constant nb_serial : integer := 40_000_000 / Freq_serial;
23
24 end; No newline at end of file
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@@ -0,0 +1,94
1 -- GeneSYNC_flag.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity GeneSYNC_flag is
7
8 port(
9 clk,raz : in std_logic;
10 flag_nw : in std_logic;
11 Sysclk : in std_logic;
12 OKAI_send : out std_logic;
13 SYNC : out std_logic
14 );
15
16 end GeneSYNC_flag;
17
18
19 architecture ar_GeneSYNC_flag of GeneSYNC_flag is
20
21 signal Sysclk_reg : std_logic;
22 signal flag_nw_reg : std_logic;
23 signal count : integer;
24
25 type etat is (e0,e1,e2,eX);
26 signal ect : etat;
27
28 begin
29 process (clk,raz)
30 begin
31 if(raz='0')then
32 SYNC <= '0';
33 Sysclk_reg <= '0';
34 flag_nw_reg <= '0';
35 count <= 14;
36 OKAI_send <= '0';
37 ect <= e0;
38
39 elsif(clk' event and clk='1')then
40 Sysclk_reg <= Sysclk;
41 flag_nw_reg <= flag_nw;
42
43 case ect is
44 when e0 =>
45 if(flag_nw_reg='0' and flag_nw='1')then
46 ect <= e1;
47 else
48 count <= 14;
49 ect <= e0;
50 end if;
51
52
53 when e1 =>
54 if(Sysclk_reg='1' and Sysclk='0')then
55 if(count=15)then
56 SYNC <= '1';
57 count <= count+1;
58 ect <= e2;
59 elsif(count=16)then
60 count <= 0;
61 OKAI_send <= '1';
62 ect <= eX;
63 else
64 count <= count+1;
65 OKAI_send <= '0';
66 ect <= e1;
67 end if;
68 end if;
69
70
71 when e2 =>
72 if(Sysclk_reg='0' and Sysclk='1')then
73 if(count=16)then
74 SYNC <= '0';
75 ect <= e1;
76 end if;
77 end if;
78
79 when eX =>
80 if(Sysclk_reg='0' and Sysclk='1')then
81 if(count=15)then
82 OKAI_send <= '0';
83 ect <= e0;
84 else
85 count <= count+1;
86 ect <= eX;
87 end if;
88 end if;
89
90 end case;
91 end if;
92
93 end process;
94 end ar_GeneSYNC_flag; No newline at end of file
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@@ -0,0 +1,86
1 -- Serialize.vhd
2 library IEEE;
3 use IEEE.numeric_std.all;
4 use IEEE.std_logic_1164.all;
5
6 entity Serialize is
7
8 port(
9 clk,raz : in std_logic;
10 sclk : in std_logic;
11 vectin : in std_logic_vector(15 downto 0);
12 send : in std_logic;
13 sended : out std_logic;
14 Data : out std_logic);
15
16 end Serialize;
17
18
19 architecture ar_Serialize of Serialize is
20
21 type etat is (attente,serialize);
22 signal ect : etat;
23
24 signal vector_int : std_logic_vector(16 downto 0);
25 signal vectin_reg : std_logic_vector(15 downto 0);
26 signal load : std_logic;
27 signal N : integer range 0 to 16;
28 signal CPT_ended : std_logic:='0';
29
30 begin
31 process(clk,raz)
32 begin
33 if(raz='0')then
34 ect <= attente;
35 vectin_reg <= (others=> '0');
36 load <= '0';
37 sended <= '1';
38
39 elsif(clk'event and clk='1')then
40 vectin_reg <= vectin;
41
42 case ect is
43 when attente =>
44 if (send='1') then
45 sended <= '0';
46 load <= '1';
47 ect <= serialize;
48 else
49 ect <= attente;
50 end if;
51
52 when serialize =>
53 load <= '0';
54 if(CPT_ended='1')then
55 ect <= attente;
56 sended <= '1';
57 end if;
58
59 end case;
60 end if;
61 end process;
62
63 process(sclk,load,raz)
64 begin
65 if (raz='0')then
66 vector_int <= (others=> '0');
67 N <= 16;
68 elsif(load='1')then
69 vector_int <= vectin & '0';
70 N <= 0;
71 elsif(sclk'event and sclk='0')then
72 if (CPT_ended='0') then
73 vector_int <= vector_int(15 downto 0) & '0';
74 N <= N+1;
75 end if;
76 end if;
77 end process;
78
79 CPT_ended <= '1' when N = 16 else '0';
80
81 with ect select
82 Data <= vector_int(16) when serialize,
83 '0' when others;
84
85 end ar_Serialize;
86
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@@ -0,0 +1,41
1 -- clock.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6
7 entity Clock_Serie is
8
9 generic(N :integer := 695);
10
11 port(
12 clk, raz : in std_logic ;
13 clock : out std_logic);
14
15 end Clock_Serie;
16
17
18 architecture ar_Clock_Serie of Clock_Serie is
19
20 signal clockint : std_logic;
21 signal countint : integer range 0 to N/2-1;
22
23 begin
24 process (clk,raz)
25 begin
26 if(raz = '0') then
27 countint <= 0;
28 clockint <= '0';
29 elsif (clk' event and clk='1') then
30 if (countint = N/2-1) then
31 countint <= 0;
32 clockint <= not clockint;
33 else
34 countint <= countint+1;
35 end if;
36 end if;
37 end process;
38
39 clock <= clockint;
40
41 end ar_Clock_Serie; No newline at end of file
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@@ -0,0 +1,77
1 library ieee;
2 use ieee.std_logic_1164.all;
3 library grlib;
4 use grlib.amba.all;
5 -- pragma translate_off
6 use std.textio.all;
7 -- pragma translate_on
8 library lpp;
9 use lpp.lpp_amba.all;
10
11
12 package lpp_cna is
13
14 component APB_CNA is
15 generic (
16 pindex : integer := 0;
17 paddr : integer := 0;
18 pmask : integer := 16#fff#;
19 pirq : integer := 0;
20 abits : integer := 8);
21 port (
22 clk : in std_logic;
23 rst : in std_logic;
24 apbi : in apb_slv_in_type;
25 apbo : out apb_slv_out_type;
26 SYNC : out std_logic;
27 SCLK : out std_logic;
28 DATA : out std_logic
29 );
30 end component;
31
32
33 component CNA_TabloC is
34 port(
35 clock : in std_logic;
36 rst : in std_logic;
37 flag_nw : in std_logic;
38 bp : in std_logic;
39 Data_C : in std_logic_vector(15 downto 0);
40 SYNC : out std_logic;
41 SCLK : out std_logic;
42 Rz : out std_logic;
43 flag_sd : out std_logic;
44 Data : out std_logic
45 );
46 end component;
47
48
49 component Clock_Serie is
50 generic(N :integer := 695);
51 port(
52 clk, raz : in std_logic ;
53 clock : out std_logic);
54 end component;
55
56
57 component GeneSYNC_flag is
58 port(
59 clk,raz : in std_logic;
60 flag_nw : in std_logic;
61 Sysclk : in std_logic;
62 OKAI_send : out std_logic;
63 SYNC : out std_logic);
64 end component;
65
66
67 component Serialize is
68 port(
69 clk,raz : in std_logic;
70 sclk : in std_logic;
71 vectin : in std_logic_vector(15 downto 0);
72 send : in std_logic;
73 sended : out std_logic;
74 Data : out std_logic);
75 end component;
76
77 end;
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@@ -43,5 +43,5 Patched-dist: Patch-GRLIB
43
43
44 doc:
44 doc:
45 doxygen lib/lpp/Doxyfile
45 doxygen lib/lpp/Doxyfile
46 make lib/lpp/doc/latex
46 #make lib/lpp/doc/latex
47 cp lib/lpp/doc/latex/refman.pdf lib/lpp/doc/VHD_lib.pdf
47 #cp lib/lpp/doc/latex/refman.pdf lib/lpp/doc/VHD_lib.pdf
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@@ -1,5 +1,3
1 amba_lcd_16x2_ctrlr.vhd
2 apb_lcd_ctrlr.vhd
3 FRAME_CLK.vhd
1 FRAME_CLK.vhd
4 LCD_16x2_CFG.vhd
2 LCD_16x2_CFG.vhd
5 LCD_16x2_DRVR.vhd
3 LCD_16x2_DRVR.vhd
@@ -7,3 +5,5 LCD_16x2_ENGINE.vhd
7 LCD_2x16_DRIVER.vhd
5 LCD_2x16_DRIVER.vhd
8 LCD_CLK_GENERATOR.vhd
6 LCD_CLK_GENERATOR.vhd
9 Top_LCD.vhd
7 Top_LCD.vhd
8 amba_lcd_16x2_ctrlr.vhd
9 apb_lcd_ctrlr.vhd
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@@ -1,4 +1,6
1 ./amba_lcd_16x2_ctrlr
2 ./dsp/iir_filter
1 ./general_purpose
3 ./general_purpose
2 ./lpp_amba
4 ./lpp_amba
3 ./dsp/iir_filter
5 ./lpp_cna
4 ./amba_lcd_16x2_ctrlr
6 ./lpp_uart
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@@ -1,12 +1,12
1 APB_IIR_CEL.vhd
1 APB_IIR_CEL.vhd
2 FILTER.vhd
3 FILTER_RAM_CTRLR.vhd
2 FILTERcfg.vhd
4 FILTERcfg.vhd
3 FilterCTRLR.vhd
5 FilterCTRLR.vhd
4 FILTER_RAM_CTRLR.vhd
5 FILTER.vhd
6 IIR_CEL_CTRLR.vhd
6 IIR_CEL_CTRLR.vhd
7 IIR_CEL_FILTER.vhd
7 IIR_CEL_FILTER.vhd
8 iir_filter.vhd
8 RAM.vhd
9 RAM_CEL.vhd
9 RAM_CEL.vhd
10 RAM_CTRLR2.vhd
10 RAM_CTRLR2.vhd
11 RAM.vhd
12 Top_Filtre_IIR.vhd
11 Top_Filtre_IIR.vhd
12 iir_filter.vhd
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@@ -1,13 +1,13
1 Adder.vhd
2 ADDRcntr.vhd
1 ADDRcntr.vhd
3 ALU.vhd
2 ALU.vhd
4 general_purpose.vhd
3 Adder.vhd
4 MAC.vhd
5 MAC_CONTROLER.vhd
5 MAC_CONTROLER.vhd
6 MAC_MUX2.vhd
7 MAC_MUX.vhd
6 MAC_MUX.vhd
7 MAC_MUX2.vhd
8 MAC_REG.vhd
8 MAC_REG.vhd
9 MAC.vhd
9 MUX2.vhd
10 Multiplier.vhd
10 Multiplier.vhd
11 MUX2.vhd
12 REG.vhd
11 REG.vhd
13 Shifter.vhd
12 Shifter.vhd
13 general_purpose.vhd
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@@ -62,6 +62,7 type LEDregs is record
62 end record;
62 end record;
63
63
64 signal r : LEDregs;
64 signal r : LEDregs;
65 signal Rdata : std_logic_vector(31 downto 0);
65
66
66
67
67 begin
68 begin
@@ -73,7 +74,6 begin
73 if rst = '0' then
74 if rst = '0' then
74 LED <= "000";
75 LED <= "000";
75 r.DATAin <= (others => '0');
76 r.DATAin <= (others => '0');
76 apbo.prdata <= (others => '0');
77 elsif clk'event and clk = '1' then
77 elsif clk'event and clk = '1' then
78
78
79 LED <= r.DATAin(2 downto 0);
79 LED <= r.DATAin(2 downto 0);
@@ -92,9 +92,9 begin
92 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
92 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
93 case apbi.paddr(abits-1 downto 2) is
93 case apbi.paddr(abits-1 downto 2) is
94 when "000000" =>
94 when "000000" =>
95 apbo.prdata <= r.DATAin;
95 Rdata <= r.DATAin;
96 when others =>
96 when others =>
97 apbo.prdata <= r.DATAout;
97 Rdata <= r.DATAout;
98 end case;
98 end case;
99 end if;
99 end if;
100
100
@@ -102,5 +102,5 begin
102 apbo.pconfig <= pconfig;
102 apbo.pconfig <= pconfig;
103 end process;
103 end process;
104
104
105
105 apbo.prdata <= Rdata when apbi.penable = '1';
106 end ar_APB_MULTI_DIODE; No newline at end of file
106 end ar_APB_MULTI_DIODE;
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@@ -62,6 +62,7 type LEDregs is record
62 end record;
62 end record;
63
63
64 signal r : LEDregs;
64 signal r : LEDregs;
65 signal Rdata : std_logic_vector(31 downto 0);
65
66
66
67
67 begin
68 begin
@@ -73,7 +74,6 begin
73 if rst = '0' then
74 if rst = '0' then
74 LED <= '0';
75 LED <= '0';
75 r.DATAin <= (others => '0');
76 r.DATAin <= (others => '0');
76 apbo.prdata <= (others => '0');
77 elsif clk'event and clk = '1' then
77 elsif clk'event and clk = '1' then
78
78
79 LED <= r.DATAin(0);
79 LED <= r.DATAin(0);
@@ -92,9 +92,9 begin
92 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
92 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
93 case apbi.paddr(abits-1 downto 2) is
93 case apbi.paddr(abits-1 downto 2) is
94 when "000000" =>
94 when "000000" =>
95 apbo.prdata <= r.DATAin;
95 Rdata <= r.DATAin;
96 when others =>
96 when others =>
97 apbo.prdata <= r.DATAout;
97 Rdata <= r.DATAout;
98 end case;
98 end case;
99 end if;
99 end if;
100
100
@@ -102,7 +102,7 begin
102 apbo.pconfig <= pconfig;
102 apbo.pconfig <= pconfig;
103 end process;
103 end process;
104
104
105
105 apbo.prdata <= Rdata when apbi.penable = '1';
106
106
107 -- pragma translate_off
107 -- pragma translate_off
108 -- bootmsg : report_version
108 -- bootmsg : report_version
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@@ -69,6 +69,7 type UART_ctrlr_Reg is record
69 end record;
69 end record;
70
70
71 signal Rec : UART_ctrlr_Reg;
71 signal Rec : UART_ctrlr_Reg;
72 signal Rdata : std_logic_vector(31 downto 0);
72
73
73 begin
74 begin
74
75
@@ -88,7 +89,6 Rec.UART_Cfg(4) <= NwData;
88 begin
89 begin
89 if(rst='0')then
90 if(rst='0')then
90 Rec.UART_Wdata <= (others => '0');
91 Rec.UART_Wdata <= (others => '0');
91 apbo.prdata <= (others => '0');
92
92
93 elsif(clk'event and clk='1')then
93 elsif(clk'event and clk='1')then
94
94
@@ -109,20 +109,21 Rec.UART_Cfg(4) <= NwData;
109 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
109 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
110 case apbi.paddr(abits-1 downto 2) is
110 case apbi.paddr(abits-1 downto 2) is
111 when "000000" =>
111 when "000000" =>
112 apbo.prdata(31 downto 27) <= Rec.UART_Cfg;
112 Rdata(31 downto 27) <= Rec.UART_Cfg;
113 apbo.prdata(26 downto 12) <= (others => '0');
113 Rdata(26 downto 12) <= (others => '0');
114 apbo.prdata(11 downto 0) <= Rec.UART_BTrig;
114 Rdata(11 downto 0) <= Rec.UART_BTrig;
115 when "000001" =>
115 when "000001" =>
116 apbo.prdata(7 downto 0) <= Rec.UART_Wdata;
116 Rdata(7 downto 0) <= Rec.UART_Wdata;
117 when "000010" =>
117 when "000010" =>
118 apbo.prdata(7 downto 0) <= Rec.UART_Rdata;
118 Rdata(7 downto 0) <= Rec.UART_Rdata;
119 when others =>
119 when others =>
120 apbo.prdata <= (others => '0');
120 Rdata <= (others => '0');
121 end case;
121 end case;
122 end if;
122 end if;
123
123
124 end if;
124 end if;
125 apbo.pconfig <= pconfig;
125 apbo.pconfig <= pconfig;
126 end process;
126 end process;
127
127
128 apbo.prdata <= Rdata when apbi.penable = '1';
128 end ar_APB_UART; No newline at end of file
129 end ar_APB_UART;
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@@ -10,6 +10,26 use lpp.lpp_amba.all;
10
10
11 package lpp_uart is
11 package lpp_uart is
12
12
13
14 component APB_UART is
15 generic (
16 pindex : integer := 0;
17 paddr : integer := 0;
18 pmask : integer := 16#fff#;
19 pirq : integer := 0;
20 abits : integer := 8;
21 Data_sz : integer := 8);
22 port (
23 clk : in std_logic;
24 rst : in std_logic;
25 apbi : in apb_slv_in_type;
26 apbo : out apb_slv_out_type;
27 TXD : out std_logic;
28 RXD : in std_logic
29 );
30 end component;
31
32
13 component UART is
33 component UART is
14 generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee
34 generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee
15 port(
35 port(
@@ -57,23 +77,5 port(
57 );
77 );
58 end component;
78 end component;
59
79
60 component APB_UART is
61 generic (
62 pindex : integer := 0;
63 paddr : integer := 0;
64 pmask : integer := 16#fff#;
65 pirq : integer := 0;
66 abits : integer := 8;
67 Data_sz : integer := 8);
68 port (
69 clk : in std_logic;
70 rst : in std_logic;
71 apbi : in apb_slv_in_type;
72 apbo : out apb_slv_out_type;
73 TXD : out std_logic;
74 RXD : in std_logic
75 );
76 end component;
77
78
80
79 end lpp_uart; No newline at end of file
81 end lpp_uart;
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