diff --git a/Makefile b/Makefile --- a/Makefile +++ b/Makefile @@ -43,5 +43,5 @@ Patched-dist: Patch-GRLIB doc: doxygen lib/lpp/Doxyfile - make lib/lpp/doc/latex - cp lib/lpp/doc/latex/refman.pdf lib/lpp/doc/VHD_lib.pdf + #make lib/lpp/doc/latex + #cp lib/lpp/doc/latex/refman.pdf lib/lpp/doc/VHD_lib.pdf diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/vhdlsyn.txt b/lib/lpp/amba_lcd_16x2_ctrlr/vhdlsyn.txt --- a/lib/lpp/amba_lcd_16x2_ctrlr/vhdlsyn.txt +++ b/lib/lpp/amba_lcd_16x2_ctrlr/vhdlsyn.txt @@ -1,5 +1,3 @@ -amba_lcd_16x2_ctrlr.vhd -apb_lcd_ctrlr.vhd FRAME_CLK.vhd LCD_16x2_CFG.vhd LCD_16x2_DRVR.vhd @@ -7,3 +5,5 @@ LCD_16x2_ENGINE.vhd LCD_2x16_DRIVER.vhd LCD_CLK_GENERATOR.vhd Top_LCD.vhd +amba_lcd_16x2_ctrlr.vhd +apb_lcd_ctrlr.vhd diff --git a/lib/lpp/dirs.txt b/lib/lpp/dirs.txt --- a/lib/lpp/dirs.txt +++ b/lib/lpp/dirs.txt @@ -1,4 +1,6 @@ +./amba_lcd_16x2_ctrlr +./dsp/iir_filter ./general_purpose ./lpp_amba -./dsp/iir_filter -./amba_lcd_16x2_ctrlr +./lpp_cna +./lpp_uart diff --git a/lib/lpp/dsp/iir_filter/vhdlsyn.txt b/lib/lpp/dsp/iir_filter/vhdlsyn.txt --- a/lib/lpp/dsp/iir_filter/vhdlsyn.txt +++ b/lib/lpp/dsp/iir_filter/vhdlsyn.txt @@ -1,12 +1,12 @@ APB_IIR_CEL.vhd +FILTER.vhd +FILTER_RAM_CTRLR.vhd FILTERcfg.vhd FilterCTRLR.vhd -FILTER_RAM_CTRLR.vhd -FILTER.vhd IIR_CEL_CTRLR.vhd IIR_CEL_FILTER.vhd -iir_filter.vhd +RAM.vhd RAM_CEL.vhd RAM_CTRLR2.vhd -RAM.vhd Top_Filtre_IIR.vhd +iir_filter.vhd diff --git a/lib/lpp/general_purpose/vhdlsyn.txt b/lib/lpp/general_purpose/vhdlsyn.txt --- a/lib/lpp/general_purpose/vhdlsyn.txt +++ b/lib/lpp/general_purpose/vhdlsyn.txt @@ -1,13 +1,13 @@ -Adder.vhd ADDRcntr.vhd ALU.vhd -general_purpose.vhd +Adder.vhd +MAC.vhd MAC_CONTROLER.vhd -MAC_MUX2.vhd MAC_MUX.vhd +MAC_MUX2.vhd MAC_REG.vhd -MAC.vhd +MUX2.vhd Multiplier.vhd -MUX2.vhd REG.vhd Shifter.vhd +general_purpose.vhd diff --git a/lib/lpp/lpp_CNA_amba/APB_CNA.vhd b/lib/lpp/lpp_CNA_amba/APB_CNA.vhd deleted file mode 100644 --- a/lib/lpp/lpp_CNA_amba/APB_CNA.vhd +++ /dev/null @@ -1,126 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- APB_CNA.vhd - -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library lpp; -use lpp.lpp_CNA_amba.all; - - -entity APB_CNA is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8); - port ( - clk : in std_logic; - rst : in std_logic; - apbi : in apb_slv_in_type; - apbo : out apb_slv_out_type; - SYNC : out std_logic; - SCLK : out std_logic; - DATA : out std_logic - ); -end APB_CNA; - - -architecture ar_APB_CNA of APB_CNA is - -constant REVISION : integer := 1; - -constant pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), - 1 => apb_iobar(paddr, pmask)); - -signal flag_nw : std_logic; -signal bp : std_logic; -signal Rz : std_logic; -signal flag_sd : std_logic; -signal Rdata : std_logic_vector(31 downto 0); - -type CNA_ctrlr_Reg is record - CNA_Cfg : std_logic_vector(3 downto 0); - CNA_Data : std_logic_vector(15 downto 0); -end record; - -signal Rec : CNA_ctrlr_Reg; ---signal ConfigREG : std_logic_vector(3 downto 0); ---signal DataREG : std_logic_vector(15 downto 0); - -begin - -bp <= Rec.CNA_Cfg(0); -flag_nw <= Rec.CNA_Cfg(1); -Rec.CNA_Cfg(2) <= flag_sd; -Rec.CNA_Cfg(3) <= Rz; - - - - CONVERTER : entity Work.CNA_TabloC - port map(clk,rst,flag_nw,bp,Rec.CNA_Data,SYNC,SCLK,Rz,flag_sd,Data); - - - - process(rst,clk) - begin - if(rst='0')then - Rec.CNA_Data <= (others => '0'); - - elsif(clk'event and clk='1')then - - - --APB Write OP - if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => - Rec.CNA_Cfg(1 downto 0) <= apbi.pwdata(1 downto 0); - when "000001" => - Rec.CNA_Data <= apbi.pwdata(15 downto 0); - when others => - null; - end case; - end if; - - --APB READ OP - if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => - Rdata(31 downto 4) <= X"ABCDEF5"; - Rdata(3 downto 0) <= Rec.CNA_Cfg; - when "000001" => - Rdata(31 downto 16) <= X"FD18"; - Rdata(15 downto 0) <= Rec.CNA_Data; - when others => - Rdata <= (others => '0'); - end case; - end if; - - end if; - apbo.pconfig <= pconfig; - end process; - -apbo.prdata <= Rdata when apbi.penable = '1'; -end ar_APB_CNA; \ No newline at end of file diff --git a/lib/lpp/lpp_CNA_amba/CNA_TabloC.vhd b/lib/lpp/lpp_CNA_amba/CNA_TabloC.vhd deleted file mode 100644 --- a/lib/lpp/lpp_CNA_amba/CNA_TabloC.vhd +++ /dev/null @@ -1,71 +0,0 @@ --- CNA_TabloC.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.Convertisseur_config.all; - -entity CNA_TabloC is - port( - clock : in std_logic; - rst : in std_logic; - flag_nw : in std_logic; - bp : in std_logic; - Data_C : in std_logic_vector(15 downto 0); - SYNC : out std_logic; - SCLK : out std_logic; - Rz : out std_logic; - flag_sd : out std_logic; - Data : out std_logic - ); -end CNA_TabloC; - - -architecture ar_CNA_TabloC of CNA_TabloC is - -component CLKINT -port( A : in std_logic := 'U'; - Y : out std_logic); -end component; - -signal clk : std_logic; ---signal reset : std_logic; - -signal raz : std_logic; -signal sys_clk : std_logic; -signal Data_int : std_logic_vector(15 downto 0); -signal OKAI_send : std_logic; - -begin - - -CLKINT_0 : CLKINT - port map(A => clock, Y => clk); - -CLKINT_1 : CLKINT - port map(A => rst, Y => raz); - - -SystemCLK : entity work.Clock_Serie - generic map (nb_serial) - port map (clk,raz,sys_clk); - - -Signal_sync : entity work.GeneSYNC_flag - port map (clk,raz,flag_nw,sys_clk,OKAI_send,SYNC); - - -Serial : entity work.serialize - port map (clk,raz,sys_clk,Data_int,OKAI_send,flag_sd,Data); - - ---raz <= not reset; -Rz <= raz; -SCLK <= not sys_clk; ---Data_Cvec <= std_logic_vector(to_unsigned(Data_C,12)); ---Data_TOT <= "0001" & Data_Cvec; - -with bp select - Data_int <= X"9555" when '1', - Data_C when others; - -end ar_CNA_TabloC; \ No newline at end of file diff --git a/lib/lpp/lpp_CNA_amba/Convertisseur_config.vhd b/lib/lpp/lpp_CNA_amba/Convertisseur_config.vhd deleted file mode 100644 --- a/lib/lpp/lpp_CNA_amba/Convertisseur_config.vhd +++ /dev/null @@ -1,24 +0,0 @@ --- Convertisseur_config.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -Package Convertisseur_config is - - ---===========================================================| ---================= Valeurs Sinus 1Khz ======================| ---===========================================================| -type Tbl is array(natural range <>) of std_logic_vector(11 downto 0); -constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF"); - ---constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80"); - - ---===========================================================| ---============= Fréquence de sérialisation ==================| ---===========================================================| -constant Freq_serial : integer := 1_000_000; -constant nb_serial : integer := 40_000_000 / Freq_serial; - -end; \ No newline at end of file diff --git a/lib/lpp/lpp_CNA_amba/GeneSYNC_flag.vhd b/lib/lpp/lpp_CNA_amba/GeneSYNC_flag.vhd deleted file mode 100644 --- a/lib/lpp/lpp_CNA_amba/GeneSYNC_flag.vhd +++ /dev/null @@ -1,94 +0,0 @@ --- GeneSYNC_flag.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity GeneSYNC_flag is - -port( - clk,raz : in std_logic; - flag_nw : in std_logic; - Sysclk : in std_logic; - OKAI_send : out std_logic; - SYNC : out std_logic -); - -end GeneSYNC_flag; - - -architecture ar_GeneSYNC_flag of GeneSYNC_flag is - -signal Sysclk_reg : std_logic; -signal flag_nw_reg : std_logic; -signal count : integer; - -type etat is (e0,e1,e2,eX); -signal ect : etat; - -begin - process (clk,raz) - begin - if(raz='0')then - SYNC <= '0'; - Sysclk_reg <= '0'; - flag_nw_reg <= '0'; - count <= 14; - OKAI_send <= '0'; - ect <= e0; - - elsif(clk' event and clk='1')then - Sysclk_reg <= Sysclk; - flag_nw_reg <= flag_nw; - - case ect is - when e0 => - if(flag_nw_reg='0' and flag_nw='1')then - ect <= e1; - else - count <= 14; - ect <= e0; - end if; - - - when e1 => - if(Sysclk_reg='1' and Sysclk='0')then - if(count=15)then - SYNC <= '1'; - count <= count+1; - ect <= e2; - elsif(count=16)then - count <= 0; - OKAI_send <= '1'; - ect <= eX; - else - count <= count+1; - OKAI_send <= '0'; - ect <= e1; - end if; - end if; - - - when e2 => - if(Sysclk_reg='0' and Sysclk='1')then - if(count=16)then - SYNC <= '0'; - ect <= e1; - end if; - end if; - - when eX => - if(Sysclk_reg='0' and Sysclk='1')then - if(count=15)then - OKAI_send <= '0'; - ect <= e0; - else - count <= count+1; - ect <= eX; - end if; - end if; - - end case; - end if; - - end process; -end ar_GeneSYNC_flag; \ No newline at end of file diff --git a/lib/lpp/lpp_CNA_amba/Serialize.vhd b/lib/lpp/lpp_CNA_amba/Serialize.vhd deleted file mode 100644 --- a/lib/lpp/lpp_CNA_amba/Serialize.vhd +++ /dev/null @@ -1,86 +0,0 @@ --- Serialize.vhd -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; - -entity Serialize is - -port( - clk,raz : in std_logic; - sclk : in std_logic; - vectin : in std_logic_vector(15 downto 0); - send : in std_logic; - sended : out std_logic; - Data : out std_logic); - -end Serialize; - - -architecture ar_Serialize of Serialize is - -type etat is (attente,serialize); -signal ect : etat; - -signal vector_int : std_logic_vector(16 downto 0); -signal vectin_reg : std_logic_vector(15 downto 0); -signal load : std_logic; -signal N : integer range 0 to 16; -signal CPT_ended : std_logic:='0'; - -begin - process(clk,raz) - begin - if(raz='0')then - ect <= attente; - vectin_reg <= (others=> '0'); - load <= '0'; - sended <= '1'; - - elsif(clk'event and clk='1')then - vectin_reg <= vectin; - - case ect is - when attente => - if (send='1') then - sended <= '0'; - load <= '1'; - ect <= serialize; - else - ect <= attente; - end if; - - when serialize => - load <= '0'; - if(CPT_ended='1')then - ect <= attente; - sended <= '1'; - end if; - - end case; - end if; - end process; - - process(sclk,load,raz) - begin - if (raz='0')then - vector_int <= (others=> '0'); - N <= 16; - elsif(load='1')then - vector_int <= vectin & '0'; - N <= 0; - elsif(sclk'event and sclk='0')then - if (CPT_ended='0') then - vector_int <= vector_int(15 downto 0) & '0'; - N <= N+1; - end if; - end if; - end process; - -CPT_ended <= '1' when N = 16 else '0'; - -with ect select - Data <= vector_int(16) when serialize, - '0' when others; - -end ar_Serialize; - diff --git a/lib/lpp/lpp_CNA_amba/clock.vhd b/lib/lpp/lpp_CNA_amba/clock.vhd deleted file mode 100644 --- a/lib/lpp/lpp_CNA_amba/clock.vhd +++ /dev/null @@ -1,41 +0,0 @@ --- clock.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - -entity Clock_Serie is - -generic(N :integer := 695); - -port( - clk, raz : in std_logic ; - clock : out std_logic); - -end Clock_Serie; - - -architecture ar_Clock_Serie of Clock_Serie is - -signal clockint : std_logic; -signal countint : integer range 0 to N/2-1; - -begin - process (clk,raz) - begin - if(raz = '0') then - countint <= 0; - clockint <= '0'; - elsif (clk' event and clk='1') then - if (countint = N/2-1) then - countint <= 0; - clockint <= not clockint; - else - countint <= countint+1; - end if; - end if; - end process; - -clock <= clockint; - -end ar_Clock_Serie; \ No newline at end of file diff --git a/lib/lpp/lpp_CNA_amba/lpp_CNA_amba.vhd b/lib/lpp/lpp_CNA_amba/lpp_CNA_amba.vhd deleted file mode 100644 --- a/lib/lpp/lpp_CNA_amba/lpp_CNA_amba.vhd +++ /dev/null @@ -1,52 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; --- pragma translate_off -use std.textio.all; --- pragma translate_on -library lpp; -use lpp.lpp_amba.all; - - -package lpp_CNA_amba is - - -component APB_CNA is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8); - port ( - clk : in std_logic; - rst : in std_logic; - apbi : in apb_slv_in_type; - apbo : out apb_slv_out_type; - SYNC : out std_logic; - SCLK : out std_logic; - DATA : out std_logic - ); -end component; - -end; diff --git a/lib/lpp/lpp_amba/APB_MULTI_DIODE.vhd b/lib/lpp/lpp_amba/APB_MULTI_DIODE.vhd --- a/lib/lpp/lpp_amba/APB_MULTI_DIODE.vhd +++ b/lib/lpp/lpp_amba/APB_MULTI_DIODE.vhd @@ -62,6 +62,7 @@ type LEDregs is record end record; signal r : LEDregs; +signal Rdata : std_logic_vector(31 downto 0); begin @@ -73,7 +74,6 @@ begin if rst = '0' then LED <= "000"; r.DATAin <= (others => '0'); - apbo.prdata <= (others => '0'); elsif clk'event and clk = '1' then LED <= r.DATAin(2 downto 0); @@ -92,9 +92,9 @@ begin if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then case apbi.paddr(abits-1 downto 2) is when "000000" => - apbo.prdata <= r.DATAin; + Rdata <= r.DATAin; when others => - apbo.prdata <= r.DATAout; + Rdata <= r.DATAout; end case; end if; @@ -102,5 +102,5 @@ begin apbo.pconfig <= pconfig; end process; - +apbo.prdata <= Rdata when apbi.penable = '1'; end ar_APB_MULTI_DIODE; \ No newline at end of file diff --git a/lib/lpp/lpp_amba/APB_SIMPLE_DIODE.vhd b/lib/lpp/lpp_amba/APB_SIMPLE_DIODE.vhd --- a/lib/lpp/lpp_amba/APB_SIMPLE_DIODE.vhd +++ b/lib/lpp/lpp_amba/APB_SIMPLE_DIODE.vhd @@ -62,6 +62,7 @@ type LEDregs is record end record; signal r : LEDregs; +signal Rdata : std_logic_vector(31 downto 0); begin @@ -73,7 +74,6 @@ begin if rst = '0' then LED <= '0'; r.DATAin <= (others => '0'); - apbo.prdata <= (others => '0'); elsif clk'event and clk = '1' then LED <= r.DATAin(0); @@ -92,9 +92,9 @@ begin if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then case apbi.paddr(abits-1 downto 2) is when "000000" => - apbo.prdata <= r.DATAin; + Rdata <= r.DATAin; when others => - apbo.prdata <= r.DATAout; + Rdata <= r.DATAout; end case; end if; @@ -102,7 +102,7 @@ begin apbo.pconfig <= pconfig; end process; - +apbo.prdata <= Rdata when apbi.penable = '1'; -- pragma translate_off -- bootmsg : report_version diff --git a/lib/lpp/lpp_cna/APB_CNA.vhd b/lib/lpp/lpp_cna/APB_CNA.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_cna/APB_CNA.vhd @@ -0,0 +1,105 @@ +-- APB_CNA.vhd + +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library lpp; +use lpp.lpp_amba.all; +use lpp.lpp_cna.all; + + +entity APB_CNA is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8); + port ( + clk : in std_logic; + rst : in std_logic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + SYNC : out std_logic; + SCLK : out std_logic; + DATA : out std_logic + ); +end APB_CNA; + + +architecture ar_APB_CNA of APB_CNA is + +constant REVISION : integer := 1; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), + 1 => apb_iobar(paddr, pmask)); + +signal flag_nw : std_logic; +signal bp : std_logic; +signal Rz : std_logic; +signal flag_sd : std_logic; + +type CNA_ctrlr_Reg is record + CNA_Cfg : std_logic_vector(3 downto 0); + CNA_Data : std_logic_vector(15 downto 0); +end record; + +signal Rec : CNA_ctrlr_Reg; +signal Rdata : std_logic_vector(31 downto 0); + +begin + +bp <= Rec.CNA_Cfg(0); +flag_nw <= Rec.CNA_Cfg(1); +Rec.CNA_Cfg(2) <= flag_sd; +Rec.CNA_Cfg(3) <= Rz; + + + CONVERTER : entity Work.CNA_TabloC + port map(clk,rst,flag_nw,bp,Rec.CNA_Data,SYNC,SCLK,Rz,flag_sd,Data); + + + process(rst,clk) + begin + if(rst='0')then + Rec.CNA_Data <= (others => '0'); + + elsif(clk'event and clk='1')then + + + --APB Write OP + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + Rec.CNA_Cfg(1 downto 0) <= apbi.pwdata(1 downto 0); + when "000001" => + Rec.CNA_Data <= apbi.pwdata(15 downto 0); + when others => + null; + end case; + end if; + + --APB READ OP + if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + Rdata(31 downto 4) <= X"ABCDEF5"; + Rdata(3 downto 0) <= Rec.CNA_Cfg; + when "000001" => + Rdata(31 downto 16) <= X"FD18"; + Rdata(15 downto 0) <= Rec.CNA_Data; + when others => + Rdata <= (others => '0'); + end case; + end if; + + end if; + apbo.pconfig <= pconfig; + end process; + +apbo.prdata <= Rdata when apbi.penable = '1'; +end ar_APB_CNA; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/CNA_TabloC.vhd b/lib/lpp/lpp_cna/CNA_TabloC.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_cna/CNA_TabloC.vhd @@ -0,0 +1,71 @@ +-- CNA_TabloC.vhd +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.Convertisseur_config.all; + +entity CNA_TabloC is + port( + clock : in std_logic; + rst : in std_logic; + flag_nw : in std_logic; + bp : in std_logic; + Data_C : in std_logic_vector(15 downto 0); + SYNC : out std_logic; + SCLK : out std_logic; + Rz : out std_logic; + flag_sd : out std_logic; + Data : out std_logic + ); +end CNA_TabloC; + + +architecture ar_CNA_TabloC of CNA_TabloC is + +component CLKINT +port( A : in std_logic := 'U'; + Y : out std_logic); +end component; + +signal clk : std_logic; +--signal reset : std_logic; + +signal raz : std_logic; +signal sys_clk : std_logic; +signal Data_int : std_logic_vector(15 downto 0); +signal OKAI_send : std_logic; + +begin + + +CLKINT_0 : CLKINT + port map(A => clock, Y => clk); + +CLKINT_1 : CLKINT + port map(A => rst, Y => raz); + + +SystemCLK : entity work.Clock_Serie + generic map (nb_serial) + port map (clk,raz,sys_clk); + + +Signal_sync : entity work.GeneSYNC_flag + port map (clk,raz,flag_nw,sys_clk,OKAI_send,SYNC); + + +Serial : entity work.serialize + port map (clk,raz,sys_clk,Data_int,OKAI_send,flag_sd,Data); + + +--raz <= not reset; +Rz <= raz; +SCLK <= not sys_clk; +--Data_Cvec <= std_logic_vector(to_unsigned(Data_C,12)); +--Data_TOT <= "0001" & Data_Cvec; + +with bp select + Data_int <= X"9555" when '1', + Data_C when others; + +end ar_CNA_TabloC; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/Convertisseur_config.vhd b/lib/lpp/lpp_cna/Convertisseur_config.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_cna/Convertisseur_config.vhd @@ -0,0 +1,24 @@ +-- Convertisseur_config.vhd +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +Package Convertisseur_config is + + +--===========================================================| +--================= Valeurs Sinus 1Khz ======================| +--===========================================================| +type Tbl is array(natural range <>) of std_logic_vector(11 downto 0); +constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF"); + +--constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80"); + + +--===========================================================| +--============= Fréquence de sérialisation ==================| +--===========================================================| +constant Freq_serial : integer := 1_000_000; +constant nb_serial : integer := 40_000_000 / Freq_serial; + +end; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/GeneSYNC_flag.vhd b/lib/lpp/lpp_cna/GeneSYNC_flag.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_cna/GeneSYNC_flag.vhd @@ -0,0 +1,94 @@ +-- GeneSYNC_flag.vhd +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity GeneSYNC_flag is + +port( + clk,raz : in std_logic; + flag_nw : in std_logic; + Sysclk : in std_logic; + OKAI_send : out std_logic; + SYNC : out std_logic +); + +end GeneSYNC_flag; + + +architecture ar_GeneSYNC_flag of GeneSYNC_flag is + +signal Sysclk_reg : std_logic; +signal flag_nw_reg : std_logic; +signal count : integer; + +type etat is (e0,e1,e2,eX); +signal ect : etat; + +begin + process (clk,raz) + begin + if(raz='0')then + SYNC <= '0'; + Sysclk_reg <= '0'; + flag_nw_reg <= '0'; + count <= 14; + OKAI_send <= '0'; + ect <= e0; + + elsif(clk' event and clk='1')then + Sysclk_reg <= Sysclk; + flag_nw_reg <= flag_nw; + + case ect is + when e0 => + if(flag_nw_reg='0' and flag_nw='1')then + ect <= e1; + else + count <= 14; + ect <= e0; + end if; + + + when e1 => + if(Sysclk_reg='1' and Sysclk='0')then + if(count=15)then + SYNC <= '1'; + count <= count+1; + ect <= e2; + elsif(count=16)then + count <= 0; + OKAI_send <= '1'; + ect <= eX; + else + count <= count+1; + OKAI_send <= '0'; + ect <= e1; + end if; + end if; + + + when e2 => + if(Sysclk_reg='0' and Sysclk='1')then + if(count=16)then + SYNC <= '0'; + ect <= e1; + end if; + end if; + + when eX => + if(Sysclk_reg='0' and Sysclk='1')then + if(count=15)then + OKAI_send <= '0'; + ect <= e0; + else + count <= count+1; + ect <= eX; + end if; + end if; + + end case; + end if; + + end process; +end ar_GeneSYNC_flag; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/Serialize.vhd b/lib/lpp/lpp_cna/Serialize.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_cna/Serialize.vhd @@ -0,0 +1,86 @@ +-- Serialize.vhd +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity Serialize is + +port( + clk,raz : in std_logic; + sclk : in std_logic; + vectin : in std_logic_vector(15 downto 0); + send : in std_logic; + sended : out std_logic; + Data : out std_logic); + +end Serialize; + + +architecture ar_Serialize of Serialize is + +type etat is (attente,serialize); +signal ect : etat; + +signal vector_int : std_logic_vector(16 downto 0); +signal vectin_reg : std_logic_vector(15 downto 0); +signal load : std_logic; +signal N : integer range 0 to 16; +signal CPT_ended : std_logic:='0'; + +begin + process(clk,raz) + begin + if(raz='0')then + ect <= attente; + vectin_reg <= (others=> '0'); + load <= '0'; + sended <= '1'; + + elsif(clk'event and clk='1')then + vectin_reg <= vectin; + + case ect is + when attente => + if (send='1') then + sended <= '0'; + load <= '1'; + ect <= serialize; + else + ect <= attente; + end if; + + when serialize => + load <= '0'; + if(CPT_ended='1')then + ect <= attente; + sended <= '1'; + end if; + + end case; + end if; + end process; + + process(sclk,load,raz) + begin + if (raz='0')then + vector_int <= (others=> '0'); + N <= 16; + elsif(load='1')then + vector_int <= vectin & '0'; + N <= 0; + elsif(sclk'event and sclk='0')then + if (CPT_ended='0') then + vector_int <= vector_int(15 downto 0) & '0'; + N <= N+1; + end if; + end if; + end process; + +CPT_ended <= '1' when N = 16 else '0'; + +with ect select + Data <= vector_int(16) when serialize, + '0' when others; + +end ar_Serialize; + diff --git a/lib/lpp/lpp_cna/clock.vhd b/lib/lpp/lpp_cna/clock.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_cna/clock.vhd @@ -0,0 +1,41 @@ +-- clock.vhd +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + + +entity Clock_Serie is + +generic(N :integer := 695); + +port( + clk, raz : in std_logic ; + clock : out std_logic); + +end Clock_Serie; + + +architecture ar_Clock_Serie of Clock_Serie is + +signal clockint : std_logic; +signal countint : integer range 0 to N/2-1; + +begin + process (clk,raz) + begin + if(raz = '0') then + countint <= 0; + clockint <= '0'; + elsif (clk' event and clk='1') then + if (countint = N/2-1) then + countint <= 0; + clockint <= not clockint; + else + countint <= countint+1; + end if; + end if; + end process; + +clock <= clockint; + +end ar_Clock_Serie; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/lpp_cna.vhd b/lib/lpp/lpp_cna/lpp_cna.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_cna/lpp_cna.vhd @@ -0,0 +1,77 @@ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +-- pragma translate_off +use std.textio.all; +-- pragma translate_on +library lpp; +use lpp.lpp_amba.all; + + +package lpp_cna is + +component APB_CNA is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8); + port ( + clk : in std_logic; + rst : in std_logic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + SYNC : out std_logic; + SCLK : out std_logic; + DATA : out std_logic + ); +end component; + + +component CNA_TabloC is + port( + clock : in std_logic; + rst : in std_logic; + flag_nw : in std_logic; + bp : in std_logic; + Data_C : in std_logic_vector(15 downto 0); + SYNC : out std_logic; + SCLK : out std_logic; + Rz : out std_logic; + flag_sd : out std_logic; + Data : out std_logic + ); +end component; + + +component Clock_Serie is + generic(N :integer := 695); + port( + clk, raz : in std_logic ; + clock : out std_logic); +end component; + + +component GeneSYNC_flag is + port( + clk,raz : in std_logic; + flag_nw : in std_logic; + Sysclk : in std_logic; + OKAI_send : out std_logic; + SYNC : out std_logic); +end component; + + +component Serialize is +port( + clk,raz : in std_logic; + sclk : in std_logic; + vectin : in std_logic_vector(15 downto 0); + send : in std_logic; + sended : out std_logic; + Data : out std_logic); +end component; + +end; diff --git a/lib/lpp/lpp_uart/APB_UART.vhd b/lib/lpp/lpp_uart/APB_UART.vhd --- a/lib/lpp/lpp_uart/APB_UART.vhd +++ b/lib/lpp/lpp_uart/APB_UART.vhd @@ -69,6 +69,7 @@ type UART_ctrlr_Reg is record end record; signal Rec : UART_ctrlr_Reg; +signal Rdata : std_logic_vector(31 downto 0); begin @@ -88,7 +89,6 @@ Rec.UART_Cfg(4) <= NwData; begin if(rst='0')then Rec.UART_Wdata <= (others => '0'); - apbo.prdata <= (others => '0'); elsif(clk'event and clk='1')then @@ -109,20 +109,21 @@ Rec.UART_Cfg(4) <= NwData; if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then case apbi.paddr(abits-1 downto 2) is when "000000" => - apbo.prdata(31 downto 27) <= Rec.UART_Cfg; - apbo.prdata(26 downto 12) <= (others => '0'); - apbo.prdata(11 downto 0) <= Rec.UART_BTrig; + Rdata(31 downto 27) <= Rec.UART_Cfg; + Rdata(26 downto 12) <= (others => '0'); + Rdata(11 downto 0) <= Rec.UART_BTrig; when "000001" => - apbo.prdata(7 downto 0) <= Rec.UART_Wdata; + Rdata(7 downto 0) <= Rec.UART_Wdata; when "000010" => - apbo.prdata(7 downto 0) <= Rec.UART_Rdata; + Rdata(7 downto 0) <= Rec.UART_Rdata; when others => - apbo.prdata <= (others => '0'); + Rdata <= (others => '0'); end case; end if; end if; apbo.pconfig <= pconfig; end process; - + +apbo.prdata <= Rdata when apbi.penable = '1'; end ar_APB_UART; \ No newline at end of file diff --git a/lib/lpp/lpp_uart/lpp_uart.vhd b/lib/lpp/lpp_uart/lpp_uart.vhd --- a/lib/lpp/lpp_uart/lpp_uart.vhd +++ b/lib/lpp/lpp_uart/lpp_uart.vhd @@ -10,6 +10,26 @@ use lpp.lpp_amba.all; package lpp_uart is + +component APB_UART is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + Data_sz : integer := 8); + port ( + clk : in std_logic; + rst : in std_logic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + TXD : out std_logic; + RXD : in std_logic + ); +end component; + + component UART is generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee port( @@ -57,23 +77,5 @@ port( ); end component; -component APB_UART is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - Data_sz : integer := 8); - port ( - clk : in std_logic; - rst : in std_logic; - apbi : in apb_slv_in_type; - apbo : out apb_slv_out_type; - TXD : out std_logic; - RXD : in std_logic - ); -end component; - end lpp_uart; \ No newline at end of file