HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r641:0dc1942211a7

Added file init for RAM_CEL IP.[Need tests]...

Jeandet Alexis -

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designs/Validation_IIR_f0_LFR/Makefile +7 -2

             #GRLIB=../..
             VHDLIB=../..
             SCRIPTSDIR=$(VHDLIB)/scripts/
             GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
             TOP=testbench
             BOARD=LFR-EQM
             include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
             DEVICE=$(PART)-$(PACKAGE)$(SPEED)
             UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
             QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
             EFFORT=high
             XSTOPT=
             SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
             #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
             VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd
             VHDLSIMFILES= tb.vhd
             SIMTOP=testbench
             #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
             PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
             SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
             BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
             CLEAN=soft-clean
             TECHLIBS = axcelerator
             LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
             	tmtc openchip hynix ihp gleichmann micron usbhc  opencores
-            DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
+            DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
             	pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \
+            	./dsp/lpp_fft_rtax \
             	./amba_lcd_16x2_ctrlr \
             	./general_purpose/lpp_AMR \
             	./general_purpose/lpp_balise \
             	./general_purpose/lpp_delay \
             	./lpp_bootloader \
             	./lfr_management \
             	./lpp_sim \
             	./lpp_sim/CY7C1061DV33 \
             	./lpp_cna \
             	./lpp_uart \
             	./lpp_usb \
             	./dsp/lpp_fft \
+            	./lpp_leon3_soc \
+            	./lpp_debug_lfr
             FILESKIP = i2cmst.vhd \
             	APB_MULTI_DIODE.vhd \
             	APB_MULTI_DIODE.vhd \
             	Top_MatrixSpec.vhd \
             	APB_FFT.vhd \
+                    lpp_lfr_ms_FFT.vhd \
             	lpp_lfr_apbreg.vhd \
-            	CoreFFT.vhd
+            	CoreFFT.vhd \
+            	lpp_lfr_ms.vhd
             include $(GRLIB)/bin/Makefile
             include $(GRLIB)/software/leon3/Makefile
             ##################  project specific targets ##########################

designs/Validation_IIR_f0_LFR/tb.vhd +7 -2

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             USE IEEE.std_logic_signed.ALL;
             USE IEEE.MATH_real.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY std;
             USE std.textio.ALL;
             LIBRARY lpp;
             USE lpp.iir_filter.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_lfr_filter_coeff.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.data_type_pkg.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.general_purpose.ALL;
             ENTITY testbench IS
+            GENERIC(
+                tech          : INTEGER := 0; --axcel,
+                Mem_use       : INTEGER := use_CEL --use_RAM
+            );
             END;
             ARCHITECTURE behav OF testbench IS
               CONSTANT ChanelCount   : INTEGER := 8;
               CONSTANT Coef_SZ       : INTEGER := 9;
               CONSTANT CoefCntPerCel : INTEGER := 6;
               CONSTANT CoefPerCel    : INTEGER := 5;
               CONSTANT Cels_count    : INTEGER := 5;
               SIGNAL sample     : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_val : STD_LOGIC;
               SIGNAL sample_fx     : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_fx_val : STD_LOGIC;
               SIGNAL TSTAMP    : INTEGER   := 0;
               SIGNAL clk       : STD_LOGIC := '0';
               SIGNAL clk_24k   : STD_LOGIC := '0';
               SIGNAL clk_24k_r : STD_LOGIC := '0';
               SIGNAL rstn      : STD_LOGIC;
               SIGNAL signal_gen : Samples(7 DOWNTO 0);
               SIGNAL offset_gen : Samples(7 DOWNTO 0);
               --SIGNAL sample_fx_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_fx_wdata : Samples(ChanelCount-1 DOWNTO 0);
               COMPONENT generator IS
                 GENERIC (
                   AMPLITUDE : INTEGER := 100;
                   NB_BITS   : INTEGER := 16);
                 PORT (
                   clk  : IN STD_LOGIC;
                   rstn : IN STD_LOGIC;
                   run  : IN STD_LOGIC;
                   data_ack : IN  STD_LOGIC;
                   offset   : IN  STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
                   data     : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
                   );
               END COMPONENT;
               FILE log_input     : TEXT OPEN write_mode IS "log_input.txt";
               FILE log_output_fx : TEXT OPEN write_mode IS "log_output_fx.txt";
               SIGNAL end_of_simu : STD_LOGIC := '0';
             BEGIN
               -----------------------------------------------------------------------------
               -- CLOCK and RESET
               -----------------------------------------------------------------------------
               clk <= NOT clk AFTER 5 ns;
               PROCESS
               BEGIN  -- PROCESS
                 end_of_simu <= '0';
                 WAIT UNTIL clk = '1';
                 rstn <= '0';
                 WAIT UNTIL clk = '1';
                 WAIT UNTIL clk = '1';
                 WAIT UNTIL clk = '1';
                 rstn <= '1';
                 WAIT FOR 2000 ms;
                 end_of_simu <= '1';
                 WAIT UNTIL clk = '1';
                 REPORT "*** END simulation ***" SEVERITY failure;
                 WAIT;
               END PROCESS;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- COMMON TIMESTAMPS
               -----------------------------------------------------------------------------
               PROCESS(clk)
               BEGIN
                 IF clk'EVENT AND clk = '1' THEN
                   TSTAMP <= TSTAMP+1;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- LPP_LFR_FILTER f0
               -----------------------------------------------------------------------------
               IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
                 GENERIC MAP (
-                  tech         => axcel,
+                  tech         => tech,
                   Mem_use      => use_RAM,
                   Sample_SZ    => 18,
                   Coef_SZ      => Coef_SZ,
                   Coef_Nb      => 25,
                   Coef_sel_SZ  => 5,
                   Cels_count   => Cels_count,
-                  ChanelsCount => ChanelCount)
+                  ChanelsCount => ChanelCount,
+                  FILENAME     => "RAM.txt")
                 PORT MAP (
                   rstn     => rstn,
                   clk      => clk,
                   virg_pos => 7,
                   coefs    => CoefsInitValCst_v2,
                   sample_in_val  => sample_val,
                   sample_in      => sample,
                   sample_out_val => sample_fx_val,
                   sample_out     => sample_fx);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- SAMPLE GENERATION
               -----------------------------------------------------------------------------
               clk_24k <= NOT clk_24k AFTER 20345 ns;
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_val <= '0';
                   clk_24k_r  <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   clk_24k_r <= clk_24k;
                   IF clk_24k = '1' AND clk_24k_r = '0' THEN
                     sample_val <= '1';
                   ELSE
                     sample_val <= '0';
                   END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               generators : FOR I IN 0 TO 7 GENERATE
                 gen1 : generator
                   GENERIC MAP (
                     AMPLITUDE => 100,
                     NB_BITS   => 16)
                   PORT MAP (
                     clk      => clk,
                     rstn     => rstn,
                     run      => '1',
                     data_ack => sample_val,
                     offset   => offset_gen(I),
                     data     => signal_gen(I)
                     );
                 offset_gen(I) <= STD_LOGIC_VECTOR(to_signed((I*200), 16));
               END GENERATE generators;
               ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
                 SampleLoop : FOR j IN 0 TO 15 GENERATE
                   sample(i,j) <= signal_gen(i)(j);
                   sample_fx_wdata(i)(j) <= sample_fx(i,j);
                 END GENERATE;
                 sample(i, 16) <= signal_gen(i)(15);
                 sample(i, 17) <= signal_gen(i)(15);
               END GENERATE;
               -----------------------------------------------------------------------------
               --  RECORD SIGNALS
               -----------------------------------------------------------------------------
               -- PROCESS(sample_val)
               --   VARIABLE line_var : LINE;
               -- BEGIN
               --   IF sample_val'EVENT AND sample_val = '1' THEN
               --     write(line_var, INTEGER'IMAGE(TSTAMP));
               --     FOR I IN 0 TO 7 LOOP
               --       write(line_var, "  " & INTEGER'IMAGE(to_integer(SIGNED(signal_gen(I)))));
               --     END LOOP;
               --     writeline(log_input, line_var);
               --   END IF;
               --  END PROCESS;
               PROCESS(sample_fx_val,end_of_simu)
                 VARIABLE line_var : LINE;
               BEGIN
                 IF sample_fx_val'EVENT AND sample_fx_val = '1' THEN
                   write(line_var, INTEGER'IMAGE(TSTAMP));
                   FOR I IN 0 TO 5 LOOP
                     write(line_var, "  " & INTEGER'IMAGE(to_integer(SIGNED(sample_fx_wdata(I)))));
                   END LOOP;
                   writeline(log_output_fx, line_var);
                 END IF;
                 IF end_of_simu = '1' THEN
                   file_close(log_output_fx);
                 END IF;
               END PROCESS;
             END;

lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd +6 -3

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe PELLION
             --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY lpp;
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             ENTITY IIR_CEL_CTRLR_v2 IS
               GENERIC (
                 tech         : INTEGER := 0;
                 Mem_use      : INTEGER := use_RAM;
                 Sample_SZ    : INTEGER := 18;
                 Coef_SZ      : INTEGER := 9;
                 Coef_Nb      : INTEGER := 25;
                 Coef_sel_SZ  : INTEGER := 5;
                 Cels_count   : INTEGER := 5;
-                ChanelsCount : INTEGER := 8);
+                ChanelsCount : INTEGER := 8;
+                FILENAME     : STRING  := "");
               PORT (
                 rstn : IN STD_LOGIC;
                 clk  : IN STD_LOGIC;
                 virg_pos : IN INTEGER;
                 coefs    : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
                 sample_in_val : IN STD_LOGIC;
                 sample_in     : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
                 sample_out_val : OUT STD_LOGIC;
                 sample_out     : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
             END IIR_CEL_CTRLR_v2;
             ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_CEL_CTRLR_v2 IS
               COMPONENT IIR_CEL_CTRLR_v2_DATAFLOW
                 GENERIC (
                   tech        : INTEGER;
                   Mem_use     : INTEGER;
                   Sample_SZ   : INTEGER;
                   Coef_SZ     : INTEGER;
                   Coef_Nb     : INTEGER;
-                  Coef_sel_SZ : INTEGER);
+                  Coef_sel_SZ : INTEGER;
+                  FILENAME    : STRING);
                 PORT (
                   rstn           : IN  STD_LOGIC;
                   clk            : IN  STD_LOGIC;
                   virg_pos       : IN  INTEGER;
                   coefs          : IN  STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
                   in_sel_src     : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   init_mem_done  : out STD_LOGIC;
                   ram_sel_Wdata  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   ram_write      : IN  STD_LOGIC;
                   ram_read       : IN  STD_LOGIC;
                   raddr_rst      : IN  STD_LOGIC;
                   raddr_add1     : IN  STD_LOGIC;
                   waddr_previous : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   alu_sel_input  : IN  STD_LOGIC;
                   alu_sel_coeff  : IN  STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
                   alu_ctrl       : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
                   alu_comp       : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   sample_in      : IN  STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
                   sample_out     : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
               END COMPONENT;
               COMPONENT IIR_CEL_CTRLR_v2_CONTROL
                 GENERIC (
                   Coef_sel_SZ  : INTEGER;
                   Cels_count   : INTEGER;
                   ChanelsCount : INTEGER);
                 PORT (
                   rstn           : IN  STD_LOGIC;
                   clk            : IN  STD_LOGIC;
                   sample_in_val  : IN  STD_LOGIC;
                   sample_in_rot  : OUT STD_LOGIC;
                   sample_out_val : OUT STD_LOGIC;
                   sample_out_rot : OUT STD_LOGIC;
                   init_mem_done  : in  STD_LOGIC;  --TODO
                   in_sel_src     : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
                   ram_sel_Wdata  : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
                   ram_write      : OUT STD_LOGIC;
                   ram_read       : OUT STD_LOGIC;
                   raddr_rst      : OUT STD_LOGIC;
                   raddr_add1     : OUT STD_LOGIC;
                   waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
                   alu_sel_input  : OUT STD_LOGIC;
                   alu_sel_coeff  : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
                   alu_ctrl       : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
               END COMPONENT;
               SIGNAL in_sel_src     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL ram_sel_Wdata  : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL ram_write      : STD_LOGIC;
               SIGNAL ram_read       : STD_LOGIC;
               SIGNAL raddr_rst      : STD_LOGIC;
               SIGNAL raddr_add1     : STD_LOGIC;
               SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL alu_sel_input  : STD_LOGIC;
               SIGNAL alu_sel_coeff  : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
               SIGNAL alu_ctrl       : STD_LOGIC_VECTOR(2 DOWNTO 0);
               SIGNAL sample_in_buf     : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
               SIGNAL sample_in_rotate  : STD_LOGIC;
               SIGNAL sample_in_s       : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
               SIGNAL sample_out_val_s  : STD_LOGIC;
               SIGNAL sample_out_val_s2 : STD_LOGIC;
               SIGNAL sample_out_rot_s  : STD_LOGIC;
               SIGNAL sample_out_s      : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
               SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
               signal init_mem_done : std_logic;
             BEGIN
               IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW
                 GENERIC MAP (
                   tech        => tech,
                   Mem_use     => Mem_use,
                   Sample_SZ   => Sample_SZ,
                   Coef_SZ     => Coef_SZ,
                   Coef_Nb     => Coef_Nb,
-                  Coef_sel_SZ => Coef_sel_SZ)
+                  Coef_sel_SZ => Coef_sel_SZ,
+                  FILENAME    => FILENAME)
                 PORT MAP (
                   rstn           => rstn,
                   clk            => clk,
                   virg_pos       => virg_pos,
                   coefs          => coefs,
                   --CTRL
                   in_sel_src     => in_sel_src,
                   init_mem_done  => init_mem_done,  --TODO
                   ram_sel_Wdata  => ram_sel_Wdata,
                   ram_write      => ram_write,
                   ram_read       => ram_read,
                   raddr_rst      => raddr_rst,
                   raddr_add1     => raddr_add1,
                   waddr_previous => waddr_previous,
                   alu_sel_input  => alu_sel_input,
                   alu_sel_coeff  => alu_sel_coeff,
                   alu_ctrl       => alu_ctrl,
                   alu_comp       => "00",
                   --DATA
                   sample_in      => sample_in_s,
                   sample_out     => sample_out_s);
               IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
                 GENERIC MAP (
                   Coef_sel_SZ  => Coef_sel_SZ,
                   Cels_count   => Cels_count,
                   ChanelsCount => ChanelsCount)
                 PORT MAP (
                   rstn           => rstn,
                   clk            => clk,
                   sample_in_val  => sample_in_val,
                   sample_in_rot  => sample_in_rotate,
                   sample_out_val => sample_out_val_s,
                   sample_out_rot => sample_out_rot_s,
                   init_mem_done  => init_mem_done,  --TODO
                   in_sel_src     => in_sel_src,
                   ram_sel_Wdata  => ram_sel_Wdata,
                   ram_write      => ram_write,
                   ram_read       => ram_read,
                   raddr_rst      => raddr_rst,
                   raddr_add1     => raddr_add1,
                   waddr_previous => waddr_previous,
                   alu_sel_input  => alu_sel_input,
                   alu_sel_coeff  => alu_sel_coeff,
                   alu_ctrl       => alu_ctrl);
               -----------------------------------------------------------------------------
               -- SAMPLE IN
               -----------------------------------------------------------------------------
               loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
                 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
                   PROCESS (clk, rstn)
                   BEGIN  -- PROCESS
                     IF rstn = '0' THEN                  -- asynchronous reset (active low)
                       sample_in_buf(I, J) <= '0';
                     ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                       IF sample_in_val = '1' THEN
                         sample_in_buf(I, J) <= sample_in(I, J);
                       ELSIF sample_in_rotate = '1' THEN
                         sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
                       END IF;
                     END IF;
                   END PROCESS;
                 END GENERATE loop_all_chanel;
                 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
               END GENERATE loop_all_sample;
               -----------------------------------------------------------------------------
               -- SAMPLE OUT
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_out_val    <= '0';
                   sample_out_val_s2 <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   sample_out_val    <= sample_out_val_s2;
                   sample_out_val_s2 <= sample_out_val_s;
                 END IF;
               END PROCESS;
               chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN  -- PROCESS
                   IF rstn = '0' THEN                  -- asynchronous reset (active low)
                     sample_out_s2(ChanelsCount-1, I) <= '0';
                   ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                     IF sample_out_rot_s = '1' THEN
                       sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
                     END IF;
                   END IF;
                 END PROCESS;
               END GENERATE chanel_HIGH;
               chanel_more : IF ChanelsCount > 1 GENERATE
                 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
                   all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
                     PROCESS (clk, rstn)
                     BEGIN  -- PROCESS
                       IF rstn = '0' THEN            -- asynchronous reset (active low)
                         sample_out_s2(J-1, I) <= '0';
                       ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                         IF sample_out_rot_s = '1' THEN
                           sample_out_s2(J-1, I) <= sample_out_s2(J, I);
                         END IF;
                       END IF;
                     END PROCESS;
                   END GENERATE all_bit;
                 END GENERATE all_chanel;
               END GENERATE chanel_more;
               sample_out <= sample_out_s2;
             END ar_IIR_CEL_CTRLR_v2;

lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd +6 -3

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe PELLION
             --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY lpp;
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS
               GENERIC(
                 tech          : INTEGER := 0;
                 Mem_use       : INTEGER := use_RAM;
                 Sample_SZ     : INTEGER := 16;
                 Coef_SZ       : INTEGER := 9;
                 Coef_Nb       : INTEGER := 30;
-                Coef_sel_SZ   : INTEGER := 5
+                Coef_sel_SZ   : INTEGER := 5;
+                FILENAME      : STRING:= ""
                 );
               PORT(
                 rstn      : IN  STD_LOGIC;
                 clk        : IN  STD_LOGIC;
                 -- PARAMETER
                 virg_pos   : IN  INTEGER;
                 coefs      : IN  STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
                 -- CONTROL
                 in_sel_src    : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
                 --
                 init_mem_done  : out STD_LOGIC;
                 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
                 ram_write     : IN STD_LOGIC;
                 ram_read      : IN STD_LOGIC;
                 raddr_rst    : IN STD_LOGIC;
                 raddr_add1     : IN STD_LOGIC;
                 waddr_previous      : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
                 --
                 alu_sel_input : IN STD_LOGIC;
                 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
                 alu_ctrl      : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op,  MULT_with_clear_ADD, IDLE)
                 alu_comp      : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
                 -- DATA
                 sample_in  : IN  STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
                 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)
                 );
             END IIR_CEL_CTRLR_v2_DATAFLOW;
             ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLOW  OF IIR_CEL_CTRLR_v2_DATAFLOW IS
               COMPONENT RAM_CTRLR_v2
                 GENERIC (
                   tech       : INTEGER;
                   Input_SZ_1 : INTEGER;
-                  Mem_use    : INTEGER);
+                  Mem_use    : INTEGER;
+                  FILENAME   : STRING);
                 PORT (
                   rstn           : IN  STD_LOGIC;
                   clk            : IN  STD_LOGIC;
                   init_mem_done  : out STD_LOGIC;
                   ram_write      : IN  STD_LOGIC;
                   ram_read       : IN  STD_LOGIC;
                   raddr_rst      : IN  STD_LOGIC;
                   raddr_add1     : IN  STD_LOGIC;
                   waddr_previous : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   sample_in      : IN  STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
                   sample_out     : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
               END COMPONENT;
               SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
               SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
               SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
               SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
               SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
               SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0);
               SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0);
               SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0);
               SIGNAL alu_coef   : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0);
             BEGIN
               -----------------------------------------------------------------------------
               -- INPUT
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   reg_sample_in <=  (OTHERS => '0');
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   CASE in_sel_src IS
                     WHEN "00" => reg_sample_in <= reg_sample_in;
                     WHEN "01" => reg_sample_in <= sample_in;
                     WHEN "10" => reg_sample_in <= ram_output;
                     WHEN "11" => reg_sample_in <= alu_output;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- RAM + CTRL
               -----------------------------------------------------------------------------
               ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE
                            alu_output    WHEN ram_sel_Wdata = "01" ELSE
                            ram_output;
               RAM_CTRLR_v2_1: RAM_CTRLR_v2
                 GENERIC MAP (
                   tech       => tech,
                   Input_SZ_1 => Sample_SZ,
-                  Mem_use    => Mem_use)
+                  Mem_use    => Mem_use,
+                  FILENAME   => FILENAME)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   init_mem_done  => init_mem_done,
                   ram_write      => ram_write,
                   ram_read       => ram_read,
                   raddr_rst      => raddr_rst,
                   raddr_add1     => raddr_add1,
                   waddr_previous => waddr_previous,
                   sample_in      => ram_input,
                   sample_out     => ram_output);
               -----------------------------------------------------------------------------
               -- MAC_ACC
               -----------------------------------------------------------------------------
               -- Control : mac_ctrl (MAC_op,  MULT_with_clear_ADD, IDLE)
               -- Data In : mac_sample, mac_coef
               -- Data Out: mac_output
               alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output;
               coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE
                 coeff_in: IF I < Coef_Nb GENERATE
                   all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
                     arrayCoeff(I,J) <= coefs(Coef_SZ*I+J);
                   END GENERATE all_bit;
                 END GENERATE coeff_in;
                 coeff_null: IF I > (Coef_Nb -1) GENERATE
                   all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
                     arrayCoeff(I,J) <= '0';
                   END GENERATE all_bit;
                 END GENERATE coeff_null;
               END GENERATE coefftable;
               Coeff_Mux : MUXN
                 GENERIC MAP (
                   Input_SZ => Coef_SZ,
                   NbStage  => Coef_sel_SZ)
                 PORT MAP (
                   sel    => alu_sel_coeff,
                   INPUT  => arrayCoeff,
                   RES    => alu_coef_s);
               all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
                 alu_coef(J) <= alu_coef_s(J);
               END GENERATE all_bit;
               -----------------------------------------------------------------------------
               -- TODO : just for Synthesis test
               --PROCESS (clk, rstn)
               --BEGIN
               --  IF rstn = '0' THEN
               --    alu_coef <= (OTHERS => '0');
               --  ELSIF clk'event AND clk = '1' THEN
               --    all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP
               --      alu_coef(J) <= alu_coef_s(J);
               --    END LOOP all_bit;
               --  END IF;
               --END PROCESS;
               -----------------------------------------------------------------------------
               ALU_1: ALU
                 GENERIC MAP (
                   Arith_en   => 1,
                   Input_SZ_1 => Sample_SZ,
                   Input_SZ_2 => Coef_SZ,
                   COMP_EN    => 1)
                 PORT MAP (
                   clk   => clk,
                   reset => rstn,
                   ctrl  => alu_ctrl,
                   comp  => alu_comp,
                   OP1   => alu_sample,
                   OP2   => alu_coef,
                   RES   => alu_output_s);
               alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos);
               sample_out <= alu_output;
             END ar_IIR_CEL_CTRLR_v2_DATAFLOW;

lib/lpp/dsp/iir_filter/RAM_CEL.vhd +39 -8

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
+            USE ieee.std_logic_textio.ALL;
             USE IEEE.numeric_std.ALL;
+            LIBRARY std;
+            USE std.textio.ALL;
             ENTITY RAM_CEL IS
               GENERIC(
                 DataSz : INTEGER RANGE 1 TO 32 := 8;
-                abits  : INTEGER RANGE 2 TO 12 := 8);
+                abits  : INTEGER RANGE 2 TO 12 := 8;
+                FILENAME : string:= ""
+                );
               PORT(
                 WD           : IN  STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
                 RD           : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
                 WEN, REN     : IN  STD_LOGIC;
                 WADDR        : IN  STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
                 RADDR        : IN  STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
                 RWCLK, RESET : IN  STD_LOGIC
                 ) ;
             END RAM_CEL;
             ARCHITECTURE ar_RAM_CEL OF RAM_CEL IS
               CONSTANT VectInit : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0) := (OTHERS => '0');
               CONSTANT MAX      : INTEGER                             := 2**(abits);
               TYPE RAMarrayT IS ARRAY (0 TO MAX-1) OF STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
-              SIGNAL RAMarray : RAMarrayT := (OTHERS => VectInit);
               SIGNAL RD_int   : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
               SIGNAL RADDR_reg        :  STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
+              -- Read a *.hex file
+                impure function ReadMemFile(FileName : STRING) return RAMarrayT is
+                  file FileHandle       : TEXT open READ_MODE is FileName;
+                  variable CurrentLine  : LINE;
+                  variable TempWord     : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
+                  variable Result       : RAMarrayT    := (others => (others => '0'));
+                begin
+                  for i in 0 to MAX - 1 loop
+                    exit when endfile(FileHandle);
+                    readline(FileHandle, CurrentLine);
+                    hread(CurrentLine, TempWord);
+                    Result(i)    := TempWord;
+                  end loop;
+                  return Result;
+                end function;
+                impure function InitMem(FileName : STRING) return RAMarrayT is
+                    variable Result       : RAMarrayT    := (others => (others => '0'));
+                begin
+                    if FileName'length /= 0 then
+                        Result := ReadMemFile(FileName);
+                    end if;
+                    return Result;
+                end function;
+                SIGNAL RAMarray : RAMarrayT := InitMem(FILENAME);
             BEGIN
               RD_int <= RAMarray(to_integer(UNSIGNED(RADDR)));
               PROCESS(RWclk, reset)
               BEGIN
                 IF reset = '0' THEN
                   RD <= VectInit;
-                  rst : FOR i IN 0 TO MAX-1 LOOP
+            --      rst : FOR i IN 0 TO MAX-1 LOOP
-                    RAMarray(i) <= (OTHERS => '0');
+            --        RAMarray(i) <= (OTHERS => '0');
-                  END LOOP;
+            --      END LOOP;
                 ELSIF RWclk'EVENT AND RWclk = '1' THEN
-            --      IF REN = '0' THEN
                   RD <= RD_int;
-            --      END IF;
                   IF REN = '0' THEN
                     RADDR_reg <= RADDR;
                   END IF;
                   IF WEN = '0' THEN
                     RAMarray(to_integer(UNSIGNED(WADDR))) <= WD;
                   END IF;
                 END IF;
               END PROCESS;
             END ar_RAM_CEL;

lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd +3 -2

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@lpp.polytechnique.fr
             ----------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY lpp;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.general_purpose.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY RAM_CTRLR_v2 IS
               GENERIC(
                 tech       : INTEGER := 0;
                 Input_SZ_1 : INTEGER := 16;
-                Mem_use    : INTEGER := use_RAM
+                Mem_use    : INTEGER := use_RAM;
+                FILENAME   : STRING:= ""
                 );
               PORT(
                 rstn : IN STD_LOGIC;
                 clk  : IN STD_LOGIC;
                 -- ram init done
                 init_mem_done: out STD_LOGIC;
                 -- R/W Ctrl
                 ram_write : IN STD_LOGIC;
                 ram_read  : IN STD_LOGIC;
                 -- ADDR Ctrl
                 raddr_rst  : IN STD_LOGIC;
                 raddr_add1 : IN STD_LOGIC;
                 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
                 -- Data
                 sample_in  : IN  STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
                 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
                 );
             END RAM_CTRLR_v2;
             ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
               SIGNAL WD       : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
               SIGNAL RD       : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
               SIGNAL WEN, REN : STD_LOGIC;
               SIGNAL RADDR    : STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL WADDR    : STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL counter  : STD_LOGIC_VECTOR(7 DOWNTO 0);
               signal rst_mem_done_s : std_logic;
               signal ram_write_s : std_logic;
             BEGIN
               init_mem_done <= rst_mem_done_s;
               sample_out                <= RD(Input_SZ_1-1 DOWNTO 0) when rst_mem_done_s = '1' else (others => '0');
               WD(Input_SZ_1-1 DOWNTO 0) <= sample_in                 when rst_mem_done_s = '1' else (others => '0');
               ram_write_s               <= ram_write                 when rst_mem_done_s = '1' else '1';
               -----------------------------------------------------------------------------
               -- RAM
               -----------------------------------------------------------------------------
               memCEL : IF Mem_use = use_CEL GENERATE
                 WEN <= NOT ram_write_s;
                 REN <= NOT ram_read;
                 RAMblk : RAM_CEL
-                  GENERIC MAP(Input_SZ_1, 8)
+                  GENERIC MAP(Input_SZ_1, 8,FILENAME)
                   PORT MAP(
                     WD    => WD,
                     RD    => RD,
                     WEN   => WEN,
                     REN   => REN,
                     WADDR => WADDR,
                     RADDR => RADDR,
                     RWCLK => clk,
                     RESET => rstn
                     ) ;
               END GENERATE;
               memRAM : IF Mem_use = use_RAM GENERATE
                 SRAM : syncram_2p
                   GENERIC MAP(tech, 8, Input_SZ_1)
                   PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write_s, WADDR, WD);
               END GENERATE;
               -----------------------------------------------------------------------------
               -- RADDR
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   counter           <= (OTHERS => '0');
                   rst_mem_done_s    <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   if rst_mem_done_s = '0' then
                     counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
                   else
                     IF raddr_rst = '1' THEN
                       counter <= (OTHERS => '0');
                     ELSIF raddr_add1 = '1' THEN
                       counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
                     END IF;
                   end if;
                   if counter = x"FF" then
                     rst_mem_done_s <= '1';
                   end if;
                 END IF;
               END PROCESS;
               RADDR <= counter;
               -----------------------------------------------------------------------------
               -- WADDR
               -----------------------------------------------------------------------------
               WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter))   when rst_mem_done_s = '0' else
                        STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
                        STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
                        STD_LOGIC_VECTOR(UNSIGNED(counter));
             END ar_RAM_CTRLR_v2;

lib/lpp/dsp/iir_filter/iir_filter.vhd +4 -2

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@lpp.polytechnique.fr
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             PACKAGE iir_filter IS
             --===========================================================|
             --================A L U   C O N T R O L======================|
             --===========================================================|
               CONSTANT IDLE                : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
               CONSTANT MAC_op              : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
               CONSTANT MULT                : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
               CONSTANT ADD                 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
               CONSTANT clr_mac             : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
               CONSTANT MULT_with_clear_ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
             --____
             --RAM |
             --____|
               CONSTANT use_RAM : INTEGER := 1;
               CONSTANT use_CEL : INTEGER := 0;
             --===========================================================|
             --=============C O E F S ====================================|
             --===========================================================|
             --  create a specific type of data for coefs to avoid errors |
             --===========================================================|
               TYPE scaleValT IS ARRAY(NATURAL RANGE <>) OF INTEGER;
               TYPE samplT IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
               TYPE in_IIR_CEL_reg IS RECORD
                 config  : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 virgPos : STD_LOGIC_VECTOR(4 DOWNTO 0);
               END RECORD;
               TYPE out_IIR_CEL_reg IS RECORD
                 config : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 status : STD_LOGIC_VECTOR(31 DOWNTO 0);
               END RECORD;
               COMPONENT APB_IIR_CEL IS
                 GENERIC (
                   tech          : INTEGER := 0;
                   pindex        : INTEGER := 0;
                   paddr         : INTEGER := 0;
                   pmask         : INTEGER := 16#fff#;
                   pirq          : INTEGER := 0;
                   abits         : INTEGER := 8;
                   Sample_SZ     : INTEGER := 16;
                   ChanelsCount  : INTEGER := 6;
                   Coef_SZ       : INTEGER := 9;
                   CoefCntPerCel : INTEGER := 6;
                   Cels_count    : INTEGER := 5;
                   virgPos       : INTEGER := 7;
                   Mem_use       : INTEGER := use_RAM
                   );
                 PORT (
                   rst            : IN  STD_LOGIC;
                   clk            : IN  STD_LOGIC;
                   apbi           : IN  apb_slv_in_type;
                   apbo           : OUT apb_slv_out_type;
                   sample_clk     : IN  STD_LOGIC;
                   sample_clk_out : OUT STD_LOGIC;
                   sample_in      : IN  samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
                   sample_out     : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
                   CoefsInitVal   : IN  STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1')
                   );
               END COMPONENT;
               COMPONENT Top_IIR IS
                 GENERIC(
                   Sample_SZ     : INTEGER := 18;
                   ChanelsCount  : INTEGER := 1;
                   Coef_SZ       : INTEGER := 9;
                   CoefCntPerCel : INTEGER := 6;
                   Cels_count    : INTEGER := 5);
                 PORT(
                   reset      : IN  STD_LOGIC;
                   clk        : IN  STD_LOGIC;
                   sample_clk : IN  STD_LOGIC;
                   --       BP : in std_logic;
                   --       BPinput       :   in std_logic_vector(3 downto 0);
                   LVLinput   : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   INsample   : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
                   OUTsample  : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT IIR_CEL_CTRLR_v2
                 GENERIC (
                   tech          : INTEGER;
                   Mem_use       : INTEGER;
                   Sample_SZ     : INTEGER;
                   Coef_SZ       : INTEGER;
                   Coef_Nb       : INTEGER;
                   Coef_sel_SZ   : INTEGER;
                   Cels_count    : INTEGER;
-                  ChanelsCount  : INTEGER);
+                  ChanelsCount  : INTEGER;
+                  FILENAME      : STRING);
                 PORT (
                   rstn          : IN  STD_LOGIC;
                   clk            : IN  STD_LOGIC;
                   virg_pos       : IN  INTEGER;
                   coefs          : IN  STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
                   sample_in_val  : IN  STD_LOGIC;
                   sample_in      : IN  samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
                   sample_out_val : OUT  STD_LOGIC;
                   sample_out     : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
               END COMPONENT;
               COMPONENT IIR_CEL_CTRLR_v3
                 GENERIC (
                   tech         : INTEGER;
                   Mem_use      : INTEGER;
                   Sample_SZ    : INTEGER;
                   Coef_SZ      : INTEGER;
                   Coef_Nb      : INTEGER;
                   Coef_sel_SZ  : INTEGER;
                   Cels_count   : INTEGER;
                   ChanelsCount : INTEGER);
                 PORT (
                   rstn            : IN  STD_LOGIC;
                   clk             : IN  STD_LOGIC;
                   virg_pos        : IN  INTEGER;
                   coefs           : IN  STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
                   sample_in1_val  : IN  STD_LOGIC;
                   sample_in1      : IN  samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
                   sample_in2_val  : IN  STD_LOGIC;
                   sample_in2      : IN  samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
                   sample_out1_val : OUT STD_LOGIC;
                   sample_out1     : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
                   sample_out2_val : OUT STD_LOGIC;
                   sample_out2     : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
               END COMPONENT;
             --component  FilterCTRLR is
             --port(
             --    reset       :   in  std_logic;
             --    clk         :   in  std_logic;
             --    sample_clk  :   in  std_logic;
             --    ALU_Ctrl    :   out std_logic_vector(3 downto 0);
             --    sample_in   :   in  samplT;
             --    coef        :   out std_logic_vector(Coef_SZ-1 downto 0);
             --    sample      :   out std_logic_vector(Smpl_SZ-1 downto 0)
             --);
             --end component;
             --component  FILTER_RAM_CTRLR is
             --port(
             --    reset       :   in  std_logic;
             --    clk         :   in  std_logic;
             --    run         :   in  std_logic;
             --    GO_0        :   in  std_logic;
             --    B_A         :   in  std_logic;
             --    writeForce  :   in  std_logic;
             --    next_blk    :   in  std_logic;
             --    sample_in   :   in  std_logic_vector(Smpl_SZ-1 downto 0);
             --    sample_out  :   out std_logic_vector(Smpl_SZ-1 downto 0)
             --);
             --end component;
               COMPONENT IIR_CEL_CTRLR IS
                 GENERIC(
                   tech          : INTEGER := 0;
                   Sample_SZ     : INTEGER := 16;
                   ChanelsCount  : INTEGER := 1;
                   Coef_SZ       : INTEGER := 9;
                   CoefCntPerCel : INTEGER := 3;
                   Cels_count    : INTEGER := 5;
                   Mem_use       : INTEGER := use_RAM
                   );
                 PORT(
                   reset      : IN  STD_LOGIC;
                   clk        : IN  STD_LOGIC;
                   sample_clk : IN  STD_LOGIC;
                   sample_in  : IN  samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
                   sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
                   virg_pos   : IN  INTEGER;
                   GOtest     : OUT STD_LOGIC;
                   coefs      : IN  STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT RAM IS
                 GENERIC(
                   Input_SZ_1 : INTEGER := 8
                   );
                 PORT(WD                                           : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); RD : OUT
                 STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); WEN, REN : IN STD_LOGIC;
                 WADDR                                             : IN STD_LOGIC_VECTOR(7 DOWNTO 0); RADDR : IN
                 STD_LOGIC_VECTOR(7 DOWNTO 0); RWCLK, RESET        : IN STD_LOGIC
                       ) ;
               END COMPONENT;
             COMPONENT RAM_CEL is
                 generic(DataSz        :   integer range 1 to 32 := 8;
-                        abits         :   integer range 2 to 12 := 8);
+                        abits         :   integer range 2 to 12 := 8;
+                        FILENAME      :   STRING:="");
                 port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out
                     std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic;
                     WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in
                     std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic
                     ) ;
             end COMPONENT;
               COMPONENT RAM_CEL_N
                 GENERIC (
                   size : INTEGER);
                 PORT (
                   WD           : IN  STD_LOGIC_VECTOR(size-1 DOWNTO 0);
                   RD           : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0);
                   WEN, REN     : IN  STD_LOGIC;
                   WADDR        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                   RADDR        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                   RWCLK, RESET : IN  STD_LOGIC);
               END COMPONENT;
               COMPONENT IIR_CEL_FILTER IS
                 GENERIC(
                   tech          : INTEGER := 0;
                   Sample_SZ     : INTEGER := 16;
                   ChanelsCount  : INTEGER := 1;
                   Coef_SZ       : INTEGER := 9;
                   CoefCntPerCel : INTEGER := 3;
                   Cels_count    : INTEGER := 5;
                   Mem_use       : INTEGER := use_RAM);
                 PORT(
                   reset      : IN  STD_LOGIC;
                   clk        : IN  STD_LOGIC;
                   sample_clk : IN  STD_LOGIC;
                   regs_in    : IN  in_IIR_CEL_reg;
                   regs_out   : IN  out_IIR_CEL_reg;
                   sample_in  : IN  samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
                   sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
                   GOtest     : OUT STD_LOGIC;
                   coefs      : IN  STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT RAM_CTRLR2 IS
                 GENERIC(
                   tech       : INTEGER := 0;
                   Input_SZ_1 : INTEGER := 16;
                   Mem_use    : INTEGER := use_RAM
                   );
                 PORT(
                   reset      : IN  STD_LOGIC;
                   clk        : IN  STD_LOGIC;
                   WD_sel     : IN  STD_LOGIC;
                   Read       : IN  STD_LOGIC;
                   WADDR_sel  : IN  STD_LOGIC;
                   count      : IN  STD_LOGIC;
                   SVG_ADDR   : IN  STD_LOGIC;
                   Write      : IN  STD_LOGIC;
                   GO_0       : IN  STD_LOGIC;
                   sample_in  : IN  STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
                   sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT APB_IIR_Filter IS
                 GENERIC (
                   tech          : INTEGER := 0;
                   pindex        : INTEGER := 0;
                   paddr         : INTEGER := 0;
                   pmask         : INTEGER := 16#fff#;
                   pirq          : INTEGER := 0;
                   abits         : INTEGER := 8;
                   Sample_SZ     : INTEGER := 16;
                   ChanelsCount  : INTEGER := 1;
                   Coef_SZ       : INTEGER := 9;
                   CoefCntPerCel : INTEGER := 6;
                   Cels_count    : INTEGER := 5;
                   virgPos       : INTEGER := 3;
                   Mem_use       : INTEGER := use_RAM
                   );
                 PORT (
                   rst            : IN  STD_LOGIC;
                   clk            : IN  STD_LOGIC;
                   apbi           : IN  apb_slv_in_type;
                   apbo           : OUT apb_slv_out_type;
                   sample_clk_out : OUT STD_LOGIC;
                   GOtest         : OUT STD_LOGIC;
                   CoefsInitVal   : IN  STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1')
                   );
               END COMPONENT;
             END;

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